Indutores Ativos são circuitos que quando utilizados se mostram como uma opção viável para melhorar o aproveitamento de área do chip e o fator de qualidade do indutor, comparado com indutor passivo, além de possibilitar o ajuste de parâmetros. Neste trabalho foram estudadas três topologias e abordagens encontradas na literatura para indutores ativos: indutor ativo simples, indutor ativo cascode, indutor ativo com resistência de realimentação. Propomos uma técnica para garantir que o indutor ativo não apresente pólos com parte real positiva, quando conectado a um circuito RC externo, através do cancelamento entre um pólo e um zero. Propomos também uma nova abordagem de projeto para a topologia indutor ativo com resistência de realimentação a qual chamamos de indutor ativo com baixa resistência de realimentação. Para estudo de aplicabilidade foi projetado um LNA (Low Noise Amplifier) utilizando a abordagem de projeto proposta. O amplificador deve atender requisitos de ganho, frequência de operação, impedância de entrada, consumo de potência, figura de ruído além de estabilidade para cargas de saída (pólos com parte real sempre positiva), utilizando o indutor ativo com baixa resistência de realimentação. / Active inductors are circuits that when used prove to be a viable option to improve chip area usage and the inductor\'s quality factor, compared to the passive inductor, while also allowing parameter adjustment. This work studies three topologies and approaches found in literature for active inductors: simple active inductor, cascode active inductor, active inductor with feedback resistance. We propose a technique to guarantee that the active inductor doesn\'t present poles with a positive real part, when connected to an external RC circuit, through cancelling between a pole and a zero. We also propose a new project approach for the topology of the active inductor with feedback resistance which we call low feedback resistance active inductor. To assess the applicability, a LNA (Low Noise Amplifier) was projected using the proposed project approach. The amplifier must meet the requirements regarding gain, operation frequency, input impedance, power consumption, noise figure and also stability for output loads (poles with an always negative real part), using the low feedback resistance active inductor.

Indutores Ativos são circuitos que quando utilizados se mostram como uma opção viável para melhorar o aproveitamento de área do chip e o fator de qualidade do indutor, comparado com indutor passivo, além de possibilitar o ajuste de parâmetros. Neste trabalho foram estudadas três topologias e abordagens encontradas na literatura para indutores ativos: indutor ativo simples, indutor ativo cascode, indutor ativo com resistência de realimentação. Propomos uma técnica para garantir que o indutor ativo não apresente pólos com parte real positiva, quando conectado a um circuito RC externo, através do cancelamento entre um pólo e um zero. Propomos também uma nova abordagem de projeto para a topologia indutor ativo com resistência de realimentação a qual chamamos de indutor ativo com baixa resistência de realimentação. Para estudo de aplicabilidade foi projetado um LNA (Low Noise Amplifier) utilizando a abordagem de projeto proposta. O amplificador deve atender requisitos de ganho, frequência de operação, impedância de entrada, consumo de potência, figura de ruído além de estabilidade para cargas de saída (pólos com parte real sempre positiva), utilizando o indutor ativo com baixa resistência de realimentação. / Active inductors are circuits that when used prove to be a viable option to improve chip area usage and the inductor\'s quality factor, compared to the passive inductor, while also allowing parameter adjustment. This work studies three topologies and approaches found in literature for active inductors: simple active inductor, cascode active inductor, active inductor with feedback resistance. We propose a technique to guarantee that the active inductor doesn\'t present poles with a positive real part, when connected to an external RC circuit, through cancelling between a pole and a zero. We also propose a new project approach for the topology of the active inductor with feedback resistance which we call low feedback resistance active inductor. To assess the applicability, a LNA (Low Noise Amplifier) was projected using the proposed project approach. The amplifier must meet the requirements regarding gain, operation frequency, input impedance, power consumption, noise figure and also stability for output loads (poles with an always negative real part), using the low feedback resistance active inductor.

<p>This is a part of the project “Radio telescope system” working at 1.42 GHz, which includes designing of patch antenna and LNA. The main objective of this thesis is to design a two stage low noise amplifier for a radio telescope system, working at the frequency 1.42 GHz. Finally our aim is to design a two stage LNA, match, connect and test together with patch antenna to reduce</p><p>the system complexity and signal loss.</p><p>The requirements to design a two stage low noise amplifier (LNA) were well studied, topics including RF basic theory, layout and fabrication of RF circuits. A number of tools are available to design and simulate low noise amplifiers but our simulation work was done using advanced design system (ADS 2004 A). The design process includes selection of a proper device, stability check of the device, biasing, designing of matching networks and layout of total design and fabrication. A lot of time has been</p><p>spent on designing of impedance matching network, fabrication and testing of the design circuits and finally a two stage low noise amplifier (LNA) was designed. After the fabrication work, the circuits were tested by the spectrum analyzer in between 9 KHz to 25 GHz frequency range. Finally the resulting noise figure 0.299 dB and gain 24.25 dB are obtained from the simulation.</p><p>While measuring the values from the fabricated circuit board, we found that bias point is not stable due to self oscillations in the amplifier stages at lower frequencies like 149 MHz for first stage and 355 MHz for second stage.</p>

IEEE 802.15 High Rate Alternative PHY task group (TG3a) is working to define a protocol for Wireless Personal Area Networks (WPANs) which makes it possible to attain data rates of greater than 110Mbps. Ultra Wideband (UWB) technology utilizing frequency band of 3.168 GHz – 10.6 GHz is an emerging solution to this with data rates of 110, 200 and 480 Mbps. Initially, UWB mode I devices using only 3.168 GHz – 4.752 GHz have been proposed. Low Noise Amplifier (LNA) and I-Q mixers are key components constituting the RF front-end. Performance of these blocks is very critical to the overall performance of the receiver. In general, main considerations for the LNA are low noise, 50 broadband input matching, high gain with maximum flatness and good linearity. For the mixers, it is essential to attain low flicker noise performance coupled with good conversion gain. Proposed LNA architecture is a derivative of inductive source degenerated topology. Broadband matching at the LNA output is achieved using LC band-pass filter. To obtain high gain with maximum flatness, an LC band-pass filter is used at its output. Proposed LNA achieved a gain of 15dB, noise figure of less than 2.6dB and IIP3 of more than -7dBm. Mixer is a modified version of double balanced Gilbert cell topology where both I and Q channel mixers are merged together. Frequency response of each sub-band is matched by using an additional inductor, which further improves the noise figure and conversion gain. Current bleeding scheme is used to further reduce the low frequency noise. Mixer achieves average conversion gain of 14.5dB, IIP3 more than 6dBm and Double Side Band (DSB) noise figure less than 9dB. Maximum variation in conversion gain is desired to be less than 1dB. Both LNA and mixers are designed to be fabricated in TSMC 0.18µm CMOS technology.

The CDMA standard operating over the wireless environment along with various other wireless standards places stringent specifications on the RF Front end. Due to possible large interference signal tones at the receiver end along with the carrier, the Low Noise Amplifier (LNA) is expected to provide high linearity, thus preventing the intermodulation tones created by the interference signal from corrupting the carrier signal. The research focuses on designing a novel LNA which achieves high linearity without sacrificing any of its specifications of gain and Noise Figure (NF). The novel LNA proposed achieves high linearity by canceling the IM3 tones in the main transistor in both magnitude and phase using the IM3 tones generated by an auxiliary transistor. Extensive Volterra series analysis using the harmonic input method has been performed to prove the concept of third harmonic cancellation and a design methodology has been proposed. The LNA has been designed to operate at 900MHz in TSMC 0.35um CMOS technology. The LNA has been experimentally verified for its functionality. Linearity is usually measured in terms of IIP3 and the LNA has an IIP3 of +21dBm, with a gain of 11 dB, NF of 3.1 dB and power consumption of 22.5 mW.

This is a part of the project “Radio telescope system” working at 1.42 GHz, which includes designing of patch antenna and LNA. The main objective of this thesis is to design a two stage low noise amplifier for a radio telescope system, working at the frequency 1.42 GHz. Finally our aim is to design a two stage LNA, match, connect and test together with patch antenna to reduce the system complexity and signal loss. The requirements to design a two stage low noise amplifier (LNA) were well studied, topics including RF basic theory, layout and fabrication of RF circuits. A number of tools are available to design and simulate low noise amplifiers but our simulation work was done using advanced design system (ADS 2004 A). The design process includes selection of a proper device, stability check of the device, biasing, designing of matching networks and layout of total design and fabrication. A lot of time has been spent on designing of impedance matching network, fabrication and testing of the design circuits and finally a two stage low noise amplifier (LNA) was designed. After the fabrication work, the circuits were tested by the spectrum analyzer in between 9 KHz to 25 GHz frequency range. Finally the resulting noise figure 0.299 dB and gain 24.25 dB are obtained from the simulation. While measuring the values from the fabricated circuit board, we found that bias point is not stable due to self oscillations in the amplifier stages at lower frequencies like 149 MHz for first stage and 355 MHz for second stage.

Low Noise Amplifiers (LNAs) are one of the most important components found in some of the radio receivers used in radio astronomy. A good LNA should simultaneously possess both a gain in excess of 25\,dB and as low a noise contribution as possible. This is because the gain is used to suppress the noise contribution of the subsequent components but the noise generated by the LNA adds directly to the noise of the overall receiver. The work presented in this thesis aimed to further enhance the noise performance through a variety of techniques with the aim of applying these techniques to the study of the polarisation of the Cosmic Microwave Background. One particular technique investigated was to cool the LNAs beyond the standard 20\,K typically used in experiments to 2\,K. In doing so it was found that the noise performance increased by between 20 and 30\% depending on the amplifier. Another technique investigated involved uniting the two technologies (MICs and MMIC) used in LNA fabrication to lower the noise performance of the LNA. Such an LNA, known as a T+MMIC LNA was successfully developed and possessed an average noise temperature of 9.4\,K and a gain in excess of 40\,dB for a 27-33\,GHz bandwidth at 8\,K physical temperature. Potential ``in field'' applications for these technologies are discussed, and a design for a variant of the T+MMIC LNA that utilises both of these technologies is presented. This particular LNA with a predicted average noise temperature of 6.8\,K for a 26-36\,GHz bandwidth, would if fabricated successfully represent the lowest noise Ka-band LNA ever reported.

The need for low cost and low size radiometers have encouraged many to look at the implementation of radiometers using MMICs. Compared to their waveguide counterparts, radiometers implemented with MMICs significantly reduce the size and weight of the radiometer, while still maintaining satisfactory electrical performance at millimeter wave frequencies. Utilizing MMICs can also help in significantly lowering the noise temperature of the radiometer, specifically, metamorphic high electron-mobility transistors (mHEMT) have demonstrated very low noise, high gain performance and comparably low cost. This thesis is focused on designing a combined switch and low noise amplifier IC at 36.5 GHz that lowers the radiometer noise temperature while allowing for an accurate calibration. The measured gain from straight and 90 degree input of the switch-LNA, at 36.5 GHz, was 6.6 dB and 7.1 dB, respectively. Likewise, the noise figure of the MMIC was 3.8 dB and 3.3 dB, respectively. The mHEMT implemented SPDT switch has a measured insertion loss, at 36.5 GHz, of 1.3 dB and 0.88 dB with isolation of 25 dB and 36 dB, respectively. The calculated temperature sensitivity based on measured temperature variations was 0.273 K at 36 GHz.

An ultra-low noise two-stage LNA design for cellular basestations using CMOS is proposed in this thesis work.  This thesis is divided into three parts. First, a literature survey which intends to bring an idea on the types of LNAs available and their respective outcomes in performances, thereby analyze how each design provides different results and is used for different applications. In the second part, technology comparison for 0.12µm, 0.18µm, and 0.25µm technologies transistors using the IBM foundry PDKs are made to analyze which device has the best noise performance. Finally, in the third phase bipolar and CMOS-based two-stage LNAs are designed using IBM 0.12µm technology node, decided from the technology comparison. In this thesis a two-stage architecture is used to obtain low noise figure, high linearity, high gain, and stability for the LNA. For the bipolar design, noise figure of 0.6dB, OIP3 of 40.3dBm and gain of 26.8dB were obtained. For the CMOS design, noise figure of 0.25dB, OIP3 of 46dBm and gain of 26dB were obtained. Thus, the purpose of this thesis is to analyze the LNA circuit in terms of design, performance, application and various other parameters. Both designs were able to fulfill the design goals of noise figure &lt; 1 dB, OIP3 &gt; 40 dBm, and gain &gt;18 dB.

Master of Science / Department of Electrical and Computer Engineering / William B. Kuhn / This thesis elaborates on the theory and art of the design of two key RF radio hardware subsystems: analog Frequency Dividers and Low Noise Amplifiers (LNAs). Specifically, the design and analysis of two Injection Locked Frequency Dividers (ILFDs), one Regenerative Frequency Divider (RFD), and two different LNAs are documented. In addition to deriving equations for various performance metrics and topology-specific optimization criterion, measurement data and software simulations are presented to quantify several parameters of interest. Also, a study of the design of LNAs is discussed, based on three “regimes:” impedance matching, transconductance-boosting, and active noise cancelling (ANC). For the ILFDs, a study of injection-locked synchronization and phase noise reduction is offered, based on previous works. As the need for low power, high frequency radio devices continues to be driven by the mobile phone industry, Frequency Dividers that are used as prescalars in phase locked loop frequency synthesizers (PLLs) must too become capable of operation at higher frequencies while consuming little power. Not only should they be low power devices, but a wide “Locking Range” (LR) is also desired. The LR is the bandwidth of signals that a Frequency Divider is capable of dividing. As such, this thesis documents the design and analysis of two ILFDs: a Tail-ILFD and a Quench-ILFD. Both of these ILFDs are implemented on the same oscillator circuit, which consumes 2.28 mW, nominally. Measurements of the Tail and Quench-ILFDs’ LRs are plotted, including one representing the Quench-ILFD operating at “very low” power. Also, an RFD is detailed in this thesis, which consumes 410 μW. This thesis documents Locking Ranges for the Tail and Quench-ILFDs of 12% and 3.7% of 6.4 GHz respectively, during nominal operation. In “very low” power mode, the Quench-ILFD has a LR of 4.8% while consuming 219.6 μW of power. For the RFD, simulations report a LR of 16.7% while consuming 410 μW. Recently in 2011, a wideband LNA topology by Nozahi et al., which employs Partial Noise Cancelling (PNC) of the thermal noise generated by active devices, was presented and claimed to achieve a minimum and maximum NF of 1.4 dB and 1.7 dB (from 100 MHz to 2.3 GHz), while consuming 18 mW from a 1.8 V supply. This thesis details the theory, design, and simulation results of a narrowband version of this PNC LNA. In order to compare the largesignal performance of this narrowband LNA to that of a well-known implementation, an LNA employing inductive source-degeneration (referred to as a “S-L LNA”) is designed and analyzed through simulation. The PNC LNA operates at a frequency of 2.3 GHz while the S-L LNA operates at 2.8 GHz. Simulations report a NF of 1.76 dB for the PNC LNA and 2.3 dB for the SL LNA, at their respective operating frequencies. Both LNAs consume roughly 15 mW of quiescent power from a 1.8 V supply. Lastly, a case for the suspected design and layout faults, which caused fabricated versions of the RFD and two LNAs documented in this thesis to fail, is presented. First, measurements of the two LNAs are shown, which display the input impedance of the S-L LNA and the s₂₁ responses for both. Then, general layout concerns are addressed, followed by topology-specific circuit design flaws.