Linköpings Universitet och Acreo AB i Norrköping bedriver ett forskningssamarbete rörande organisk elektrokemisk elektronik och det man kallar papperselektronik. Målet på Acreo är att kunna trycka denna typ av elektronik med snabba trycktekniker så som offset- eller flexotryck. Idag görs de flesta demonstratorer och prototyper, baserade på denna typ av elektrokemisk elektronik, med manuella och subtraktiva mönstringsmetoder. Det skulle vara intressant att hitta fler verktyg och automatiserade tekniker som kan underlätta detta arbete. Målet med detta examensarbete har varit att utvärdera vilken potential bläckstråleteknik respektive screentryck har som tillverkningsmetoder för organiska elektrokemiska elektroniksystem samt att jämföra de båda teknikernas för- och nackdelar. Vad gäller bläckstråletekniken, så ingick även i uppgiften att modifiera en bläckstråleskrivare avsedd för kontor/hemmabruk för att möjliggöra tryckning av de två grundläggande materialen inom organisk elektrokemisk elektronik - den konjugerade polymeren PEDOT och en elektrolyt. I denna uppsats rapporteras om hur en procedur för produktion av elektrokemisk elektronik har utvecklats. Världens första elektrokemiska transistor som producerats helt med bläckstråleteknik presenteras tillsammans med fullt fungerande implementeringar i logiska kretsar. Karaktärisering av filmer, komponenter och kretsar som producerats med bläckstråle- och screentrycksteknik har legat till grund för den utvärdering och jämförelse som har gjorts av teknikerna. Resultaten ser lovande ut och kan motivera vidare utveckling av bläckstrålesystem för produktion av prototyper och mindre serier. En kombination av de båda nämnda teknikerna är också ett tänkbart alternativ för småskalig tillverkning. / Linköping University and the research institute Acreo AB in Norrköping are in collaboration conducting research on organic electrochemical electronic devices. Acreo is pushing the development of high-speed reel-to-reel printing of this type of electronics. Today, most demonstrators and prototypes are made using manual, subtractive patterning methods. More tools, simplifying this work, are of interest. The purpose of this thesis work was to evaluate the potential of both inkjet and screen printing as manufacturing tools of electrochemical devices and to conduct a comparative study of these two additive patterning technologies. The work on inkjet printing included the modification of a commercially available desktop inkjet printer in order to print the conjugated polymer PEDOT and an electrolyte solution - these are the two basic components of organic electrochemical devices. For screen printing, existing equipment at Acreo AB was employed for device production. In this report the successful development of a simple system and procedure for the inkjet printing of organic electrochemical devices is described. The first all-inkjet printed electrochemical transistor (ECT) and fully functional implementations of these ECTs in printed electrochemical logical circuits are presented. The characterization of inkjet and screen printed devices has, along with an evaluation of how suitable the two printing procedures are for prototype production, been the foundation of the comparison of the two printing technologies. The results are promising and should encourage further effort to develop a more complete and easily controlled inkjet system for this application. At this stage of development, a combination of the two technologies seems like an efficient approach.

In this study, delay-insensitive asynchronous circuit design style has been adopted to systolic array architectures to exploit the benefits of both techniques for improved throughput. A delay-insensitivity verification analysis method employing symbolic delays is proposed for bit-level pipelined asynchronous circuits. The proposed verification method allows datadependent early output evaluation to co-exist with robust delay-insensitive circuit behavior in pipelined architectures such as systolic arrays. Regardless of the length of the pipeline, delay-insensitivity verification of a systolic array with early output evaluation paths in onedimension is reduced to analysis of three adjacent systoles for eight possible early/late output evaluation scenarios. Analyzing both combinational and sequential parts concurrently, delay-insensitivity violations are located and corrected at structural level, without diminishing the early output evaluation benefits. Since symbolic delays are used without imposing any timing constraints on the environment / the method is technology independent and robust against all physical and environmental variations. To demonstrate the verification method, adders are selected for being at the core of data processing systems. Two asynchronous adder topologies in the delay-insensitive dual-rail threshold logic style, having data-dependent early carry evaluation paths, are converted into bit-level pipelined systolic arrays. On these adders, data-dependent delay-insensitivity violations are detected and resolved using the proposed verification technique. The modified adders achieved the targeted O(log2n) average completion time and -as a result of bit-level pipelining- nearly constant throughput against increased bit-length. The delay-insensitivity verification method could further be extended to handle more early output evaluation paths in multi-dimension.

The primary metrics associated with a logic gate's performance are speed, power, and area. We define a gate as a specific CMOS transistor level implementation of a particu- lar boolean function in a specific fabrication technology at a constant rail voltage, constant length, and where the ratio of any two transistor widths are constant. Asking how fast a gate switches then is highly situational; it changes with load capacitance, choice of inputs, input slew rate, and the size of the gate. Predicting how much energy the gate consumes depends on the time frame, how many times the gate has switched in this time frame, input selection, input slew rate, load capacitance, and gate width. Logical Effort (LE) predicts gate delay with a simple linear equation: d = t(gh+p). Where g and p are gate and input dependent parameters independent of load size and gate size, and h is the ratio of output ca- pacitance to input capacitance (directly related to gate width), and t is a process dependent conversion factor. The product, gh, then is the delay associated with driving a subsequent gate, and p is the delay of the gate driving itself. The prediction ignores input slew rate and the linear dependence fails for very large values of h, but for input slew rates on the same order as the output slew rate, and for reasonable fan-outs, LE provides remarkably accurate predictions of gate switching time. The methodology goes on to solve for the widths nec- essary for each gate in an arbitrary logic path to minimize delay. Designs can quickly be compared, analyzed and optimized. By breaking down delay into components, one is able to intuitively choose better logic implementations, if parasitic delay is dominating, often a better implementation is one with smaller fan-in gates and less logic depth, if effort delay is dominating then then higher logic depth can lead to faster results. What the method does not do is predict the power consumption ramifications of all of these choices. What about minimizing power on non-critical paths, for instance? To our knowledge, no methodology exists to predict power consumption in a similar fashion. We propose a power prediction methodology, Logical Power (LP), compatible with LE that breaks down power consumption into dynamic, static, and short-circuit com- ponents with linear equations dependent on h. This would allow a compact and efficient way to characterize a gate that scales with its environment, as well as to allow designers optimizing with LE to consider not only the speed ramifications of individual gate sizings but power as well. For instance given a target path delay higher than the theoretical mini- mum predicted by LE, sizings could be chosen with LE and LP that minimize power that still result in meeting the target delay. The other major contribution of this work is a new short-circuit power measurement technique for simulation that more accurately distinguishes between short-circuit and the parasitic portions of dynamic power in total active power dissipation than all known tech- niques.

Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, September 1990. / Thesis Advisor(s): Lee, Chin-Hwa. Second Reader: Butler, Jon T. "September 1990." Description based on title screen as viewed on December 29, 2009. DTIC Identifier(s): Computerized simulation, computer aided design, logic circuits, subroutines, theses, integrated circuits. Author(s) subject terms: VHDL, costfunction, hardware description language. Includes bibliographical references (p. 77). Also available in print.

Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009. / Committee Chair: Cressler, John; Committee Member: Deo, Chaitanya; Committee Member: Doolittle, Alan; Committee Member: Keezer, David; Committee Member: May, Gary; Committee Member: Papapolymerou, John. Part of the SMARTech Electronic Thesis and Dissertation Collection.

No description available.

No description available.

The development of cost-effective circuits is primarily a matter of economy. To achieve it, design errors and circuit flaws must be eliminated during the design process. To this end, considerable effort must be put into all phases of the design cycle. Effective CAD tools are essential for the production of high-performance digital systems. This thesis describes a CAD tool called LOVERD, which consists of ATPG, fault simulation, design verification and diagnosis. It uses test patterns, developed to detect single stuck-at faults in the gate-level implementation, to compare the results of the functional level description and its gate-level implementation. Whenever an error is detected, the logic diagnosis tool can be used to provide useful information to designers. It is shown that certain types of design errors in combinational logic circuits can be detected and allocated by LOVERD efficiently.

No description available.

No description available.