A program has been written for the Texas Instrument's TI-59 hand-held calculator implementing the Quine-McCluskey minimization method for logic circuit design. This program is contained on multiple magnetic cards and provides the user with the capability for combinational logic minimization of circuit design problems containing up to six variables.

A software interface between a firmware documentation system and a logic simulator named TEGAS-51 is described. The interface accepts PALASM2 inputs for PAL files. The output is an ASCII file which defines the firmware parts in TEGAS-5 format. Modules are written in FORTRAN and command routines are written in DCL on VAX 11/780 machines. No system calls are required, so portability is maintained. Limitations include the inability to load two different programs in identical firmware parts on the same design, but this can be overcome. 1GE/Calma Corporation trademark 2MMI Corporation trademark

A new CAD tool, aimed at providing a simple graphical interface to the chip-level simulation system GSP, has been developed. It consists of pre and post-processors allowing the user to model systems using pre-defined library as well as custom modules and to view their outputs in a more familiar waveform-like display. The actual coding of the models is still the responsibility of the user; the pre-processor enables the net list specification as well as the input of simulator commands in a menu-based approach. Facilities for simple data checking as well as hardcopy generation of system models has been provided. Developed to run on the IBM PC, this system also integrates the three discrete parts of GSP, viz. GSPASM, GSPLINK and GSPSIM along with the graphics processors into a single menu-based system. / M.S.

The thesis presents an analysis of FET based Multiple Valued Logic circuits. The circuit analysis program SPICE2 was used to analyze these circuits. A description of device modelling as done by SPICE2 is included in the beginning of the thesis. Techniques to implement MVL circuits using simple threshold circuits as building blocks are outlined. The two principal methods of achieving different switching voltages, namely, changing the device threshold and the device transconductance, for these threshold circuits are discussed. A comparative study of these two methods from a theoretical and practical viewpoint is included. Several MOSFET based MVL circuits are developed and an explanation of their operation is also given. / Master of Science

No description available.

Call number: LD2668 .T4 1956 K31 / Master of Science

Ho Chi Kit. / Thesis submitted in: September 2005. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2006. / Includes bibliographical references (leaves 66-70). / Abstracts in English and Chinese. / Chapter 1 --- Introduction --- p.9 / Chapter 1.1 --- Aims and Contribution --- p.9 / Chapter 1.2 --- Dissertation Overview --- p.10 / Chapter 2 --- Literature Review --- p.11 / Chapter 2.1 --- ATPG-based Alternative Wiring --- p.11 / Chapter 2.1.1 --- Post-Layout Logic Restructuring for Performance Optimization --- p.11 / Chapter 2.1.2 --- Timing Optimization by an Improved Redundancy Addition and Removal Technique --- p.12 / Chapter 2.2 --- Logic Synthesis --- p.13 / Chapter 2.2.1 --- Local Logic Substitution Algorithm for Post-Layout Re-synthesis --- p.13 / Chapter 2.2.2 --- SIS: A System for Sequential Circuit Synthesis --- p.13 / Chapter 2.3 --- Fanout Optimization --- p.14 / Chapter 2.3.1 --- Efficient Global Fanout Optimization Algorithms --- p.14 / Chapter 2.3.2 --- Fanout Optimization under a Submicron Transistor-Level Delay Model --- p.15 / Chapter 2.4 --- Genetic Algorithm --- p.15 / Chapter 2.4.1 --- Scalability and Efficiency of Genetic Algorithms for Geometrical Applications --- p.15 / Chapter 2.4.2 --- "The Gambler's Ruin Problem, Genetic Algorithms, and the Sizing of Populations" --- p.16 / Chapter 3 --- Background --- p.18 / Chapter 3.1 --- Redundancy Addition and Removal --- p.18 / Chapter 3.2 --- REWIRE --- p.19 / Chapter 4 --- Standard Cell Logic Synthesis --- p.20 / Chapter 4.1 --- Introduction --- p.20 / Chapter 4.2 --- Objective --- p.22 / Chapter 4.3 --- Use Standard Patterns for Logic Synthesis --- p.22 / Chapter 4.4 --- Optimization --- p.25 / Chapter 4.5 --- Proposed Scheme --- p.26 / Chapter 4.6 --- Criteria for Selection of Wire --- p.28 / Chapter 4.7 --- Experimental Results --- p.30 / Chapter 4.8 --- Conclusion --- p.34 / Chapter 5 --- Theory on GBAW --- p.35 / Chapter 5.1 --- Introduction --- p.35 / Chapter 5.2 --- Notations and Definitions --- p.36 / Chapter 5.3 --- Minimality and Duality --- p.37 / Chapter 5.4 --- Topological Property of GBAW patterns --- p.41 / Chapter 5.5 --- Experimental Results --- p.47 / Chapter 5.6 --- Conclusion --- p.51 / Chapter 6 --- Multi-way GBAW Partitioning Scheme --- p.52 / Chapter 6.1 --- Introduction --- p.52 / Chapter 6.2 --- Algorithm of GBAW Partitioning Scheme --- p.55 / Chapter 6.3 --- Experimental Results --- p.56 / Chapter 6.4 --- Conclusion --- p.63 / Chapter 7 --- Conclusion --- p.64 / Bibliography --- p.66

Continued aggressive scaling of electronic technology poses obstacles for maintaining circuit reliability. To this end, analysis of reliability is of increasing importance. Large scale number of inputs and gates or correlations of failures render such analysis computationally complex. This paper presents an accurate framework for reliability analysis of logic circuits, while inherently handling reconvergent fan-out without additional complexity. Combinational circuits are modeled stochastically as Discrete-Time Markov Chains, where propagation of node logic levels and error probability distributions through circuitry are used to determine error probabilities at nodes in the circuit. Model construction is scalable, as it is done so on a gate-by-gate basis. The stochastic nature of the model lends itself to allow various properties of the circuit to be formally analyzed by means of steady-state properties. Formal verifying the properties against the model can circumvent strenuous simulations while exhaustively checking all possible scenarios for given properties. Small combinational circuits are used to explain model construction, properties are presented for analysis of the system, more example circuits are demonstrated, and the accuracy of the method is verified against an existing simulation method.

Graduation date: 1991

Graduation date: 1991