This Thesis explores building low cost and reliable portable laboratory infrastructure platform for Logic Design, methods for allowing access to modern test equipment via the internet, and issues related to academic integrity. A comprehensive engineering education, per ABET, requires an equal emphasis on both lecture and laboratory components. The laboratory experience builds and establishes a foundation of skills and experiences that the student cannot obtain through any other means. The laboratory must use modern, pertinent methods and techniques including the use of appropriate tools. This is especially true when it comes to test equipment. Engineering students require and deserve training on and access to modern test equipment in order to obtain better career opportunities. However, providing access to modern and relevant labs requires a significant budget commitment. One way to extend current budgets is to adopt the growing concept of “remote labs.” This approach allows higher utilization of existing (and costly) equipment, it improves an institution’s Return on Investment (ROI), and also can be used to meet the needs of students’ complicated schedules, especially in the case of a “commuter campus,” where a majority of students live off campus. By developing remote labs, both the institution and the students benefit: Institutions increase equipment utilization, and utilize space, budgets and support personnel more efficiently. Students can access a lab whenever and wherever they have internet access. Finally, academic integrity must be protected to ensure the potential of remote laboratories in education. This Thesis presents a design and implementation plan for a low cost Logic Design laboratory infrastructure built and tested over 3 years by over 1,500 Logic Design students; a design and implementation of the infrastructure to include the ability to measure using remote test equipment; and the design of a case (3d printed or laser cut) to encapsulate a USB enabled micro-controller; and a scheme to ensure the academic integrity is maintained for in-person, hybrid and fully online classes. / Includes bibliography. / Thesis (M.S.)--Florida Atlantic University, 2018. / FAU Electronic Theses and Dissertations Collection

No description available.

Thesis (Ph. D.)--University of Texas at Austin, 1999. / Vita. Includes bibliographical references (leaves 132-150). Available also in a digital version from Dissertation Abstracts.

A program has been written for the Texas Instrument's TI-59 hand-held calculator implementing the Quine-McCluskey minimization method for logic circuit design. This program is contained on multiple magnetic cards and provides the user with the capability for combinational logic minimization of circuit design problems containing up to six variables.

A software interface between a firmware documentation system and a logic simulator named TEGAS-51 is described. The interface accepts PALASM2 inputs for PAL files. The output is an ASCII file which defines the firmware parts in TEGAS-5 format. Modules are written in FORTRAN and command routines are written in DCL on VAX 11/780 machines. No system calls are required, so portability is maintained. Limitations include the inability to load two different programs in identical firmware parts on the same design, but this can be overcome. 1GE/Calma Corporation trademark 2MMI Corporation trademark

This thesis is concerned with the use of memory function devices in place of binary storage devices in sequential machines. In particular, various counters are considered as memory elements. Design limitations and design procedures for each type of counter are determined, with emphasis placed on UP/DN/PRESET type counters. It is shown that a presettable counter is capable of realizing any sequential machine. Special considerations involved in state assignment and minimization in designs using counters are investigated. Finally, extensions and areas of possible further study are discussed. / Master of Science

Ho Chi Kit. / Thesis submitted in: September 2005. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2006. / Includes bibliographical references (leaves 66-70). / Abstracts in English and Chinese. / Chapter 1 --- Introduction --- p.9 / Chapter 1.1 --- Aims and Contribution --- p.9 / Chapter 1.2 --- Dissertation Overview --- p.10 / Chapter 2 --- Literature Review --- p.11 / Chapter 2.1 --- ATPG-based Alternative Wiring --- p.11 / Chapter 2.1.1 --- Post-Layout Logic Restructuring for Performance Optimization --- p.11 / Chapter 2.1.2 --- Timing Optimization by an Improved Redundancy Addition and Removal Technique --- p.12 / Chapter 2.2 --- Logic Synthesis --- p.13 / Chapter 2.2.1 --- Local Logic Substitution Algorithm for Post-Layout Re-synthesis --- p.13 / Chapter 2.2.2 --- SIS: A System for Sequential Circuit Synthesis --- p.13 / Chapter 2.3 --- Fanout Optimization --- p.14 / Chapter 2.3.1 --- Efficient Global Fanout Optimization Algorithms --- p.14 / Chapter 2.3.2 --- Fanout Optimization under a Submicron Transistor-Level Delay Model --- p.15 / Chapter 2.4 --- Genetic Algorithm --- p.15 / Chapter 2.4.1 --- Scalability and Efficiency of Genetic Algorithms for Geometrical Applications --- p.15 / Chapter 2.4.2 --- "The Gambler's Ruin Problem, Genetic Algorithms, and the Sizing of Populations" --- p.16 / Chapter 3 --- Background --- p.18 / Chapter 3.1 --- Redundancy Addition and Removal --- p.18 / Chapter 3.2 --- REWIRE --- p.19 / Chapter 4 --- Standard Cell Logic Synthesis --- p.20 / Chapter 4.1 --- Introduction --- p.20 / Chapter 4.2 --- Objective --- p.22 / Chapter 4.3 --- Use Standard Patterns for Logic Synthesis --- p.22 / Chapter 4.4 --- Optimization --- p.25 / Chapter 4.5 --- Proposed Scheme --- p.26 / Chapter 4.6 --- Criteria for Selection of Wire --- p.28 / Chapter 4.7 --- Experimental Results --- p.30 / Chapter 4.8 --- Conclusion --- p.34 / Chapter 5 --- Theory on GBAW --- p.35 / Chapter 5.1 --- Introduction --- p.35 / Chapter 5.2 --- Notations and Definitions --- p.36 / Chapter 5.3 --- Minimality and Duality --- p.37 / Chapter 5.4 --- Topological Property of GBAW patterns --- p.41 / Chapter 5.5 --- Experimental Results --- p.47 / Chapter 5.6 --- Conclusion --- p.51 / Chapter 6 --- Multi-way GBAW Partitioning Scheme --- p.52 / Chapter 6.1 --- Introduction --- p.52 / Chapter 6.2 --- Algorithm of GBAW Partitioning Scheme --- p.55 / Chapter 6.3 --- Experimental Results --- p.56 / Chapter 6.4 --- Conclusion --- p.63 / Chapter 7 --- Conclusion --- p.64 / Bibliography --- p.66

Typescript (photocopy). / Digitized by Kansas Correctional Industries

Thesis. 1977. Ph.D.--Massachusetts Institute of Technology. Dept. of Mechanical Engineering. / MICROFICHE COPY AVAILABLE IN ARCHIVES AND ENGINEERING. / Vita. / Bibliography: p. 293-295. / Ph.D.

Lo Wing Hang. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2005. / Includes bibliographical references (leaves 60-61). / Abstracts in English and Chinese. / Abstract --- p.i / Chapter 1 --- Introduction --- p.1 / Chapter 2 --- Preliminaries --- p.5 / Chapter 2.1 --- Backgrounds and Definitions --- p.5 / Chapter 2.1.1 --- Boolean Network --- p.5 / Chapter 2.1.2 --- Transitive Fanin and Fanout Cone --- p.6 / Chapter 2.1.3 --- Controlling and Sensitizing Values --- p.6 / Chapter 2.1.4 --- Stuck-at Faults and Test Generation --- p.6 / Chapter 2.1.5 --- Mandatory Assignments --- p.8 / Chapter 2.2 --- Review of ATPG-based Rewiring --- p.9 / Chapter 3 --- Improved Single-Pass Rewiring Scheme Using Inconsistent Assignments --- p.14 / Chapter 3.1 --- Introduction --- p.14 / Chapter 3.2 --- Overview of FIRE --- p.15 / Chapter 3.3 --- Alternative Wire Identification Method --- p.17 / Chapter 3.3.1 --- Identifying Candidate Wires --- p.17 / Chapter 3.3.2 --- Redundancy Test on Candidate Wire --- p.18 / Chapter 3.4 --- Redundancy Identification Using Inconsistent Assignments --- p.21 / Chapter 3.5 --- Experimental Results --- p.26 / Chapter 3.6 --- Conclusions --- p.28 / Chapter 4 --- Improving Circuit Partitioning With Rewiring Techniques --- p.29 / Chapter 4.1 --- Introduction --- p.29 / Chapter 4.2 --- Implementation of Rewiring Schemes --- p.31 / Chapter 4.3 --- Coupling Partitioning Algorithm With Rewiring Techniques --- p.33 / Chapter 4.4 --- Experimental Results --- p.37 / Chapter 4.5 --- Conclusions --- p.43 / Chapter 5 --- Circuit Logic Level Reduction by Rewiring for FPGA Mapping --- p.45 / Chapter 5.1 --- Introduction --- p.45 / Chapter 5.2 --- Overview of the Technology Mapping Problem --- p.47 / Chapter 5.2.1 --- Problem Formulation --- p.47 / Chapter 5.2.2 --- FlowMap Algorithm Outline --- p.49 / Chapter 5.3 --- Logic Level Reduction by Rewiring Transformations --- p.51 / Chapter 5.4 --- Experimental Results --- p.54 / Chapter 5.5 --- Conclusions --- p.57 / Chapter 6 --- Conclusions and Future Works --- p.58 / Bibliography --- p.60