<p>Advancements of the semiconductor technology opened a new era in</p> <p>wireless communications which led manufacturers to produce faster,</p> <p>more functional devices in much smaller sizes. However, testing</p> <p>these devices of today's technology became much harder and expensive</p> <p>due to the complexity of the devices and the high operating speeds.</p> <p>Moreover, testing these devices becomes more important since decreasing</p> <p>feature sizes increase the probability of parametric and catastrophic</p> <p>faults because of the severe effects of process variations. Manufacturers</p> <p>have to increase their test budgets to address quality and reliability</p> <p>concerns. In the radio frequency (RF) domain, overall test cost are higher</p> <p>due to equipment costs, test development and test time costs. Advanced</p> <p>circuit integration, which integrates various analog and digital circuit</p> <p>blocks into single device, increases test costs further because of the</p> <p>additional tests requiring new test setups with extra test equipments.</p> <p>Today's RF transceiver circuits contain many analog and digital circuit</p> <p>blocks, such as synthesizers, data converters and the analog RF front-end</p> <p>leading to a mixed signal device. Verification of the specifications and</p> <p>functionality of each circuit block and the overall transceiver require</p> <p>RF instrumentation and lengthy test routines. In this dissertation, we</p> <p>propose efficient component and system level test methods for RF</p> <p>transceivers which are low cost alternatives to traditional tests.</p> <p>In the first component level test, we focus on in-band phase noise of the</p> <p>phase locked loops (PLL). Most on-chip self-test methods for PLLs aim at</p> <p>measuring the timing jitter that may require precise reference clocks and/or</p> <p>additional computation of measured specs. We propose a built in test (BiT)</p> <p>circuit to perform a go/no-go test for in-band PLL phase noise. The proposed</p> <p>circuit measures the band-limited noise power at the input of the voltage</p> <p>controlled oscillator (VCO). This noise power is translated as the high</p> <p>frequency in-band phase noise at the output of the PLL. Our circuit contains</p> <p>a self calibration sequence based on a simple sinusoidal input signal to make</p> <p>it robust with respect to process variations.</p> <p>The second component level test is a built in self test (BiST) scheme</p> <p>proposed for analog to digital converters (ADC) based on a linear ramp</p> <p>generator and efficient output analysis. The proposed analysis method is</p> <p>an alternative to histogram based analysis techniques to provide test time</p> <p>improvements, especially when the resources are scarce. In addition to the</p> <p>measurement of differential nonlinearity (DNL) and integral nonlinearity</p> <p>(INL), non-monotonic behavior of the ADC can also be detected with the</p> <p>proposed technique. The proposed ramp generator has a high linearity</p> <p>capable of testing 13-bit ADCs.</p> <p>In the proposed system level test methods, we utilize the loop-back</p> <p>configuration to eliminate the need for an RF instrument. The first loop-back</p> <p>test method, which is proposed for wafer level test of direct conversion</p> <p>transceivers, targets catastrophic and large parametric faults. The use of</p> <p>intermediate frequencies (IF) generates a frequency offset between the transmit</p> <p>and receive paths and prevents a direct loop-back connection. We overcome this</p> <p>problem by expanding the signal bandwidth through saturating the receive path</p> <p>composed of low noise amplifier (LNA) and mixer. Once the dynamic range of the</p> <p>receiver path is determined, complete transceiver can be tested for catastrophic</p> <p>signal path faults by observing the output signal. A frequency spectrum</p> <p>envelope signature technique is proposed to detect large parametric faults.</p> <p>The impact of impairments, such as transmitter receiver in-phase/quadrature</p> <p>(I/Q) gain and phase mismatches on the performance have become severe due to</p> <p>high operational speeds and continuous technology scaling. In the second system</p> <p>level loop-back test method, we present BiST solutions for quadrature modulation</p> <p>transceiver circuits with quadrature phase shift keying (QPSK) and Gaussian</p> <p>minimum shift keying (GMSK) baseband modulation schemes. The BiST methods</p> <p>use only transmitter and receiver baseband signals for test analysis. The</p> <p>mapping between transmitter input signals and receiver output signals are</p> <p>used to extract impairment and nonlinearity parameters separately with the</p> <p>help of signal processing methods and detailed nonlinear system modeling.</p> <p>The last system level test proposed in this dissertation combines the benefits </p> <p>of loop-back and multi-site test approaches. In this test method, we present </p> <p>a 2x-site test solution for RF transceivers. We perform all operations on </p> <p>communication standard-compliant signal packets, thereby putting the device </p> <p>under the normal operating conditions. The transmitter on one device under </p> <p>test (DUT) is coupled with a receiver on another DUT to form a complete TX-RX </p> <p>path. Parameters of the two devices are decoupled from one another by carefully </p> <p>modeling the system into a known format and using signal processing techniques.</p> / Dissertation

The advent of deep submicron technology coupled with ever increasing demands from the customer for more functionality on a compact silicon real estate has led to a proliferation of highly complex integrated RF system-on-chip (SoC) and system-on-insulator (SoI) solutions. The use of scaled CMOS technologies for high frequency wireless applications is posing daunting technological challenges both in design and manufacturing test. To ensure market success, manufacturers need to ensure the quality of these advanced RF devices by subjecting them to a conventional set of production test routines that are both time consuming and expensive. Typically the devices are tested for parametric specifications such as gain, linearity metrics, quadrature mismatches, phase noise, noise figure (NF) and end-to-end system level specifications such as EVM (error vector magnitude), BER (bit-error-rate) etc. Due to the reduced visibility imposed by high levels of integration, testing for parametric specifications are becoming more and more complex. To offset the yield loss resulting from process variability effects and reliability issues in RF circuits, the use of self-healing/self-tuning mechanisms will be imperative. Such self-healing is typically implemented as a test/self-test and self-tune procedure and is applied post-manufacture. To enable this, simple test routines that can accurately diagnose complex performance parameters of the RF circuits need to be developed first. After diagnosing the performance of a complex RF system appropriate compensation techniques need to be developed to increase or restore the system performance. Moreover, the test, diagnosis and compensation approach should be low-cost with minimal hardware and software overhead to ensure that the final product is economically viable for the manufacturer. The main components of the thesis are as follows: 1) Low-cost specification testing of advanced radio frequency front-ends: Methodologies are developed to address the issue of test cost and test time associated with conventional production testing of advanced RF front-ends. The developed methodologies are amenable for performing self healing of RF SoCs. Test generation algorithms are developed to perform alternate test stimulus generation that includes the artifacts of test signal path such as response capture accuracy, load-board DfT etc. A novel cross loop-back methodology is developed to perform low cost system level specification testing of multi-band RF transceivers. A novel low-cost EVM testing approach is developed for production testing of wireless 802.11 OFDM front-ends. A signal transformation based model extraction technique is developed to compute multiple RF system level specifications of wireless front-ends from a single data capture. The developed techniques are low-cost and facilitate a reduction in the overall contribution of test cost towards the manufacturing cost of advanced wireless products. 2)Analog tuning methodologies for compensating wireless RF front ends: Methodologies for performing low-cost self tuning of multiple impairments of wireless RF devices are developed. This research considers for the first time, multiple analog tuning parameters of a complete RF transceiver system (transmitter and receiver) for tuning purposes. The developed techniques are demonstrated on hardware components and behavioral models to improve the overall yield of integrated RF SoCs.