As the oil industry continues to drill deeper to reach new wells, electronics are being required to operate at extreme pressures and temperatures. Coupled with substantial real-time data targets, the need for robust high speed electronics is quickly on the rise. This paper presents a high temperature wideband low noise amplifier (LNA) with zero temperature coefficient maximum available gain (ZTCMAG) biasing for a downhole communication system. The proposed LNA is designed and prototyped using 0.25μm GaN on SiC RF transistor technology, which is chosen due to the high junction temperature capability. Measurements show that the proposed LNA can operate reliably up to an ambient temperature of 230°C with a minimum noise figure (NF) of 2.0 dB, gain of 16.1 dB, and P1dB of 19.1 dBm from 230.5MHz — 285.5MHz. The maximum variation with temperature from 25°C to 230°C is 1.53dB for NF and 0.65dB for gain. / Master of Science

Future wireless communication devices must support multiple standards and features on a single-chip. The trend towards software-defined radio requires flexible and efficient RF building blocks which justifies the adoption of broadband receiver front-ends in modern and future communication systems. The broadband receiver front-end significantly reduces cost, area, pins, and power, and can process several signal channels simultaneously. This research is mainly focused on the analysis and realization of the broadband receiver architecture and its various building blocks (LNA, Active Balun-LNA, Mixer, and trans-impedance amplifier) for multi-standard applications. In the design of the mobile DTV tuner, a direct-conversion receiver architecture is adopted achieving low power, low cost, and high dynamic-range for DVB-H standard. The tuner integrates a single-ended RF variable gain amplifier (RFVGA), a current-mode passive mixer, and a combination of continuous and discrete-time baseband filter with built-in anti-aliasing. The proposed RFVGA achieves high dynamic-range and gain-insensitive input impedance matching performance. The current-mode passive mixer achieves high gain, low noise, and high linearity with low power supplies. A wideband common-gate LNA is presented that overcomes the fundamental trade-off between power and noise match without compromising its stability. The proposed architecture can achieve the minimum noise figure over the previously reported feedback amplifiers in common-gate configuration. The proposed architecture achieves broadband impedance matching, low noise, large gain, enhanced linearity, and wide bandwidth concurrently by employing an efficient and reliable dual negative-feedback. For the wideband Inductorless Balun-LNA, active single-to-differential architecture has been proposed without using any passive inductor on-chip which occupies a lot of silicon area. The proposed Balun-LNA features lower power, wider bandwidth, and better gain and phase balance than previously reported architectures of the same kind. A surface acoustic wave (SAW)-less direct conversion receiver targeted for multistandard applications is proposed and fabricated with TSMC 0.13?m complementary metal-oxide-semiconductor (CMOS) technology. The target is to design a wideband SAW-less direct coversion receiver with a single low noise transconductor and current-mode passive mixer with trans-impedance amplifier utilizing feed-forward compensation. The innovations in the circuit and architecture improves the receiver dynamic range enabling highly linear direct-conversion CMOS front-end for a multi-standard receiver.

Master´s thesis is interested in the problems of low-noise road surfaces. The theoretical part describes noise, sources of noise, the low-noise road surfaces and the practical part describes two proposals of low-noise stone mastic asphalt SMA 8 LA.

In the thesis the design of process tolerant, use-aware radio-frequency front-ends were explored. First, the design of fuzzy logic and equation based controllers, which can adapt to multi-dimensional channel conditions, are proposed. Secondly, the thesis proves that adaptive systems can have multiple modes of operation depending upon the throughput requirements of the system. Two such modes were demonstrated: one optimizing the energy-per-bit (energy priority mode) and another achieving the lowest power consumption at the highest throughput (data priority mode). Finally, to achieve process tolerant channel adaptive operation a self-learning methodology is proposed which learns the optimal re-configuration setting for the system on-the-fly. Implications of the research are discussed and future avenues of further research are proposed.

La pénétration importante d’objets communicants dans notre vie quotidienne révèle des défis important quant à leur développement. Notamment l’explosion d'applications multimédia sans fil pour l'électronique grand public fait de la consommation électrique une métrique clef dans la conception des dispositifs portables multimodes sans fil. Les émetteurs-récepteurs conventionnels proposent des performances fixes et sont conçus pour respecter ces hautes performances dans toutes les conditions de communication sans fil. Cependant, la plupart du temps, le canal n'est pas dans le pire cas de communication et ces émetteurs-récepteurs sont donc surdimensionnés. En connaissant l’état du canal en temps réel, de tels dispositifs pourraient s'adapter aux besoins et réduire significativement leur consommation électrique. Le défi consiste à respecter la Qualité de Service , ou Quality of Service (QoS) en anglais, imposée par les différents standards de communication. Afin de rester compétitifs, les émetteurs-récepteurs adaptatifs doivent donc proposer une même QoS que ceux déjà disponibles sur le marché. Ainsi, ni la portée de communication ni le temps de réponse ne peuvent être dégradés.Basé sur ces exigences, cette thèse propose une technique d'adaptation pour la conception d'un récepteur reconfigurable qui fonctionne à la limite des performances nécessaires pour recevoir le signal utile. Ainsi, le récepteur proposé est toujours au minimum de consommation électrique tout en garantissant la bonne QoS. Ceci permet alors de multiplier la durée de vie de sa batterie par un facteur 5.Cette adaptabilité est démontrée ensuite côté circuit par la conception d'un LNA (Amplificateur Faible Bruit) dont les performances sont reconfigurables. En effet, en tant que premier élément de la chaîne de réception, le LNA limite le récepteur en termes de sensibilité. Ces travaux exploitent la technologie FD-SOI (Fully Depleted Silicon-On-Insulator) pour d’une part, réduire la consommation du LNA et d’autre part, ajouter de la reconfigurabilité à ce même circuit. / Communicating objects are inviting themselves into daily life leading to digitization of the physical world. This explosion of multimedia wireless applications for consumer electronics makes the power consumption a key metric in the design of multi-mode wireless portable devices. Conventional transceivers have fixed performances and are designed to meet high performances in all wireless link conditions. However, most of the time, the channel of communication is not at worst case and these transceivers are therefore over specified. Being aware of the channel link conditions would allow such devices to adapt themselves and to reduce significantly their power consumption. Therefore, the challenge is to propose a QoS (Quality of Service) in terms of communication range, response time as instance, equivalent to industrial modules with a reduced overall power consumption.To address this purpose, this thesis proposes a design strategy for the implementation of adaptive radio-frequency receiver (Rx) modules. Hence the Rx front end achieves the correct QoS for various scenarii of communications with a minimum of power consumption.As a proof of concept, the adaptive approach is demonstrated with the design of a tunable LNA (Low Noise Amplifier). As the first element of the receiver chain, the LNA limits the receiver in terms of sensitivity and is therefore a good candidate to perform reconfiguration. The body biasing of the FD-SOI (Fully Depleted Silicon-On-Insulator) technology is first exploited to reduce the power consumption of a circuit and then as an opportunity to perform circuit tunability.

The presentation highlights research on theory, design, EM modeling, fabrication, packaging, and measurement of GaAs Monolithic Microwave Integrated Circuits (MMICs). The goal of this work is to design MMIC LNAs with low noise figure, high gain, and wide bandwidth. The work aims to develop GaAs MMIC LNAs for the application of RF front-end receivers in radio telescopes. GaAs MMIC technology offers modern radio astronomy attractive solutions based on its advantage in terms of high operational frequency, low noise, excellent repeatability and high integration density. Theoretical investigations are performed, presenting the formulation and graphical methods, and focusing on a systematic method to design a low noise amplifier for the best noise, gain and input/output return loss. Additionally, an EM simulation method is utilized and successfully applied to MMIC designs. The effect of packaging including the wire bond and chassis is critical as the frequency increases. Therefore, it is modeled by full-wave analysis where the measured results verify the reliability of these models. The designed MMICs are validated by measurements of several prototypes, including three C/X band and one Q band MMIC LNAs. Moreover, comparison to similar industrial chips demonstrates the superiority of the proposed structures regarding bandwidth, noise and gain flatness, and making them suitable for use in radio astronomy receivers. / Graduate / 2020-05-01

Este trabalho apresenta o projeto de um bloco LNA-Misturador dentro de um mesmo circuito integrado para aplicações em um receptor Bluetooth 2;45GHz. Uma estratégia de projeto bem clara, concisa e com uma boa base física e matemática foi desenvolvida para auxiliar o processo de projeto de um bloco LNA-Misturador, composto por um LNA cascode em cascata com um misturador de chaveamento de corrente com entradas simples e degeneração indutiva nas fontes dos estágios de transcondutância. Esta estratégia foi adaptada de trabalhos apresentados na literatura. A estratégia de projeto proposta considera o compromisso entre ruído, linearidade, ganho, dissipação de potência, casamento de impedâncias e isolamento de portas, usando as dimensões dos dispositivos e condições de polarização como variáveis de projeto. Com base nesta estratégia se obteve um bloco LNA-Misturador que atinge algumas especificações propostas. Um bloco LNA-Misturador foi projetado e fabricado em uma tecnologia CMOS 0;35µm para validar a estratégia de projeto proposta. Além disso, para atingir os objetivos, durante o desenvolvimento deste trabalho foi dada atenção especial no projeto dos indutores. Foi projetado, fabricado e medido um chip de teste. Para tal fim foram aplicadas técnicas e estruturas de de-embedding nas medidas para conseguir resultados mais confiáveis. Os resultados experimentais obtidos para os indutores e os resultados preliminares do bloco LNA-Misturador s~ao satisfatórios de acordo com as especificações e os esperados das simulações. No entanto, os indutores integrados degradam significativamente o desempenho do bloco LNA-Misturador. Se forem usados processos de fabricação nos quais os indutores apresentem melhor desempenho, os resultados do bloco LNA-Misturador aplicando a estratégia de projeto desenvolvida neste trabalho podem ser melhorados. Finalmente, é importante ressaltar que a estratégia de projeto proposta neste trabalho já está sendo usada e adaptada em outros projetos com o propósito de melhorar os resultados obtidos, e conseguir auxiliar o processo de projeto deste tipo de blocos. / This work presents a fully integrated LNA-Mixer design for a Bluetooth receiver application at 2:45GHz. A concise design strategy with good physics and mathematics basis was developed to assist the design process of a LNA-Mixer block, formed by a cascode LNA in cascade to a single balanced current commutation Mixer with inductive degeneration. This strategy was adapted from literature and considers the trade-offs between noise, linearity, gain, power dissipation, impedance matching and ports isolation, using the device dimensions and bias conditions as design variables. Based on this strategy, the proposed LNA-Mixer design specifications were achieved. To validate the proposed design strategy, the LNA-Mixer were fabricated in a 0:35µm CMOS process. Furthermore, to achieve the specifications, during the development of this work a special attention to the RF CMOS inductors was given. A test chip was designed, fabricated and measured applying de-embedding structures to obtain more reliable results. The experimental results obtained for the inductors and the preliminary results for the LNA-Mixer are satisfactory compared to the specifications and as expected from simulations. However, the integrated inductors degrade the performance of the block significantly and if a manufacturing process in which the inductor has better performance is used, the resulting LNA-Mixer design applying the strategy developed in this work can be improved. Finally, it is important to highlight that the design strategy proposed in this work is already being used and adapted in other designs in order to improve the results, and to assist the design process of such blocks.

The global market of mobile and wireless communications is witnessing explosive growth in size as well as radical changes. Third generation (3G) wireless systems have recently been deployed and some are still in the process. 3G wireless systems promise integration of voice and data communications with higher data rates and a superior quality of service compared to second generation systems. Unfortunately, more and more communication standards continue to be developed which ultimately requires specific RF/MW and baseband communication integrated circuits that are designed for functionality and compatibility with a specific type of network. Although communication devices such as cellular phones integrate different services such as voice, Bluetooth, GPS, and WLAN, each service requires its own dedicated radio transceiver which results in high power consumption and larger PCB area usage. With the rapid advances in silicon CMOS integrated circuit technology combined with extensive research, a global solutionswhich aims at introducing a global communication system that encompasses all communication standards appears to be emerging. State of the art CMOS technology not only has the capability of operation in the GHz range, but it also provides the advantage of low cost and high level of integration. These features propel CMOS technology as the ideal candidate for current trends, which currently aim to integrate more RF/MW circuits on the same chip. Armed with such technology ideas such as software radio look more attainable than they ever were in the past. Unfortunately, realizing true software radio for mobile applications still remains a tremendous challenge since it requires a high sampling rate and a wide-bandwidth Analog-to-Digital converter which is extremely power hungry and not suitable for battery operated mobile devices. Another approach to realize a flexible and reconfigurable RF/MW transceiver that could operate in a diverse mobile environment and provides a multiband and multistandard solution. The work presented in this thesis focuses on the design of an integrated and tunable low-noise amplifier as part of software defined radio (SDR).

<p>This master thesis deals with the study of ultra low power Low Noise Amplifier (LNA) for use inmedical implant device. Usually, low power consumption is required for a long battery lifetime andlonger operation. The target technology is 90nm CMOS process.First basic principle of LNA is discussed. Then based on a literature review of LNA design, theproposed LNA is presented in sub-threshold region which reduce power consumption through scalingthe supply voltage and through scaling current.The circuit implementation and simulations is presented to testify the performance of LNA .Besides thepower consumption simulated under the typical supply voltage (1V), it is also measured under someother low supply voltages (down to 0.5V) to investigate the minimum power consumption and theminimum noise figure. Evaluation results show that at a supply voltage of 1V the LNA performs a totalpower consumption of 20mW and a noise of 1dB. Proper performance is achieved with a current ofdown to 200uA and supply voltage of down to 0.45V, and a total power consumption of 200uW</p>

<p>In modern medicine, the measurement of electrophysiological signals play a key role in health monitoring and diagnostics. Electrical activity originating from our nerve and muscle cells conveys real-time information about our current health state. The two most common and actively used techniques for measuring such signals are electrocardiography (ECG) and electroencephalography (EEG).</p><p>These signals are very weak, reaching from a few millivolts down to tens of microvolts in amplitude, and have the majority of the power located at very low frequencies, from below 1 Hz up to 40 Hz. These characteristics sets very tough requirements on the electrical circuit designs used to measure them. Usually, measurement is performed by attaching electrodes with direct contact to the skin using an adhesive, conductive gel to fixate them. This method requires a clinical environment and is time consuming, tedious and may cause the patient discomfort.</p><p>This thesis investigates another method for such measurements; by using a non-contact, capacitively coupled sensor, many of these shortcomings can be overcome. While this method relieves some problems, it also introduces several design difficulties such as: circuit noise, extremely high input impedance and interference. A capacitively coupled sensor was created using the bottom layer of a printed circuit board (PCB) as a capacitor plate and placing it against the signal source, that acts as the opposite capacitor plate. The PCB solder mask layer and any air in between the two acts as the insulator to create a full capacitor. The signal picked up by this sensor was then amplified by 60 dB with a high input impedance amplifier circuit and further conditioned through filtering.</p><p>Two measurements were made of the same circuit, but with different input impedances; one with 10 MΩ and one with 10 GΩ input impedance. Additional filtering was designed to combat interference from the main power lines at 50 Hz and 150 Hz that was discovered during initial measurements. The circuits were characterized with their transfer functions, and the ability to amplify a very low-level, low frequency input signal. The results of these measurements show that high input impedance is of critical importance for the functionality of the sensor and that an input impedance of 10 GΩ is sufficient to produce a signal-to-noise ratio (SNR) of 9.7 dB after digital filtering with an input signal of 25 μV at 10 Hz.</p>