Due to the rapid development of semiconductor technology, the number of transistors of integrated circuits in unit area increases by double in roughly every two years. We then can add more circuits and functionality into a single chip. The size of electronic products certainly is reduced. Besides, because of the blooming popularity of wireless network standards in recently year, sensors have been wireless connected to provide more functionality and intelligence. They are, namely, wireless sensor network (WSN). Before long, the integrated circuit design will not only be emphasized on front-end circuits and hardware design, but also integration and functionality, which is so-called the system-on-chip (SOC) design. The first topic of this thesis is the implementation of IEEE 802.15.4 network prototype and hardware design. The main purpose of prototyping is to realize the highly portable IEEE 802.15.4 protocol stack library which can be quickly transferred to different hardwares. Thus, it shortens the time to market. In ASIC hardware design, we use WISHBONE bus as the interconnection architecture which can be easily integrated into current SOC design for an embedded system. The second topic is an application of IEEE 802.15.4 in medical monitoring, including system prototyping and ASIC hardware design, which collects the bladder pressure readings by a wireless link and ECG signals from our ASIC sensors. Finally, we realize the medical monitoring in a prototypical system.

This thesis presents the development of CMOS readout electronics for microbolometer type infrared detector arrays. A low power output buffering architecture and a new bias correction digital-to-analog converter (DAC) structure for resistive microbolometer readouts is developed / and a 384x288 resistive microbolometer FPA readout for 35 &micro / m pixel pitch is designed and fabricated in a standard 0.6 &micro / m CMOS process. A 4-layer PCB is also prepared in order to form an imaging system together with the FPA after detector fabrication. The low power output buffering architecture employs a new buffering scheme that reduces the capacitive load and hence, the power dissipation of the readout channels. Furthermore, a special type operational amplifier with digitally controllable output current capability is designed in order to use the power more efficiently. With the combination of these two methods, the power dissipation of the output buffering structure of a 384x288 microbolometer FPA with 35 &micro / m pixel pitch operating at 50 fps with two output channels can be decreased to 8.96% of its initial value. The new bias correction DAC structure is designed to overcome the power dissipation and noise problems of the previous designs at METU. The structure is composed of two resistive ladder DAC stages, which are capable of providing multiple outputs. This feature of the resistive ladders reduces the overall area and power dissipation of the structure and enables the implementation of a dedicated DAC for each readout channel. As a result, the need for the sampling operation required in the previous designs is eliminated. Elimination of sampling prevents the concentration of the noise into the baseband, and therefore, allows most of the noise to be filtered out by integration. A 384x288 resistive microbolometer FPA readout with 35 &amp / #956 / m pixel pitch is designed and fabricated in a standard 0.6 &amp / #956 / m CMOS process. The fabricated chip occupies an area of 17.84 mm x 16.23 mm, and needs 32 pads for normal operation. The readout employs the low power output buffering architecture and the new bias correction DAC structure / therefore, it has significantly low power dissipation when compared to the previous designs at METU. A 4-layer imaging PCB is also designed for the FPA, and initial tests are performed with the same PCB. Results of the performed tests verify the proper operation of the readout. The rms output noise of the imaging system and the power dissipation of the readout when operating at a speed of 50 fps is measured as 1.76 mV and 236.9 mW, respectively.

For many years batteries have been used as the main power sources for portable electronic devices. However, the rate of scaling in integrated circuits and micro-electro-mechanical systems (MEMS) has been much higher than that of the batteries technology. Therefore, a need to replace these temporary energy reservoirs with small sized continuously charged energy supply units has emerged. These units, named as energy harvesters, use several types of ambient energy sources such as heat, light, and vibration to provide energy to intelligent systems such as sensor nodes. Among the available types, vibration based electromagnetic (EM) energy harvesters are particularly interesting because of their simple structure and suitability for operation at low frequency values (&lt / 10 Hz), where most vibrations exits. However, since the generated EM power and voltage is relatively low at low frequencies, high performance interface electronics is required for efficiently transferring the generated power from the harvester to the load to be supplied. The aim of this study is to design low power and efficient interface electronics to convert the low voltage and low power generated signals of the EM energy harvesters to DC to be usable by a real application. The most critical part of such interface electronics is the AC/DC converter, since all the other blocks such as DC/DC converters, power managements units, etc. rely on the rectified voltage generated by this block. Due to this, several state-of-the-art rectifier structures suitable for energy harvesting applications have been studied. Most of the previously proposed rectifiers have low conversion efficiency due to the high voltage drop across the utilized diodes. In this study, two rectifier structures are proposed: one is a new passive rectifier using the Boot Strapping technique for reducing the diode turn-on voltage values / the other structure is a comparator-based ultra low power active rectifier. The proposed structures and some of the previously reported designs have been implemented in X-FAB 0.35 &micro / m standard CMOS process. The autonomous energy harvesting systems are then realized by integrating the developed ASICs and the previously proposed EM energy harvester modules developed in our research group, and these systems have been characterized under different electromechanical excitation conditions. In this thesis, five different systems utilizing different circuits and energy harvesting modules have been presented. Among these, the system utilizing the novel Boot Strap Rectifier is implemented within a volume of 21 cm3, and delivers 1.6 V, 80 &micro / A (128 &micro / W) DC power to a load at a vibration frequency of only 2 Hz and 72 mg peak acceleration. The maximum overall power density of the system operating at 2 Hz is 6.1 &micro / W/cm3, which is the highest reported value in the literature at this operation frequency. Also, the operation of a commercially available temperature sensor using the provided power of the energy harvester has been shown. Another system utilizing the comparator-based active rectifier implemented with a volume of 16 cm3, has a dual rail output and is able to drive a 1.46 V, 37 &micro / A load with a maximum power density of 6.03 &micro / W/cm3, operating at 8 Hz. Furthermore, a signal conditioning system for EM energy harvesting has also been designed and simulated in TSMC 90 nm CMOS process. The proposed ASIC includes a highly efficient AC-DC converter as well as a power processing unit which steps up and regulates the converted DC voltages using an on-chip DC/DC converter and a sub-threshold voltage regulator with an ultra low power management unit. The total power consumption on the totally passive IC is less than 5 &micro / W, which makes it suitable for next generation MEMS-based EM energy harvesters. In the frame of this study, high efficiency CMOS rectifier ICs have been designed and tested together with several vibration based EM energy harvester modules. The results show that the best efficiency and power density values have been achieved with the proposed energy harvesting systems, within the low frequency range, to the best of our knowledge. It is also shown that further improvement of the results is possible with the utilization of a more advanced CMOS technology.

This thesis presents circuit-level techniques for soft error mitigation, low-power design with performance trade-off, and variation-tolerant low-power design. The proposed techniques are divided into two broad categories. First, error compensation techniques, which are used for soft error mitigation and also for low-power operation of linear and non-linear filters. Second, a framework for variation tolerant low-power operation of wireless devices is presented. This framework analyzes the effects of circuit "tuning knobs" such as voltage, frequency, wordlength precision, etc. on system performance, and power efficiency. Process variations are considered as well, and the best operating tuning knob levels are determined, which results in maximum system wide power savings while keeping the system performance within acceptable limits. Different methods are presented for variation-tolerant and power-efficient wireless communication. Techniques are also proposed for application driven low-power operation of the OFDM baseband receiver.

This dissertation focuses on design and implementation of a fully-integrated SRAM-based arbitrary waveform generator for analog signal processing applications in a CMOS technology. The dissertation consists of two parts: Firstly, a fully-integrated arbitrary waveform generator for a multi-resolution spectrum sensing of a cognitive radio applications, and an analog matched-filter for a radar application and secondly, low-power techniques for an arbitrary waveform generator. The fully-integrated low-power AWG is implemented and measured in a 0.18-¥ìm CMOS technology. Theoretical analysis is performed, and the perspective implementation issues are mentioned comparing the measurement results. Moreover, the low-power techniques of SRAM are addressed for the analog signal processing: Self-deactivated data-transition bit scheme, diode-connected low-swing signaling scheme with a short-current reduction buffer, and charge-recycling with a push-pull level converter for power reduction of asynchronous design. Especially, the robust latch-type sense amplifier using an adaptive-latch resistance and fully-gated ground 10T-SRAM bitcell in a 45-nm SOI technology would be used as a technique to overcome the challenges in the upcoming deep-submicron technologies.

A central component of modern computing is the idea that computation requires determinism. Contrary to this belief, the primary contribution of this work shows that useful computation can be accomplished in an error-prone fashion. Focusing on low-power computing and the increasing push toward energy conservation, the work seeks to sacrifice accuracy in exchange for energy savings. Probabilistic computing forms the basis for this error-prone computation by diverging from the requirement of determinism and allowing for randomness within computing. Implemented as probabilistic CMOS (PCMOS), the approach realizes enormous energy sav- ings in applications that require probability at an algorithmic level. Extending probabilistic computing to applications that are inherently deterministic, the biased voltage overscaling (BIVOS) technique presented here constrains the randomness introduced through PCMOS. Doing so, BIVOS is able to limit the magnitude of any resulting deviations and realizes energy savings with minimal impact to application quality. Implemented for a ripple-carry adder, array multiplier, and finite-impulse-response (FIR) filter; a BIVOS solution substantially reduces energy consumption and does so with im- proved error rates compared to an energy equivalent reduced-precision solution. When applied to H.264 video decoding, a BIVOS solution is able to achieve a 33.9% reduction in energy consumption while maintaining a peak-signal-to-noise ratio of 35.0dB (compared to 14.3dB for a comparable reduced-precision solution). While the work presented here focuses on a specific technology, the technique realized through BIVOS has far broader implications. It is the departure from the conventional mindset that useful computation requires determinism that represents the primary innovation of this work. With applicability to emerging and yet to be discovered technologies, BIVOS has the potential to contribute to computing in a variety of fashions.

Includes vita. / Title from PDF of title page. / Document formatted into pages; contains 289 pages. / Thesis (Ph.D.)--University of South Florida, 2003. / Includes bibliographical references. / Text (Electronic thesis) in PDF format. / ABSTRACT: The proliferation of portable systems and mobile computing platforms has increased the need for the design of low power consuming integrated circuits. The increase in chip density and clock frequencies due to technology advances has made low power design a critical issue. Low power design is further driven by several other factors such as thermal considerations and environmental concerns. In low-power design for battery driven portable applications, the reduction of peak power, peak power differential, average power and energy are equally important. In this dissertation, we propose a framework for the reduction of these parameters through datapath scheduling at behavioral level. Several ILP based and heuristic based scheduling schemes are developed for datapath synthesis assuming : (i) single supply voltage and single frequency (SVSF), (ii) multiple supply voltages and dynamic frequency clocking (MVDFC), and (iii) multiple supply voltages and multicycling (MVMC). / ABSTRACT: The scheduling schemes attempt to minimize : (i) energy, (ii) energy delay product, (iii) peak power, (iv) simultaneous peak power and average power, (v) simultaneous peak power, average power, peak power differential and energy, and (vi) power fluctuation. A new parameter called "Cycle Power Function" CPF) is defined which captures the transient power characteristics as the equally weighted sum of normalized mean cycle power and normalized mean cycle differential power. Minimizing this parameter using multiple supply voltages and dynamic frequency clocking results in the reduction of both energy and transient power. The cycle differential power can be modeled as either the absolute deviation from the average power or as the cycle-to-cycle power gradient. The switching activity information is obtained from behavioral simulations. Power fluctuation is modeled as the cycle-to-cycle power gradient and to reduce fluctuation the mean power gradient MPG is minimized. / ABSTRACT: The power models take into consideration the effect of switching activity on the power consumption of the functional units. Experimental results for selected high-level synthesis benchmark circuits under different constraints indicate that significant reductions in power, energy and energy delay product can be obtained and that the MVDFC and MVMC schemes yield better power reduction compared to the SVSF scheme. Several application specific VLSI circuits were designed and implemented for digital watermarking of images. Digital watermarking is the process that embeds data called a watermark into a multimedia object such that the watermark can be detected or extracted later to make an assertion about the object. / ABSTRACT: A class of VLSI architectures were proposed for various watermarking algorithms : (i) spatial domain invisible-robust watermarking scheme, (ii) spatial domain invisible-fragile watermarking scheme, (iii) spatial domain visible watermarking scheme, (iv) DCT domain invisible-robust watermarking scheme, and (v) DCT domain visible watermarking scheme. Prototype implementation of (i), (ii) and (iii) are given. The hardware modules can be incorporated in a "JPEG encoder" or in a "digital still camera". / System requirements: World Wide Web browser and PDF reader. / Mode of access: World Wide Web.

The Internet of Things (IoTs) has triggered rapid advances in sensors, surveillance devices, wearables and body area networks with advanced Human-Computer Interfaces (HCI). Neural Networks optimized algorithmically for high accuracy and high representation power are very deep and require tremendous storage and processing capabilities leading to higher area and power costs. For developing smart front-ends for ‘always on’ sensor nodes we need to optimize for power and area. This requires considering trade-offs with respect to various entities such as resource utilization, processing time, area, power, accuracy etc. Our experimental results show that there is presence of a network configuration with minimum energy given the input constraints of an application in consideration. This presents the need for a hardware-software co-design approach. We present a highly parameterized hardware design on an FPGA allowing re-configurability and the ability to evaluate different design choices in a short amount of time. We also describe the capability of extending our design to offer run time configurability. This allows the design to be altered for different applications based on need and also allows the design to be used as a cascaded classifier beneficial for continuous sensing for low power applications. This thesis aims to evaluate the use of Restricted Boltzmann Machines for building such re-configurable low power front ends. We develop the hardware architecture for such a system and provide experimental results obtained for the case study of Posture detection for body worn cameras used for law enforcement.

In the past, we could rely on technology scaling and new micro-architectural techniques to improve the performance of processors. Nowadays, both of these methods are reaching their limits. The primary concern in future architectures with billions of transistors on a chip and limited power budgets is power/energy efficiency. Full-custom design of application-specific cores can yield up to two orders of magnitude better power efficiency over conventional general-purpose cores. However, a tremendous design effort is required in integrating a new accelerator for each new application. In this dissertation, we present the design of specialized compute fabrics that maintain the efficiency of full custom hardware while providing enough flexibility to execute a whole class of coarse-grain operations. The broad vision is to develop integrated and specialized hardware/software solutions that are co-optimized and co-designed across all layers ranging from the basic hardware foundations all the way to the application programming support through standard linear algebra libraries. We try to address these issues specifically in the context of dense linear algebra applications. In the process, we pursue the main questions that architects will face while designing such accelerators. How broad is this class of applications that the accelerator can support? What are the limiting factors that prevent utilization of these accelerators on the chip? What is the maximum achievable performance/efficiency? Answering these questions requires expertise and careful codesign of the algorithms and the architecture to select the best possible components, datapaths, and data movement patterns resulting in a more efficient hardware-software codesign. In some cases, codesign reduces complexities that are imposed on the algorithm side due to the initial limitations in the architectures. We design a specialized Linear Algebra Processor (LAP) architecture and discuss the details of mapping of matrix-matrix multiplication onto it. We further verify the flexibility of our design for computing a broad class of linear algebra kernels. We conclude that this architecture can perform a broad range of matrix-matrix operations as complex as matrix factorizations, and even Fast Fourier Transforms (FFTs), while maintaining its ASIC level efficiency. We present a power-performance model that compares state-of-the-art CPUs and GPUs with our design. Our power-performance model reveals sources of inefficiencies in CPUs and GPUs. We demonstrate how to overcome such inefficiencies in the process of designing our LAP. As we progress through this dissertation, we introduce modifications of the original matrix-matrix multiplication engine to facilitate the mapping of more complex operations. We observe the resulting performance and efficiencies on the modified engine using our power estimation methodology. When compared to other conventional architectures for linear algebra applications and FFT, our LAP is over an order of magnitude better in terms of power efficiency. Based on our estimations, up to 55 and 25 GFLOPS/W single- and double-precision efficiencies are achievable on a single chip in standard 45nm technology. / text

This dissertation presents an efficient multilayer background modeling approach to distinguish among midground objects, the objects whose existence occurs over varying time scales between the extremes of short-term ephemeral appearances (foreground) and long-term stationary persistences (background). Traditional background modeling separates a given scene into foreground and background regions. However, the real world can be much more complex than this simple classification, and object appearance events often occur over varying time scales. There are situations in which objects appear on the scene at different points in time and become stationary; these objects can get occluded by one another, and can change positions or be removed from the scene. Inability to deal with such scenarios involving midground objects results in errors, such as ghost objects, miss-detection of occluding objects, aliasing caused by the objects that have left the scene but are not removed from the model, and new objects’ detection when existing objects are displaced. Modeling temporal layers of multiple objects allows us to overcome these errors, and enables the surveillance and summarization of scenes containing multiple midground objects.