The Internet of Things (IoT) concept has been realised with the advent of Machineto-Machine (M2M) communication through which the vision of future Internet has been revolutionised. IPv6 over Low power Wireless Personal Area Networks (6LoWPAN) provides feasible IPv6 connectivity to previously isolated environments, e.g. wireless M2M sensors and actuator networks. This thesis's contributions include a novel mathematical model, energy-efficient algorithms, and a centralised software controller for dynamic consolidation of programmability features in cloud-based M2M networks. A new generalised joint mathematical model has been proposed for performance analysis of the 6LoWPAN MAC and PHY layers. The proposed model differs from existing analytical models as it precisely adopts the 6LoWPAN specifications introduced by the Internet Engineering Task Force (IETF) working group. The proposed approach is based on Markov chain modelling and validated through Monte-Carlo simulation. In addition, an intelligent mechanism has been proposed for optimal 6LoWPAN MAC layer parameters set selection. The proposed mechanism depends on Artificial Neural Network (ANN), Genetic Algorithm (GA), and Particles Swarm Optimisation (PSO). Simulation results show that utilising the optimal MAC parameters improve the 6LoWPAN network throughput by 52-63% and reduce end-to-end delay by 54-65%. This thesis focuses on energy-efficient data extraction and dissemination in a wireless M2M sensor network based on 6LoWPAN. A new scalable and self-organised clustering technique with a smart sleep scheduler has been proposed for prolonging M2M network's lifetime and enhancing network connectivity. These solutions succeed in overcoming performance degradation and unbalanced energy consumption problems in homogeneous and heterogeneous sensor networks. Simulation results show that by adopting the proposed schemes in multiple mobile sink sensory field will improve the total aggregated packets by 38-167% and extend network lifetime by 30-78%. Proof-of-concept real-time hardware testbed experiments are used to verify the effectiveness of Software-Defined Networking (SDN), Network Function Virtualisation (NFV) and cloud computing on a 6LoWPAN network. The implemented testbed is based on open standards development boards (i.e. Arduino), with one sink, which is the M2M 6LoWPAN gateway, where the network coordinator and the customised SDN controller operated. Experimental results indicate that the proposed approach reduces network discovery time by 60% and extends the node lifetime by 65% in comparison with the traditional 6LoWPAN network. Finally, the thesis is concluded with an overall picture of the research conducted and some suggestions for future work.

Vertical integration technologies, such as three-dimensional integration and interposers, are technologies that support high integration densities while offering shorter interconnect lengths as compared to planar integration and other packaging technologies. To exploit these advantages, however, several challenges lay across the designing, manufacturing and testing stages of integrated systems. Considering the high complexity of modern microelectronic devices and the diverse features of vertical integration technologies, this thesis sheds light on the circuit design process. New methodologies and tools are offered in order to assess and improve traditional objectives in circuit design, such as performance, power, and area for vertically integrated circuits. Interconnects on different interposer materials are investigated, demonstrating the several trade-offs between power, performance, area, and crosstalk. A backend design flow is proposed to capture the performance and power gains from the introduction of the third dimension. Emphasis is also placed on the power consumption of modern circuits due to the immense growth of battery-operated devices in the last fifteen years. Therefore, the effect of scaling the operating voltage in three-dimensional circuits is investigated as it is one of the most efficient techniques for reducing power while considering the performance of the circuit. Furthermore, a solution to eliminate timing penalties from the usage of voltage scaling technique at finer circuits granularities is also presented in this thesis.

Depuis trois décennies, la tendance du marché répond à la demande actuelle de miniaturisation et d'augmentation de performances des appareils multimédias. Or, toute réduction des dimensions d'un facteur donné impose une diminution des tensions (pour des raisons de fiabilité). Afin d'y répondre, la réduction de taille des circuits intégrés CMOS atteint des échelles d'intégration submicroniques entrainant une baisse importante de la fiabilité des composants et en particulier des transistors. La création de porteurs chauds, ainsi que la dissipation thermique à l'intérieur des circuits submicroniques, sont les deux phénomènes physiques principaux à l'origine de la baisse de fiabilité. La solution technique permettant de garder un bon degré de fiabilité, tout en réduisant la taille des composants, consiste à réduire la tension d'alimentation des circuits. Parallèlement aux contraintes de performances, les normes environnementales demandent une consommation la plus réduite possible. La difficulté consiste alors en la réalisation de circuits associant une alimentation basse puissance (tension et courant) d'où la notion de circuits " Low Power ". Ces circuits sont pour certains déjà utilisés dans le domaine du multimédia, du médical, avec des contraintes d'intégration différentes (possibilité de composants externes, stabilité, etc.). L'augmentation des performances en vitesse des circuits digitaux nécessite par ailleurs l'utilisation de technologies générant des fuites de plus en plus importantes qui sont incompatibles avec une réduction de la consommation dans des modes de veille sans la mise en place de nouvelles techniques / For three decades, the market trend answers the current demand of miniaturization and performance increase of the multimedia devices. Yet, any reduction of the dimensions of a given factor imposes a decrease of the tensions (for reasons of reliability). To answer this question, the downsizing of CMOS integrated circuits reaches submicron scales of integration resulting in a significant decrease in the reliability of components and in particular transistors. The hot carriers creations, as well as heat dissipation within the submicron circuits, are the two main physical phenomena behind the reliability decline. The technical solution to maintain a good degree of reliability, while reducing component size, is to reduce the supply voltage of circuits. In parallel to performance constraints, environmental standards require consumption as small as possible. The challenge is then to build circuits combining low power supply (voltage and current) where the concept of circuits "Low Power". These circuits are used for some already in the field of multimedia, medical, integration with various constraints (possibility of external components, stability, etc..). The speed increase performance of digital circuits also requires the use of technologies that generate leaks increasingly important that are inconsistent with consumption reduction in standby modes without the introduction of new techniques.

O presente estudo avaliou a eficácia do piroxicam associado ao laser de baixa potência (LBP) no tratamento da artralgia da articulação temporomandibular (ATM). Trinta e dois pacientes (média de idade de 32,44 anos ± 13,02) com artralgia da ATM foram selecionados e divididos em 3 grupos: LBP+piroxicam (LPi), LBP+placebo de piroxicam (L) e piroxicam+placebo de LBP (Pi). Os pacientes receberam a terapêutica por 10 dias. As avaliações foram feitas no 1º, 3º, 8º, 10º dias de tratamento e 30 dias após o término. A presença e intensidade de dor espontânea, dor à palpação e máxima abertura bucal foram mensurados. Os dados foram analisados usando os testes de Friedman e de Wilcoxon, ou ANOVA e o teste t, adotando-se p<0,05 como nível de significância. Melhoras foram encontradas para os fatores dor espontânea e dor à palpação na análise intragrupo, embora diferenças significantes não foram encontradas entre os grupos. Entretanto, na avaliação de 30 dias, o grupo Pi apresentou menor dor à palpação (p=0,01) e menor dor para o músculo temporal (p=0,02) com diferenças significantes entre os grupos. Os resultados obtidos sugerem que a associação entre LBP e piroxicam não foi mais eficaz que as terapêuticas isoladas no tratamento de artralgia da ATM, e todas as terapêuticas foram eficazes na diminuição da dor. O uso do piroxicam isolado mostrou-se mais eficaz no acompanhamento de 30 dias para dor à palpação comparado ao uso de LBP isolado. / This aim of this study was to evaluate the efficacy of piroxicam associated with low-level laser therapy (LLLT) in the treatment of arthralgia of the temporomandibular joint (TMJ). Thirty-two patients (mean age 32,44 years old ± 13,02) with TMJ arthralgia were enrolled in the study and divided into 3 groups: LLLT+ piroxicam (LPi), LLLT+placebo piroxicam (L) e piroxicam+placebo LLLT (Pi). Patients were managed for ten days. Follow-up evaluations were done at the 1st, 3rd, 8th and 10th days of treatment and 30 days after the end. The presence and intensity of spontaneous pain, pain on palpation and mandibular maximum vertical opening were measured. Data were analyzed using Friedman and Wilcoxon tests or ANOVA and t test, considering a significance level of 5%. Improvements were found for factors spontaneous pain and pain on palpation in the intragroup analysis, although no significant differences were detected among groups. However, evaluation of 30 days after the treatment showed significant differences among groups, that the group Pi had the lowest pain on palpation (p=0,01) and the lowest pain for temporal muscle (p=0,02). The obtained results suggest that the association of LLLT and piroxicam were not more effective than single therapies in the treatment of TMJ arthralgia, and all treatments were effective in decreasing pain. The use of piroxicam alone was more effective in the following 30 days for pain on palpation over the use of LBP alone.

Esta dissertação de mestrado propõe uma hierarquia de memória para a Estimação de Movimento e de Disparidade (ME/DE) centrada nas referências da codificação, estratégia chamada de Reference-Centered Data Reuse (RCDR), com foco em redução de energia em codificadores de vídeo multivistas (MVC - Multiview Video Coding). Nos codificadores MVC, a ME/DE é responsável por praticamente 98% do consumo total de energia. Além disso, até 90% desta energia está relacionada com a memória do codificador: (a) acessos à memória externa para a busca das referências da ME/DE (45%) e (b) memória interna (cache) para manter armazenadas as amostras da área de busca e enviá-las para serem processadas pela ME/DE (45%). O principal objetivo deste trabalho é minimizar de maneira conjunta a energia consumida pelo módulo de ME/DE com relação às memórias externa e interna necessárias para a codificação MVC. A hierarquia de memória é composta por uma memória interna (a qual armazena a área de busca inteira), um controle dinâmico para a estratégia de power-gating da memória interna e um compressor de resultados parciais. Um controle de buscas foi proposto para explorar o comportamento da busca com o objetivo de atingir ainda mais reduções de energia. Além disso, este trabalho também agrega à hierarquia de memória um compressor de quadros de referência de baixa complexidade. A estratégia RCDR provê reduções de até 68% no consumo de energia quando comparada com estratégias estadoda- arte que são centradas no bloco atual da codificação. O compressor de resultados parciais é capaz de reduzir em 52% a comunicação com memória externa necessária para o armazenamento desses elementos. Quando comparada a técnicas de reuso de dados que não acessam toda área de busca, a estratégia RCDR também atinge os melhores resultados em consumo de energia, visto que acessos regulares a memórias externas DDR são energeticamente mais eficientes. O compressor de quadros de referência reduz ainda mais o número de acessos a memória externa (2,6 vezes menos acessos), aliando isso a perdas insignificantes na eficiência da codificação MVC. A memória interna requerida pela estratégia RCDR é até 74% menor do que estratégias centradas no bloco atual, como Level C. Além disso, o controle dinâmico para a técnica de power-gating provê reduções de até 82% na energia estática, o que é o melhor resultado entre os trabalho relacionados. A energia dinâmica é tratada pela técnica de união dos blocos candidatos, atingindo ganhos de mais de 65%. Considerando as reduções de consumo de energia atingidas pelas técnicas propostas neste trabalho, conclui-se que o sistema de hierarquia de memória proposto nesta dissertação atinge seu objetivo de atender às restrições impostas pela codificação MVC, no que se refere ao processamento do módulo de ME/DE. / This Master Thesis proposes a memory hierarchy for the Motion and Disparity Estimation (ME/DE) centered on the encoding references, called Reference-Centered Data Reuse (RCDR), focusing on energy reduction in the Multiview Video Coding (MVC). In the MVC encoders the ME/DE represents more than 98% of the overall energy consumption. Moreover, in the overall ME/DE energy, up to 90% is related to the memory issues, and only 10% is related to effective computation. The two items to be concerned with: (1) off-chip memory communication to fetch the reference samples (45%) and (2) on-chip memory to keep stored the search window samples and to send them to the ME/DE processing core (45%). The main goal of this work is to jointly minimize the on-chip and off-chip energy consumption in order to reduce the overall energy related to the ME/DE on MVC. The memory hierarchy is composed of an onchip video memory (which stores the entire search window), an on-chip memory gating control, and a partial results compressor. A search control unit is also proposed to exploit the search behavior to achieve further energy reduction. This work also aggregates to the memory hierarchy a low-complexity reference frame compressor. The experimental results proved that the proposed system accomplished the goal of the work of jointly minimizing the on-chip and off-chip energies. The RCDR provides off-chip energy savings of up to 68% when compared to state-of-the-art. the traditional MBcentered approach. The partial results compressor is able to reduce by 52% the off-chip memory communication to handle this RCDR penalty. When compared to techniques that do not access the entire search window, the proposed RCDR also achieve the best results in off-chip energy consumption due to the regular access pattern that allows lots of DDR burst reads (30% less off-chip energy consumption). Besides, the reference frame compressor is capable to improve by 2.6x the off-chip memory communication savings, along with negligible losses on MVC encoding performance. The on-chip video memory size required for the RCDR is up to 74% smaller than the MB-centered Level C approaches. On top of that, the power-gating control is capable to save 82% of leakage energy. The dynamic energy is treated due to the candidate merging technique, with savings of more than 65%. Due to the jointly off-chip communication and on-chip storage energy savings, the proposed memory hierarchy system is able to meet the MVC constraints for the ME/DE processing.

La technologie des réseaux de capteurs sans fil (RCSF) est l’un des éléments constitutifs de l’Internet des objets (IoT). En raison de leurs caractéristiques de déploiement facile et de leur flexibilité, ils sont utilisés dans de nombreux domaines d’application. Les réseaux à faible consommation et à perte (LLN) sont un type spécial de WSN dans lequel les noeuds sont largement limités en ressources. Convergecast est l’un des modes de communication de base, dans lequel tout le trafic du réseau est destiné à une destination prédéfinie appelée collecteur. Tout en prenant en compte les domaines d’applications IoT, convergecast n’est pas le seul mode de communication sur le réseau. Le récepteur doit envoyer des commandes à certains capteurs pour effectuer des actions. Dans cette application, anycast est un autre mode de communication de base. Dans anycast, le trafic provenant du récepteur est destiné à tout membre d’un groupe de récepteurs potentiels du réseau.Les LLN sont formés de noeuds de capteurs statiques et changent rarement de position. En raison des contraintes de ressources strictes imposées au calcul, à l’énergie et à la mémoire des LLN, la plupart des protocoles de routage ne prennent en charge que les réseaux statiques. Cependant, la mobilité est devenue une exigence importante pour de nombreuses applications émergentes. Dans ces applications, certains noeuds sont libres de se déplacer et de s’organiser dans un réseau connecté. La topologie changerait continuellement en raison du mouvement des noeuds et de l’instabilité des liaisons radio. Il s’agit d’une tâche difficile pour la plupart des protocoles de routage des réseaux LLN afin de s’adapter rapidement au mouvement et de reconstruire la topologie en temps voulu. Le but de cette thèse est de proposer un support de mobilité efficace pour les protocoles de routage dans les réseaux LLN. Nous nous concentrons sur convergecast et anycast, qui sont les modes de communication les plus utilisés dans les réseaux LLN, dans les scénarios de réseau mobile. Nous proposons un mécanisme d’amélioration, nommé RL (RSSI and Level),pour prendre en charge les protocoles de routage dans les réseaux LLN convergecast en mobilité. Ce mécanisme aide le protocole de routage à prendre des décisions plus rapides pour la détection de la mobilité et la mise à jour des voisins du saut suivant,mais souffre d’une surcharge importante. Nous proposons une gestion dynamique des messages de contrôle pour améliorer les performances de RL et l’implémentons en plus du protocole de routage pour réseau à faible consommation (RPL) et nous l’avons nommé RRD (RSSI, Rank and Dynamic). Après une prise en compte de l’hystérésis de la zone de couverture de la plage de transmission des noeuds, nousavons optimisé RRD. Cette version améliorée s’appelle RRD +. Sur la base de RRD+, nous avons proposé MRRD + (Multiple, RSSI, Rank et Dynamic) pour prendre en charge plusieurs puits dans les réseaux LLN convergecast en mobilité. ADUP (Adaptive Downward / Upward Protocol) est une solution de routage prenant en charge simultanément convergecast et anycast dans les réseaux LLN. Nous avons évalué les performances de nos contributions à la fois en simulation avec le simulateur Cooja et en expérience (uniquement pour ADUP) sur des motosTelosB. Les résultats obtenus en simulation et en expérience confirment l’efficacité de nos protocoles de routage. / Wireless Sensor Networks (WSNs) technology is one of the building blocks ofthe Internet of Things (IoT). Due to their features of easy deployment and flexibility,they are used in many application domains. Low-Power and Lossy Networks(LLNs) are a special type of WSNs in which nodes are largely resources constrained.For LLNs, convergecast is one of the basic traffic modes, where all traffic in the networkis destined to a predefined destination called the sink. While considering theIoT application domains, convergecast is not the only traffic mode in the network.The sink needs to send commands to certain sensors to perform actions. In this application,anycast is another basic traffic mode. In anycast, the traffic from the sinkis destined to any member of a group of potential receivers in the network.Traditionally LLNs are formed by static sensor nodes and rarely change positions.Due to the strict resource constraints in computation, energy and memory ofLLNs, most routing protocols only support static network. However, mobility hasbecome an important requirement for many emerging applications. In these applications,certain nodes are free to move and organize themselves into a connectednetwork. The topology would continuously change due to the movement of nodesand radio links instability. This is a hard task for most routing protocols of LLNs toadapt rapidly to the movement and to reconstruct topology in a timely manner.The goal of this thesis is to propose an efficient mobility support for routingprotocols in LLNs. We focus on convergecast and anycast, which are the most usedtraffic modes in LLNs, in mobile network scenarios.We propose an enhancement mechanism, named RL (RSSI and Level), to supportrouting protocols in convergecast LLNs in mobility. This mechanism helps routingprotocol make faster decisions for detecting mobility and updating next-hop neighborsbut suffers from high overhead. We propose a dynamic control message managementto enhance the overhead performance of RL and implement it on top ofRouting Protocol for Low-power and Lossy network (RPL) and we named it RRD(RSSI, Rank and Dynamic). After taking into account hysteresis of the coveragezone of the transmission range of nodes, we optimized RRD. This enhanced versionis called RRD+. Based on RRD+, we proposed MRRD+ (Multiple, RSSI, Rankand Dynamic) to support multiple sinks in convergecast LLNs in mobility. ADUP(Adaptive Downward/Upward Protocol) is a routing solution that supports bothconvergecast and anycast in LLNs concurrently.We evaluated the performance of our contributions in both simulation usingCooja simulator and experiment (only for ADUP) on TelosB motes. The resultsobtained in both simulation and experiment confirm the efficiency of our routingprotocols.

The proliferation of portable systems and mobile computing platforms has increased the need for the design of low power consuming integrated circuits. The increase in chip density and clock frequencies due to technology advances has made low power design a critical issue. Low power design is further driven by several other factors such as thermal considerations and environmental concerns. In low-power design for battery driven portable applications, the reduction of peak power, peak power differential, average power and energy are equally important. In this dissertation, we propose a framework for the reduction of these parameters through datapath scheduling at behavioral level. Several ILP based and heuristic based scheduling schemes are developed for datapath synthesis assuming : (i) single supply voltage and single frequency (SVSF), (ii) multiple supply voltages and dynamic frequency clocking (MVDFC), and (iii) multiple supply voltages and multicycling (MVMC). The scheduling schemes attempt to minimize : (i) energy, (ii) energy delay product, (iii) peak power, (iv) simultaneous peak power and average power, (v) simultaneous peak power, average power, peak power differential and energy, and (vi) power fluctuation. A new parameter called "Cycle Power Function" (CPF) is defined which captures the transient power characteristics as the equally weighted sum of normalized mean cycle power and normalized mean cycle differential power. Minimizing this parameter using multiple supply voltages and dynamic frequency clocking results in the reduction of both energy and transient power. The cycle differential power can be modeled as either the absolute deviation from the average power or as the cycle-to-cycle power gradient. The switching activity information is obtained from behavioral simulations. Power fluctuation is modeled as the cycle-to-cycle power gradient and to reduce fluctuation the mean power gradient (MPG) is minimized. The power models take into consideration the effect of switching activity on the power consumption of the functional units. Experimental results for selected high-level synthesis benchmark circuits under different constraints indicate that significant reductions in power, energy and energy delay product can be obtained and that the MVDFC and MVMC schemes yield better power reduction compared to the SVSF scheme. Several application specific VLSI circuits were designed and implemented for digital watermarking of images. Digital watermarking is the process that embeds data called a watermark into a multimedia object such that the watermark can be detected or extracted later to make an assertion about the object. A class of VLSI architectures were proposed for various watermarking algorithms : (i) spatial domain invisible-robust watermarking scheme, (ii) spatial domain invisible-fragile watermarking scheme, (iii) spatial domain visible watermarking scheme, (iv) DCT domain invisible-robust watermarking scheme, and (v) DCT domain visible watermarking scheme. Prototype implementation of (i), (ii) and (iii) are given. The hardware modules can be incorporated in a "JPEG encoder" or in a "digital still camera".

<p>In the last three decades we have witnessed a remarkable development in the area of integrated circuits. From small logic devices containing some hundred transistors to modern processors containing several tens of million transistors. However, power consumption has become a real problem and may very well be the limiting factor of future development. Designing for low power is therefore increasingly important. To accomplice an efficient low power design, accurate power estimation at early design stage is essential. The aim of this thesis was to set up a power estimation flow to estimate the power consumption at early design stage. The developed flow spans over both RTL- and gate-level incorporating Mentor Graphics Modelsim (RTL-level simulator), Cadence PKS (gate- level synthesizer) and own developed power estimation tools. The power consumption is calculated based on gate-level physical information and RTL- level toggle information. To achieve high estimation accuracy, real node annotations is used together with an own developed on-chip wire model to estimate node voltage swing. </p><p>Since the power estimation may be very time consuming, the flow also includes support for low power design iteration. This gives efficient power estimation speedup when concentrating on smaller sub- parts of the design.</p>

<p>This report is the outcome of a thesis work done at Linköpings University, campus Norrköping. The thesis work was part of the development of a RF transceiver chip for implantable medical applications. The development was done in cooperation with Zarlink Semiconductor AB, located in Järfälla, Stockholm.</p><p>The transceiver is divided into three main blocks, which are the wakeup block, the MAC block and the RF block. The wakeup block is always operating and is awaiting a wakeup request in the 2,45GHz ISM-band. The RF-block is operating in the 400MHz ISM-band and is powered up after wakeup The MAC is the controller of the whole chip. All three blocks in the transceiver structure should be integrated on the same chip, using TSMC 0,18µm process design kit for CMOS (Mixed Signal /RF).</p><p>The purpose of the thesis work was to develop the wakeup circuit for the transceiver. The main purpose was to develop the digital control logic in the circuitry, using RTL-coding (mainly VHDL) but the thesis work also included a system analysis of the whole wakeup block, including the front-end, for getting a better overview and understanding of the project.</p><p>A complete data packet or protocol for the wakeup message on 2,45GHz, is defined in the report and is one of the results of the project. The packet was developed continuously during progress in the project. Once the data packet was defined the incoming RF stage could be investigated. The final proposal to a complete system design for the wakeup block in the RF transceiver is also one of the outcomes of the project. The front-end consists mainly of a LNA, a simple detector and a special decoder. Since the total power consumption on the wakeup block was set to 200nA, this had to be taken under consideration continuously. There was an intention not to have an internal clock signal or oscillator available in the digital part (for keeping the power consumption down). The solution to this was a self-clocking method used on the incoming RF signal. A special decoder distinguishes the incoming RF signal concerning the burst lengths in time. The decoder consists of a RC net that is uploaded and then has an output of 1, if the burst length is long enough and vice versa.</p><p>When it was decided to use a LNA in the front-end, it was found that it could not be active continuously, because of the requirements on low power consumption. The solution to this was to use a strobe signal for the complete front-end, which activates it. This strobe signal was extracted in the digital logic. The strobe signal has a specific duty cycle, depending on the time factors in the detector and in the decoder in the front-end. The total strobing time is in the implemented solution 250µs every 0,5s.</p><p>The digital implementation of the control logic in the wakeupblock was made in VHDL (source code) and Verilog (testbenches). The source code was synthesized against the component library for the process 0,18µm from TSMC, which is a mixed/signal and RF process. The netlist from the synthesizing was stored as a Verilog file and simulated together with the testbenches using the simulator Verilog-XL. The results from the simulations were examined and reviewed in the program Simvison from Cadence. The result was then verified during a pre-layout review together with colleagues at Zarlink Semiconductor AB. During the implementation phase a Design report was written continuously and then used for the pre-layout review. Extracts (source code and testbench) from this document can be found as appendixes to the report.</p>

<p>Rapid development in CMOS technology has resulted in its suitability for the implementation of readout front-end systems in terms of high integration density, and low power consumption yet at the same time posing many challenges for analog circuits design like readout front-end. One of the significant challenges is the low noise design for high speed front-end systems, while at the same time minimizing the power consumption as much as possible.</p><p>A high speed, low noise, low power, and programmable readout front-end system is designed and implemented for an X-ray detector in CMOS 0.18 m technology in this thesis work. The front-end system has a peaking time of 10 ns, which is the highest speed ever reported in the published work. The front-end system is designed to achieve low noise in terms of ENC, and a low power consumption of 2.9 mW. The detector capacitance is the most dominating parameter to low noise, which in turn is directly related to the power consumption. In this thesis work an ENC of 435 electrons is achieved for a detector capacitance of 5 pF and an ENC of 320 electrons for a detector capacitance of 3 pF. Based on the comparison to related published work, a performance improvement of at least two times is achieved taking peaking time, power, ENC, and detector capacitance all into consideration. The output pulse after amplification has peak amplitude of 300 mV for a maximum injected charge of 40000 electrons from the detector.</p><p>The readout front-end system noise performance is strongly dependent on the input MOSFET type, size, and biasing. In this work a PMOS has been selected and optimized as the input device due to its smaller 1/f noise and high gain as compare to NMOS when biased at same currents. The architecture designed in this work consists of a folded cascode CSA with extra cascode in first stage, a pole-zero cancellation circuit to eliminate undershoot, a shaper amplifier, and integrators using Gm-C filter technique. All of these components are optimized for low power while meeting the noise requirements. The whole front-end system is programmed for peaking times of 10, 20, and 40 ns. The programmability is achieved by switching different capacitors and resistors values for all the poles and zeros in the front-end, and by switching parallel transconductance in the Gm-C filters. Finally fine tuning of all the capacitance, resistance, and transconductance values is done to achieve required performance.</p>