A sensor node 'AccuMicroMotion' is proposed that has the ability to detect motion in 6 degrees of freedom for the application of physiological activity monitoring. It is expected to be light weight, low power, small and cheap. The sensor node may collect and transmit 3 axes of acceleration and 3 axes of angular rotation signals from MEMS transducers wirelessly to a nearby base station while attached to or implanted in human body. This dissertation proposes a wireless electronic system-on-a-single-chip to implement the sensor in a traditional CMOS process. The system is low power and may operate 50 hours from a single coin cell battery. A CMOS readout circuit, an analog to digital converter and a wireless transmitter is designed to implement the proposed system. In the architecture of the 'AccuMicroMotion' system, the readout circuit uses chopper stabilization technique and can resolve DC to 1 KHz and 200 nV signals from MEMS transducers. The base band signal is digitized using a 10-bit successive approximation register analog to digital converter. Digitized outputs from up to nine transducers can be combined in a parallel to serial converter for transmission by a 900 MHz RF transmitter that operates in amplitude shift keying modulation technique. The transmitter delivers a 2.2 mW power to a 50 Ù antenna. The system consumes an average current of 4.8 mA from a 3V supply when 6 sensors are in operation and provides an overall 60 dB dynamic range. Furthermore, in this dissertation, a methodology is developed that applies accelerated electrical stress on MOS devices to extract BSIM3 models and RF parameters through measurements to perform comprehensive study, analysis and modeling of several analog and RF circuits under hot carrier and breakdown degradation.

This work presents novel continuous-time delta-sigma modulator architectures with low-power consumption and improved signal transfer functions which are suitable for wideband A/D conversion in wireless applications, e.g., 3G and 4G receivers. The research has explored two routes for improving the overall performance of continuous-time delta-sigma modulator. The first part of this work proposes the use of the power efficient Successive-Approximations (SAR) architecture, instead of the conventional Flash ADC, as the internal quantizer of the delta-sigma modulator. The SAR intrinsic latency has been addressed by means of a faster clock for the quantizer as well as full-period delay compensation. The use of SAR quantizer allows for increasing the resolution while reducing the total power consumption and complexity. A higher resolution quantizer, made feasible by the SAR, would allow implementing more aggressive noise shaping to facilitate wideband delta-sigma A/D conversion at lower over-sampling-rates. As proof of concept, a first-order CT delta-sigma modulator with a 5-bit SAR quantizer is designed and implemented in a 130 nm CMOS process which achieves 62 dB dynamic range over 1.92 MHz signal bandwidth meeting the requirements of the WCDMA standard. The prototype modulator draws 3.1 mW from a single 1.2 V supply and occupies 0.36 mm2 of die area. The second part of this research addresses the issue of out-of-band peaking in the signal-transfer-function (STF) of the widely used feedforward structure. The STF peaking is harmful to the performance of the modulator as it allows an interferer to saturate the quantizer and result in severe harmonic distortion and instability. As a remedy to this problem a general low-pass and peaking-free STF design methodology has been proposed which allows for implementing an all-pole filter in the input signal path for any given NTF. Based on the proposed method, the STF peaking of any feedforward modulator can be eliminated using extra feed-in paths to all the integrator inputs. A major drawback of the conventional feedforward topology having low-pass STF is the large sensitivity of the STF to the coefficients. In particular, component mismatch, due to random errors in the relative values of individual resistors or capacitors, can significantly degrade the anti-aliasing of the CT modulator and give rise to the unwanted STF peaking. To solve this problem two new architectures, namely dual-feedback and dual-feed-in are proposed which allow us to synthesize a low-pass STF with a smaller number of coefficients than the feedforward structure. The dual-feedback structure which shows significantly lower sensitivity to coefficient mismatch is extensively analyzed and simulated. Also for proof of concept a third-order modulator is implemented in a 130 nm CMOS process which achieves 76 dB dynamic-range over 5 MHz signal bandwidth meeting, for example, the requirements of a DVB-H receiver standard. In addition the modulator shows 77 dB anti-aliasing and less than 0.1 dB worst-case STF peaking. The measured power consumption of the modulator is 6 mW from a single 1.2 V and the die area is 0.56 mm2.

Global navigation satellite systems (GNSS) have radically changed business, industry, and society, shaping the way we transport, navigate, and generally live every day. After all these years, however, GNSS location information remains only valuable outdoors, leaving indoor environments where people dwell most of the time without proper localization support. Many technologies and systems have approached this problem including optical, inertial, ultrasonic, and radio-frequency (RF), to name a few; yet the problem remains. In this thesis, inspired by the indisputable success of GNSS and the re-emergence of ultra-wideband (UWB) radios to the forefront of technology, we aim to change the state of affairs in RF localization by proposing novel clean-slate UWB ranging and localization schemes based on concurrent transmissions. These are generally considered harmful for communication but become a rich source of localization information when combined with knowledge of the channel impulse response (CIR). Our first novel contribution lies in the concept of concurrent ranging, which allows mobile nodes to simultaneously measure the distance to multiple devices—hereafter, called responders—removing the need for the wasteful long packet exchanges traditionally used for ranging and localization. Different from conventional schemes, which spread responder transmissions over time, we force responders to transmit concurrently and let their signals “fuse” in the wireless channel; the resulting impulse response, as measured by commercial UWB radios, contains all the necessary timing information to extract the desired distance to all responders. This first contribution, however, also serves us to realize the many challenges ahead to unlock the real power of concurrent transmissions for localization. We address these challenges along the way, starting with Chorus, our second contribution. Chorus exploits an anchor infrastructure that transmits packets concurrently. Mobile nodes listen for these transmissions and measure from the CIR the time difference of arrival (TDoA) of the concurrent signals, privately computing their own position at a high rate using hyperbolic localization. This reverse TDoA scheme, although simple in concept, is extremely powerful in that it enables passive self-localization of infinitely many targets at once, a feature largely missing in the RF literature. In Chorus, we address the difficult challenges to reliably detect and identify the signal from the different responders. Yet, the limited transmission precision of commercial UWB transceivers constrains the many benefits of Chorus. In this context, we i) contribute a model to ascertain the impact of the transmission uncertainty on concurrent transmissions, and ii) address the issue with a compensation mechanism that fine-tunes the local oscillator frequency of responders while they prepare to transmit, allowing us to simultaneously tackle the impact of clock drift on distance estimation. We demonstrate in our evaluation that with this compensation mechanism we can schedule transmissions with < 1 ns error, removing the need to share timestamps to precisely measure distance. We rebuild concurrent ranging around this mechanism, obtaining decimeter-level ranging and localization at a fraction of the cost of conventional schemes. These results turn concurrent ranging into an immediately applicable technique that new systems can now exploit, benefiting from a different set of trade-offs hitherto unavailable. Further, the TX compensation mechanism can be directly applied to Chorus, similarly making fast and accurate passive self-localization a tangible reality. We continue our endeavor with a systematic characterization of the conditions under which UWB concurrent transmissions succeed to provide reliable ranging and communication across different complex channels. The results we put forth empower developers to fully exploit concurrent transmissions in their designs, potentially inspiring a new wave of ranging, and also communication, primitives that can bring to UWB the same striking benefits found in low-power narrowband radios. The thesis is completed by looking at other challenges preventing the wide adoption of UWB localization systems, namely, large-scale operation, energy efficiency, and the complexity to install anchor deployments. We tackle these aspects in the last part of the thesis with three additional contributions. First, we propose Talla, a TDoA system that provides seamless large-scale localization for many tags across cells of time-synchronized anchors. Secondly, we fuse UWB ranging with odometry information and build an uncertainty model that only triggers new UWB estimates if and when needed, reducing consumption and channel utilization while satisfying the application-specific demands in terms of accuracy. And thirdly, we build state-of-the-art mechanisms to automatically compute the positions of all anchors deployed across large areas based on ranging information, facilitating anchor network deployment for the many UWB-based real-time location systems (RTLS) to come. Overall, this thesis changes the landscape of UWB localization with a new set of potentially disruptive schemes and systems that exploit the peculiar benefits of concurrent transmissions and that consequently redefine the trade-offs of the technology.

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The digital transformation of production and living is one research field with potential to overcome arising ecological and social problems. Digital technologies associated with the internet of things (IoT) enable new intelligent, sustainable and efficient production techniques. Massive monitoring and optimal controlling of industrial processes (smart fabrication) and human living (smart cities) ultimately results in the reduction of resource demands. Key parts of these new applications are microelectronic sensor read-out systems connected in IoT sensor networks, which measure and transmit multi-physical environmental parameters. In practical applications, large quantities (tens to hundreds) of sensor nodes are used. Circuitry with minimized power consumption is necessary to ensure long operation time and low maintenance cost. The motivation of this work is the development of a low-power, low-cost, microelectronic sensor read-out circuit, which combines flexibility of employed IoT sensor hardware with flexibility in complementary metal oxide semiconductor (CMOS) technology. This work covers design and implementation of an integrated multi-sensor analog frontend (AFE) with a near-zero power consumption below 10 μW, which offers above-state of the art, real-time configurability of key parameters and flexibility in application and technology. It aims for IoT environmental sensing applications, where energy-efficient, medium-speed and medium-resolution data acquisition of different environmental sensor signals is required. Its innovative architecture supports a wide variety of voltage ranges, frequency levels and sensor types, while maintaining energy-efficiency in different operation modes. Samples of the developed AFE are employed in autonomous sensor nodes for smart cities and smart factories, where they collect and process environmental parameters such as weather (light, temperature) and gases. The durable sensor nodes are operated by energy harvester sources and transmit data wirelessly, demonstrating one practical realization of an autonomous zero-power IoT network. Moreover, the technological flexibility of the AFE is investigated by migrating one key building block, which is the analog-to-digital converter, to different CMOS technologies. Conclusions for the optimal CMOS node for the entire AFE are drawn by performance comparison. / Die digitale Transformation von Industrie und Gesellschaft hat das Potential, zur Bewältigung bevorstehender ökologischer und sozialer Krisen beizutragen. Moderne digitale Technologien, wie das Internet der Dinge (engl. internet of things, IoT), ermöglichen intelligente Produktionsketten von nie dagewesener Effizienz und Nachhaltigkeit. Mit feingranularer Kontrolle und optimierter Steuerung soll schlussendlich der Ressourcenverbrauch von geregelten Prozessen, zum Beispiel in der smarten Fabrik und in der smarten Stadt, verringert werden. Schlüsseltechnologien dieser neuen Anwendungsfälle sind mikroelektronische Sensor-Auslese-Schaltungen, die multi-physikalische Umweltparameter messen und drahtlos in IoT-Netzwerke übertragen. In praktisch relevanten Szenarien bestehen solche Netzwerke aus dutzenden bis tausenden Sensorknoten. Unter unternehmerischen Gesichtspunkten sind lange Betriebszeiten ohne Batteriewechsel und geringe Wartungskosten notwendig, welche u. a. durch Elektronik mit minimalem Energieverbrauch erreicht werden können. Die Motivation dieser Arbeit ist die Entwicklung einer energiesparenden und kostengünstigen mikroelektronischen Sensor-Auslese-Schaltung, die Flexibilität in der Auswahl der eingesetzten IoTSensoren mit Flexibilität in der Auswahl der Halbleiter-Technologie (engl. complementary metal oxide semiconductor, CMOS) verbindet. Diese Arbeit behandelt Entwurf und Implementierung eines integrierten Multi-Sensor-Analog-Frontends (AFE) mit extrem geringer Leistungsaufnahme von weniger als 10 μW (engl. near zero power), dessen Echtzeit-Konfigurierbarkeit von relevanten Parametern und dessen Flexibilität in Anwendung und Technologie ein Niveau erreicht, das sich über dem Stand der Technik befindet. Es soll in IoT-Anwendungen eingesetzt werden, in denen die energieeffiziente Verarbeitung von verschiedenen Umwelt-Sensor-Signalen mit mittlerer Geschwindigkeit und mittlerer Genauigkeit gefordert ist. Mit seiner innovativen Architektur unterstützt es einen großen Bereich von Eingangsspannungen, Eingangs-Frequenzen und Sensor-Typen in unterschiedlichen Operations-Modi, wobei seine Energieeffizienz nicht beeinträchtigt wird. Exemplare des entworfenen AFEs werden durch den Einsatz in autonomen Sensorknoten für die smarte Stadt und die smarte Fabrik, wo sie Umweltparameter wie Wetter (Licht, Temperatur) und Gaskonzentrationen sammeln und verarbeiten, in die Anwendung überführt. Die langlebigen Sensorknoten, die ihre Energie von alternativen Quellen beziehen und via drahtloser Funkverbindung kommunizieren, demonstrieren eine praktische Realisierung eines autonomen Zero-Power-IoT Netzwerkes. Zusätzlich untersucht diese Arbeit die Technologie-Flexbilität des AFEs, indem ein Kernbaustein, der Analog-Digital-Wandler, in verschiedene CMOS-Technologien migriert wird. Anhand eines Vergleichs werden Schlüsse für den optimalen Technologieknoten des gesamten AFEs gezogen.

Smart cameras operate mostly in sleep mode, which is light load for power supplies. Typical buck converter applications have low efficiency under the light load condition, primarily from their power stage and control being optimized for heavy load. The battery life of a smart camera can be extended through improvement of the light load efficiency of the buck converter. This thesis research investigated the first stage converter of a car black box to provide power to a microprocessor, camera, and several other peripherals. The input voltage of the converter is 12 V, and the output voltage is 5 V with the load range being 20 mA (100 mW) to 1000 mA (5000 mW). The primary design objective of the converter is to improve light load efficiency. A 3-level buck converter and its control scheme proposed by Reusch were adopted for the converter in this thesis. A 3-level buck converter has two more MOSFETs and one more capacitor than a synchronous buck converter. Q1 and Q2 are considered the top MOSFETs, while Q3 and Q4 are the synchronous ones. The extra capacitor is used as a second power source to supply the load, which is connected between the source of Q1 and the drain of Q2 and the source of Q3 and the drain of Q4. The methods considered to improve light load efficiency are: PFM (pulse frequency modulation) control scheme with DCM (discontinuous conduction mode) and use of Schottky diodes in lieu of the synchronous MOSFETs, Q3 and Q4. The 3-level buck converter operates in CCM for heavy load above 330 mA and DCM for light load below 330 mA. The first method uses a COT (constant on-time) valley current mode controller that has a built in inductor current zero-crossing detector. COT is used to implement PFM, while the zero-crossing detector allows for DCM. The increase in efficiency comes from reducing the switching frequency as the load decreases by minimizing switching and gate driving loss. The second method uses an external current sense amplifier and a comparator to detect when to shut down the gate drivers for Q3 and Q4. Schottky diodes in parallel with Q3 and Q4 carry the load current when the MOSFETs are off. This increases the efficiency through a reduction in switching loss, gate driving loss, and gate driver power consumption. The proposed converter is prototyped using discrete components. LTC3833 is used as the COT valley current mode controller, which is the center of the control scheme. The efficiency of the 3-level buck converter was measured and ranges from 82% to 95% at 100 mW and 5000 mW, respectively. The transient response of the converter shows no overshoot due to a 500 mA load step up or down, and the output voltage ripple is 30 mV. The majority of the loss comes from the external components, which include a D FF (D flip-flop), AND gate, OR gate, current sense chip, comparator, and four gate drivers. The proposed converter was compared to two off-the-shelf synchronous buck converters. The proposed converter has good efficiency and performance when compared to the other converters, despite the fact that the converter is realized using discrete components. / Master of Science

General-purpose step-down converter is essential in electronic system for processing energy from high-voltage rail to low-voltage circuits. The applications can be found at the auxiliary supplies in automobile, industrial and communication systems. Buck converter is a common circuit topology to fulfill step-down conversion, especially in low-power application since it is well-studied and straightforward. However, it suffers from low duty cycle under high step-down condition, and typically operates in continuous conduction mode (CCM) that generates large switching loss. On the other hand, as an extension of the buck converter, tapped-inductor (TI) buck converter has larger duty cycle while maintaining the structural simplicity. Therefore, the main objective of this thesis is to explore the potential of TI buck converter as a wide conversion range, high power density and high efficiency topology for low power application. To achieve high efficiency at switching frequency of MHz-level, synchronous conduction mode (SCM) is applied for turn-on losses elimination. The operation principle and power stage design of SCM TI buck is first introduced. The design of high switching frequency coupled inductor is emphasized since its size plays a critical role in power density. Loss breakdown is also provided to perform a comprehensive topological study. Secondly, detailed zero-voltage-switching (ZVS) condition of SCM TI buck is derived so that the converter does not experience redundant circulating energy. The experimental results of 15-W SCM TI buck converter prototypes are provided with 90.7% of peak power stage efficiency. The size of coupled inductor is down to 116 mm3. To enhance light-load efficiency, a variable frequency control scheme based on derived ZVS conditions is implemented with the switching frequency ranging from 2 MHz to 2.9 MHz. / Master of Science / General-purpose step-down converter is essential in electronic system for processing energy from high-voltage rail to low-voltage circuits. The applications can be found at the auxiliary supplies in automobile, industrial and communication systems. Typically, the ultimate goals of general-purpose step-down converter are versatility, high efficiency and compact size. Recently, tapped-inductor (TI) buck converter is studied since it could overcome the drawback of commonly used buck converter under high step-down conversion. Therefore, the potential of TI buck converter as a general-purpose step-down converter candidate is explored in this thesis, including control method, hardware design, etc. The thesis verifies that TI buck converter could have compact size while remaining efficient and adaptable.