Post-Silicon validation of a designed ASIC is an essential step in the product development process. During the validation process, all specifications of the ASICs have to be controlled in a lab environment. Serializer/Deserialiser(SerDes) blocks in an ASIC are used to perform high-speed serial data communication between distinct integrated circuits. The goal of the thesis is to validate the power consumption of SerDes IP blocks provided by different vendors in an ASIC. To validate power consumption, current and voltage values are read from power supply lines. Then these values are digitized and stored on a Raspberry Pi. To perform these operations, the initial firmware provided by vendors is improved to control SerDes operations, and software is developed to control the Raspberry Pi. Power measured operation is performed for every possible data rate for each SerDes modules. Power measurement is also performed for different temperature range in industry standards with the highest possible data rate for each SerDes IP block. As a final step, measured power consumption values are compared to vendors’ data. / Validering av en designad ASIC efter kisel är ett viktigt steg i produktutvecklingsprocessen. Under valideringsprocessen måste alla specifikationer för ASIC kontrolleras i en laboratoriemiljö. Serializer / Deserialiser (SerDes) -block i en ASIC används för att utföra höghastighets seriell datakommunikation mellan distinkta integrerade kretsar. Målet med avhandlingen är att validera strömförbrukningen för SerDes IP-block som tillhandahålls av olika leverantörer i en ASIC. För att validera strömförbrukningen läses strömoch spänningsvärden från strömförsörjningsledningarna. Sedan digitaliseras dessa värden och lagras på en Raspberry Pi. För att utföra dessa operationer förbättras den inledande firmware som tillhandahålls av leverantörer för att styra SerDesoperationer och programvara utvecklas för att styra Raspberry Pi. Effektmätt operation utförs för varje möjlig datahastighet för varje SerDes-modul. Mätoperationer utförs också för olika temperaturintervall i branschstandarder med högsta möjliga datahastighet för varje SerDes IP-block. Som ett sista steg jämförs uppmätta energiförbrukningsvärden med leverantörens data.

<p>In addition to the performance, low power design became an important issue in the design process of mobile embedded systems. Mobile electronics with rich features most often involve complex computation and intensive processing, which result in short battery lifetime and particularly when low power design is not taken in consideration. In addition to mobile computers, thermal design is also calling for low power techniques to avoid components overheat especially with VLSI technology. Low power design has traced a new era. In this thesis we examined several techniques to achieve low power design for FPGAs, ASICs and Processors where ASICs were more flexible to exploit the HW oriented techniques for low power consumption. We surveyed several power estimation methodologies where all of them were prone to at least one disadvantage. We also compared and analyzed the power and energy consumption in three different designs, which perform matrix multiplication within Altera platform and using state-of-the-art FPGA device. We concluded that NIOS II\e is not an energy efficient alternative to multiply nxn matrices compared to HW matrix multipliers on FPGAs and configware is an enormous potential to reduce the energy consumption costs.</p>

In addition to the performance, low power design became an important issue in the design process of mobile embedded systems. Mobile electronics with rich features most often involve complex computation and intensive processing, which result in short battery lifetime and particularly when low power design is not taken in consideration. In addition to mobile computers, thermal design is also calling for low power techniques to avoid components overheat especially with VLSI technology. Low power design has traced a new era. In this thesis we examined several techniques to achieve low power design for FPGAs, ASICs and Processors where ASICs were more flexible to exploit the HW oriented techniques for low power consumption. We surveyed several power estimation methodologies where all of them were prone to at least one disadvantage. We also compared and analyzed the power and energy consumption in three different designs, which perform matrix multiplication within Altera platform and using state-of-the-art FPGA device. We concluded that NIOS II\e is not an energy efficient alternative to multiply nxn matrices compared to HW matrix multipliers on FPGAs and configware is an enormous potential to reduce the energy consumption costs.