Minimizing the dynamic power consumption of a circuit is becoming a more and more important issue for digital circuit design in the age of portable electronics. Among all the arithmetic circuits, addition is the most fundamental operation. Therefore, designing low power adder is an important and necessary research area. In this thesis, the dynamic switching power consumption of ripple carry adder, carry look ahead adder, carry skip adder, carry select adder, and prefix adder are discussed. The power factor, the sum of products of probability and fan-out of all internal nodes, is presented. This thesis also studies the power and time trade-off with efficiency index which is the product of power factor and worst case gate counts. The result shows that the carry look ahead adder has the lowest efficiency index in the design of a 64 bit adder. The carry skip adder is the best one in a design of a 16 and 32 bit adder. The ripple carry adder is the best choice for an 8 bit adder. This study also presents a low power prefix adder design which will reduce the power consumption of the prefix adder without lost of performance. / Graduation date: 1998

An active-matrix electroluminescent (AMEL) design tool has been developed for the simulation of AMEL display devices. The AMEL design tool is a software package that simulates AMEL device operation using a lumped parameter circuit model. The lumped parameter circuit model is developed primarily to address AMEL power dissipation issues. The AMEL design tool provides a user-friendly approach for investigating the AMEL display device through the AMEL lumped parameter circuit model. The AMEL design tool is programmed in C with a standard Microsoft Windows interface. Three techniques for power reduction have been identified and investigated: increasing the high voltage NDMOS transistor breakdown voltage, parasitic capacitance optimization, and development of a low voltage phosphor. / Graduation date: 1998

Thesis (M.S.)--Oregon State University, 2007. / Printout. Includes bibliographical references (leaves 82-86). Also available on the World Wide Web.

Fortums electric grid in Norra Djurgårdsstaden is a test grid for smart equipment and they are investigating new techniques and ways to improve the quality of the grid. With the quality improvements that are researched, a "self-restoring system" is a part of the research with the intention to lower the amount of outages and shorten the time it takes to restore faults. This thesis can be seen as a part of the optimization process of the grid in Norra Djurgårdsstaden where the benefits with a basic self-restoring system have been investigated on low voltage level. In the thesis the self-restoring system has been classified into a "basic" and an "advanced" category. The basic self-restoring system cross-connect several feeding paths by cross-connecting different low voltage grids and use mechanical equipment to change between cables when a fault in a cable occurs. The advanced self-restoring system uses several feeders and smart grid technology with equipment and softwares which communicate and visualize the grid. The difference between the systems is that the advanced system can visualize the grid and is able to tell when and where faults have occurred to a more detailed level. The advanced system can also calculate the power available and does not need the same amount of cables for redundancy because it can command users to lower their consumption when an outage has occurred. A decision was made to only investigate the technique on low voltage level because a basic system already exists on medium voltage in Norra Djurgårdsstaden. Results show that investing in a basic self-restoring system in Norra Djurgårdsstaden would cost about 2 million SEK and lower the total amount of outages for the customers in the area from 45 minutes per customer and year down to about 41 minutes. The reason why the decrease is only four minutes per year and customer is because faults occurring on higher voltage level cannot be reduced with the system. It is totally about 10 % of the faults that occur on low voltage level. One conclusion from the thesis is that the reduction in quality costs which are because to the lowered outages will not be enough to pay back the investment. More outage-time per customer and year need to be prevented with the system or the customers need to value reduced outages significantly more.

No description available.

A dual-mode second-order Multirate Multibit Sigma Delta (MM-SD) modulator is implemented in a 90nm digital CMOS process for application in the baseband path of RF receivers. Low power consumption is achieved through a new integrator structure and a dedicated timing scheme along with aggressive capacitor scaling in the second stage of the modulator loop. Fabricated prototype achieves 68.6dB peak Signal-to-Noise and Distortion ratio (SNDR) in the 200 kHz GSM band and requires 1.1mA of total current from a 1.5V supply. This dual-mode design also achieves 42.8dB SNDR in the 1.94 MHz WCDMA band with only 1.9mA of total current consumption.

Class D power amplifier applies in high efficiency circuit. In hearing aid system, we require high power efficiency, low-voltage and low-power. The operation of frequency is low frequency. All the circuits are designed based on the TSMC 035 CMOS process technology. The supply voltage is 1.5V and the input signal is 4KHz. Simulation results show that the Class D power efficiency is high efficiency amplifier. When 0.3V of 2KHz input signal is applied, The maximum THD is 0.63% and static current is 4uA and the efficiency is 83.6%.

The topic of this thesis is to propose a dual-tracking clock data recovery device and method for LVDS. Particularly, it is related to a high speed data transmission which utilizes phase-locked loops (PLL) to trace and track two eyes (left eye and right eye), called dual-tracking, to align data sampling at the middle of data eye. Hence, the detection of the data is ensured to be optimal and the BER (bit error rate) is drastically reduced.

We propose two kinds of 1.0 Gbps LVDS ( low voltage differential signaling ) transceivers for LCD ( liquid crystal display ) in this thesis. LVDS has become a popular choice for high-speed serial links in large-sized display units. Our designs are an I/O interface circuit for Gbps operation which is fully complied with the IEEE STD 1596.3 (LVDS). A step-down voltage regulator is employed to reject the noise coupled in the system power supply. In the first design of the transmitter, a CMFB (common mode feedback) circuitry is utilized to stabilize the common voltage in a pre-defined range. In the second design of the transmitter, we try to use a DC bias circuitry to stabilize output common mode voltage to further improve the stability of the common mode voltage. By contrast, a regenerative circuit which provides a positive feedback loop gain between the preamplifier and the output buffer in the receiver such that the received bit streams can be correctly restored

In this thesis, we propose a low voltage low power wide-tuning 4th-order butterworth low-pass OTA-C channel selection filter. It is implemented by using TSMC 0.35£gm 2P4M CMOS technology. The drain voltage of triode-biased input transistors of the OTA is regulated through an active-cascode loop for low power and wide-tuning range. The Gm-C channel selection filter can be programmed from 0.5 to 12MHz. The OTA also employs a circuit to reduce the OTA output current in a high transconductance mode and the total power consumption of filter is suppressed below 3mW.