Advances toward increased integration and complexity of radio frequency (RF) andmixed-signal integrated circuits reduce the effectiveness of contemporary testmethodologies and result in a rising cost of testing. The focus in this research is on thecircuit-level implementation of alternative test strategies for integrated wirelesstransceivers with the aim to lower test cost by eliminating the need for expensive RFequipment during production testing.The first circuit proposed in this thesis closes the signal path between the transmitterand receiver sections of integrated transceivers in test mode for bit error rate analysis atlow frequencies. Furthermore, the output power of this on-chip loopback block wasmade variable with the goal to allow gain and 1-dB compression point determination forthe RF front-end circuits with on-chip power detectors. The loopback block is intendedfor transceivers operating in the 1.9-2.4GHz range and it can compensate for transmitterreceiveroffset frequency differences from 40MHz to 200MHz. The measuredattenuation range of the 0.052mm2 loopback circuit in 0.13µm CMOS technology was 26-41dB with continuous control, but post-layout simulation results indicate that theattenuation range can be reduced to 11-27dB via optimizations.Another circuit presented in this thesis is a current generator for built-in testing ofimpedance-matched RF front-end circuits with current injection. Since this circuit hashigh output impedance (>1k up to 2.4GHz), it does not influence the input matchingnetwork of the low-noise amplifier (LNA) under test. A major advantage of the currentinjection method over the typical voltage-mode approach is that the built-in test canexpose fabrication defects in components of the matching network in addition to on-chipdevices. The current generator was employed together with two power detectors in arealization of a built-in test for a LNA with 14% layout area overhead in 0.13µm CMOStechnology (<1.5% for the 0.002mm2 current generator). The post-layout simulationresults showed that the LNA gain (S21) estimation with the external matching networkwas within 3.5% of the actual gain in the presence of process-voltage-temperaturevariations and power detector imprecision.

Today, the advances in Complementary MetalOxideSemiconductor (CMOS) technology have guided the progress in the wireless communications circuits and systems area. Various new communication standards have been developed to accommodate a variety of applications at different frequency bands, such as cellular communications at 900 and 1800 MHz, global positioning system (GPS) at 1.2 and 1.5 GHz, and Bluetooth andWiFi at 2.4 and 5.2 GHz, respectively. The modern wireless technology is now motivated by the global trend of developing multi-band/multistandard terminals for low-cost and multifunction transceivers. Exploring the unused 10-66 GHz frequency spectrum for high data rate communication is also another trend in the wireless industry. In this dissertation, the challenges and solutions for designing a multi-band/multistandard mobile device is addressed from system-level analysis to circuit implementation. A systematic system-level design methodology for block-level budgeting is proposed. The system-level design methodology focuses on minimizing the power consumption of the overall receiver. Then, a novel millimeter-wave dual-band receiver front-end architecture is developed to operate at 24 and 31 GHz. The receiver relies on a newly introduced concept of harmonic selection that helps to reduce the complexity of the dual-band receiver. Wideband circuit techniques for millimeterwave frequencies are also investigated and new bandwidth extension techniques are proposed for the dual-band 24/31 GHz receiver. These new techniques are applied for the low noise amplifier and millimeter-wave mixer resulting in the widest reported operating bandwidth in K-band, while consuming less power consumption. Additionally, various receiver building blocks, such as a low noise amplifier with reconfigurable input matching network for multi-band receivers, and a low drop-out regulator with high power supply rejection are analyzed and proposed. The low noise amplifier presents the first one with continuously reconfigurable input matching network, while achieving a noise figure comparable to the wideband techniques. The low drop-out regulator presented the first one with high power supply rejection in the mega-hertz frequency range. All the proposed building blocks and architecture in this dissertation are implemented using the existing silicon-based technologies, and resulted in several publications in IEEE Journals and Conferences.

<p>In this Master's thesis, a direct-conversion receiver front-end has been designed in a 0.18um CMOS technology. </p><p>Direct-conversion receivers (DCR) have obvious advantages over the heterodyne counterpart. Since the intermediate frequency (IF) is zero, the problem of image is circumvented. As a result, no front-end image reject filter is required and the channel selection requires only a low-pass filter, which makes it easy to integrate directly on chip. However, the DCR also suffers from several drawbacks such as extreme sensitivity to DC offsets, 1/f noise, local oscillator (LO) leakage/radiation, front-end nonlinearity and I/Q mismatch. This implies very high demands on the DCR front-end. </p><p>The front-end comprises a low-noise amplifier (LNA) and a mixer. Different LNA and mixer architectures has been studied and from the mentioned inherited problems with direct conversion, one proposal for a solution is a differential source degenerated LNA and a differential harmonic mixer, which has been designed and simulated. </p><p>The LNA has a gain of 12dB, a noise figure of 3.6dB and provides a return loss better than -15dB. The overall noise figure of the signal path is 8dB and the overall IIP3 and IIP2 is -12dBm and 31dBm, respectively.</p>

In this thesis, the circuits which comprise the front-end of a millimeter-wave transmit-receive module are investigated using a state-of-the-art 90 nm SiGe BiCMOS process for use in radar remote sensing applications. In Chapter I, the motivation for a millimeter-wave radar in the context of space-based remote sensing is discussed. In addition, an overview of Silicon-germanium technology is presented, and the chapter concludes with a discussion of design challenges at millimeter-wave frequencies. In Chapter II, a brief history of radar technology is presented - the motivations leading to the development of the transmit-receive module for active electronically scanned arrays are discussed, and the critical components which reside in nearly every high-frequency transmit-receive module are introduced. In Chapter III, the design and results of a W-band single-pole, double-throw switch using SiGe p-i-n diodes are discussed. In particular, the design topology and methods used to achieve low-loss and high power handling over a wide matching bandwidth without sacrificing isolation are described. In Chapter IV, the design and results of a W-band low-noise amplifier using SiGe HBT's are discussed. The design methodologies used to achieve high gain and exceptional noise performance over a wide matching bandwidth are described. Concluding remarks and a discussion of future work are in Chapter V.

Ces dernières années, le développement durable, notamment le contrôle de la consommation de nos appareils électriques, est devenu un enjeu majeur de notre société. L'essor de la domotique associé à cette problématique implique la nécessité d'optimiser le bilan énergétique de chaque dispositif électrique. L'objectif de cette thèse est la réalisation d'un amplificateur faible bruit (LNA) qui propose deux modes de fonctionnement suivant la qualité du signal reçu: un mode haute performance et un mode basse consommation.Afin de satisfaire la problématique liée aux systèmes multistandard, l'architecture sélectionnée pour l'amplificateur faible bruit est la topologie distribuée. En effet, elle est connue pour ses performances en terme de bande passante et permet un gain en puissance accordable. Une méthode de conception est proposée, basée sur la technologie GaAs de la fonderie TriQuint Semiconducteur Texas. Les mesures réalisées sur le LNA dans sa configuration haute performance se situe au niveau de l'état de l'art. Pour le mode basse consommation, on obtient de bonnes performances tout en réduisant sa consommation de 91%.Enfin, une stratégie de reconfiguration innovante est proposée basée sur l'intégration de notre LNA dans un récepteur homodyne. Elle permet de réduire de manière significative la consommation du récepteur, dans le cas où la puissance reçue permet un fonctionnement en mode basse consommation (contraintes sur le Bit Error Rate (BER) vérifiées). En considérant chaque puissance reçue de manière équiprobable, notre récepteur reconfigurable a une consommation réduite de 77% par rapport à un récepteur classique qui possède un seul mode de fonctionnement (mode haute performance). / In recent years, the sustainable development, especially the control of the electrical appliances' consumption, has became a major issue in our society. The optimisation of each electrical devices' energy is needed to reduce the consumption of home appliances. The objective of this thesis is the realization of a low noise amplifier (LNA) that offers two modes of operation depending on the quality of the received signal: a high performance mode and a low consumption mode.In order to meet the problem related to multistandard systems, the distributed architecture is selected for low noise amplifier. Indeed, it is known for its wide bandwidth and tunable power gain. A design method is proposed, which is based on GaAs technology of TriQuint Semiconductor Texas foundry. The LNA's high performance mode measurement results is at the level of the state of the art. For the low consumption mode, LNA shows good performance while reducing power consumption by 91%.Finally, an innovative reconfiguration strategy is defined. It's applied to a homodyne receiver based on the integration of our LNA. It reduces significantely the receiver's consumption in case where the received power allows the receiver operates in low power mode (constraint of the Bit Error Rate (BER) is verified). Considering each received power is equiprobable, our reconfigurable receiver saves consumption by 77% compared to a conventional receiver that has a single mode (high performance mode).

This work is focused on proposal of receiver with Integrated Antenna Tuner operating at 28 MHz. The design was primarily focused on simplicity and low power consumption. The receiver is adapted for SSB modulation. This work was realized for the transmission of audio signals. SSB modulation is far more efficient in terms of the radio spectrum used. First part of this thesis describes about the Antenna Tuner and block diagram of a receiver. Next parts are focused on proposal of individual blocks of the receiver, especially its most important parts. Finally, the overall evaluations of the design characteristics of SSB receivers with Integrated Antenna Tuner are discussed.

This project describesa microwave antenna for GNSS and low noise amplifier. Mikrostrip antenna is a modern type of antenna. This mikrostrip antenna is Dual – band antenna with circual polarization. The thesis describes how to make anantenna, what a circular polarization is, whata patch antenna is and what GNSS is. Low noise amplifier amplifies the antenna output signal.

Thesis discusses the possibility of using MEMS microphones in measuring systems. Describes the characteristics of MEMS components and shows possible realization of analog to digital signal convertor when a microphone with analog output is used. Design of the amplifier is made with respect to low noise and low power consumption. Also is shown the possibility of using antialliasing filter as microphone frequency response correction at the same time.

This masters thesis deals with low noise amplifier design for frequency range 1 GHz - 3 GHz. There is a short theoretical introduction in the first part of the thesis. There are described parameters and properties of transistors and general two-ports. Description of the noise characteristics two-ports follows. The next capture contains design of two-stage amplifiers. One of them is with a microstrip filter between stages and the second one is with combline filter on input of the amplifier. The amplifiers and the microstrip filter were designed in program ANSOFT Designer. The design of combline filter was realised in program CST Microwave Studio. Both amplifiers ware made and their properties ware compared with simulations.

This work presents design and full implementation of a fast switchable and band-tunable 5 - 7.5 GHz low noise amplifier (LNA) in a 45nm CMOS SOI technology. The target application are wake-up receivers that employ aggressive duty cycling. Based on a cascode topology, the LNA utilizes a transformer for its 50 input matching as well as a balun with a capacitor bank to realize 8 digitally selectable bands. According to measurement results, the fabricated LNA exhibits a voltage gain of 18 - 21 dB while drawing a current of merely 2.2mA from a 1V supply. At all the 8 bands from 5 to 7.5 GHz, the input reflection coefficient lies below -8 dB, and the noise figure ranges from 7.8 to 6.2 dB. The LNA is able to settle in less than 9.5 ns