International Telemetering Conference Proceedings / October 23-26, 2000 / Town & Country Hotel and Conference Center, San Diego, California / This student paper was produced as part of the team design competition in the University of Arizona course ECE 485, Radiowaves and Telemetry. It describes the design of a telemetry system for the University of Arizona’s Daedalus solar car. This is a distributed, low-power, telemetry-on-demand system that solves many of the problems typically encountered in this specialized telemetry application. The topology of the distributed microcontroller system is shown, as are optimal command and data packet structures. Also featured is a high-gain, low profile antenna system designed specifically for the solar car. Additionally, a customized chase car operator interface is illustrated.

This thesis investigates optimization of advanced telecommunication algorithms from power and performance perspectives. The algorithms chosen are MIMO and LDPC. MIMO is implemented in custom ASIC for power optimization and LDPC is implemented on dynamically reconfigurable fabric for both power and performance optimization. Both MIMO and LDPC are considered computational bottlenecks of current and future wireless standards such as IEEE 802.11n for Wi-Fi and IEEE 802.16 for WiMax applications. Optimization of these algorithms is carried out separately. The thesis is organized implicitly in two parts. The first part presents selection and analysis of the VBLAST receiver used in MIMO wireless system from custom ASIC perspective and identifies those processing elements that consume larger area as well as power due to complex signal processing. The thesis models a scalable VBLAST architecture based on MMSE nulling criteria assuming block rayleigh flat fading channel. After identifying the major area and power consuming blocks, it proposes low power and area efficient VLSI architectures for the three building blocks of VBLAST namely Pseudo Inverse, Sorting and NULLing & Cancellation modules assuming a 4x4 MIMO system. The thesis applies dynamic power management, algebraic transformation (strength reduction), resource sharing, clock gating, algorithmic modification, operation substitution, redundant arithmetic and bus encoding as the low power techniques applied at different levels of design abstraction ranging from system to architecture, to reduce power consumption. It also presents novel architectures not only for the constituent blocks but also for the whole receiver. It builds the low power VBLAST receiver for single carrier and provides its area, power and performance figures. It then investigates into the practicality and feasibility of VBLAST into an OFDM environment. It provides estimated data with respect to silicon real estate and throughput from which conclusion can easily be drawn about the feasibility of VBLAST in a multi carrier environment. The second part of the thesis presents novel architectures for the real time adaptive LDPC encoder and decoder as specified in IEEE 802.16E standard for WiMax application. It also presents optimizations of encoder as well as decoder on RICA (Reconfigurable Instruction Cell Architecture). It has searched an optimized way of storing the H matrices that reduces the memory by 20 times. It uses Loop unrolling to distribute the instructions spatially depending upon the available resources to execute them concurrently to as much as possible. The parallel memory banks and distributed registers inside RICA allow good reduction in memory access time. This together with hardware pipelining provides substantial potential for optimizing algorithms from power and performance perspectives. The thesis also suggests ways of improvements inside RICA architecture.

Master of Science / Department of Electrical and Computer Engineering / Dwight D. Day / Low-power systems implemented on Field Programmable Gate Arrays (FPGA) have become more practical with advancements leading to decreases in FPGA power consumption, physical size, and cost. In systems that may need to operate for an extended time independent of a central power source, low-power FPGA’s are now a reasonable option. Combined with research into energy harvesting solutions, a FPGA-based system could operate independently indefinitely and be cost effective. Four simple demodulator designs were implemented on a FPGA to test and compare the performance and power consumption of each. The demodulators were a Counter that tracked the length of the input signal period, a One-Shot that counted the input edges over time, a Phase-Frequency Detector (PFD), and a PFD with preprocessing on the input signal to mitigate distortion introduces by the 1-bit subsampling. The designs demodulated a binary frequency shift keying (BFSK) signal using 10.69MHz and 10.71MHz as the input frequencies and a 1kHz data rate. The signal was 1-bit subsampled at 75kHz to provide the demodulators with a signal containing 15kHz and 35kHz. The design size, power consumption, and error performance of each demodulator were compared. At the frequencies and data rate used, the Counter and One-Shot are the most energy efficient by a significant margin over the PFDs. The error performance was nearly equal for all four. As the BFSK baseband frequencies and especially the data rate are increased, the PFD options are expected to be the better options as the Counter and One-Shot may not react quickly enough.

Pervasive Service Discovery (SD) in Low-power and Lossy Networks (LLNs) is expected to play a major role in realising the Internet of Things (IoT) vision. Such a vision aims to expand the current Internet to interconnect billions of miniature smart objects that sense and act on our surroundings in a way that will revolutionise the future. The pervasiveness and heterogeneity of such low-power devices requires robust, automatic, interoperable and scalable deployment and operability solutions. At the same time, the limitations of such constrained devices impose strict challenges regarding complexity, energy consumption, time-efficiency and mobility. This research contributes new lightweight solutions to facilitate automatic deployment and operability of LLNs. It mainly tackles the aforementioned challenges through the proposition of novel component-based, automatic and efficient SD solutions that ensure extensibility and adaptability to various LLN environments. Building upon such architecture, a first fully-distributed, hybrid pushpull SD solution dubbed EADP (Extensible Adaptable Discovery Protocol) is proposed based on the well-known Trickle algorithm. Motivated by EADPs’ achievements, new methods to optimise Trickle are introduced. Such methods allow Trickle to encompass a wide range of algorithms and extend its usage to new application domains. One of the new applications is concretized in the TrickleSD protocol aiming to build automatic, reliable, scalable, and time-efficient SD. To optimise the energy efficiency of TrickleSD, two mechanisms improving broadcast communication in LLNs are proposed. Finally, interoperable standards-based SD in the IoT is demonstrated, and methods combining zero-configuration operations with infrastructure-based solutions are proposed. Experimental evaluations of the above contributions reveal that it is possible to achieve automatic, cost-effective, time-efficient, lightweight, and interoperable SD in LLNs. These achievements open novel perspectives for zero-configuration capabilities in the IoT and promise to bring the ‘things’ to all people everywhere.

Virtually every industry and discipline (e.g., mining, pharmaceutical, construction, agriculture, reclamation, etc.) is finding applications for wireless data acquisition for monitoring and managing processes and resources. Two sectors, namely agriculture and environmental research, are seeking ways to obtain distributed soil and plant measurements over larger areas like a watershed or large fields rather than a single site of intensive instrumentation (i.e., a weather station). Wireless sensor networks and remote sensing have been explored as a means to satisfy this need. Commercial products are readily available that have remote wireless options to support distributed senor networking. However, these systems have been designed with a field engineer or technician as the target end-user. Equipment and operating costs, device specific programming languages, and complex wireless configuration schemes have impeded the adoption of large-scale, multi-node wireless systems in these fields. This report details the development of an easy-to-use, ultra-low power wireless datalogger incorporating a scalable, intelligent data collection and transmission topology. The final product can interface to various sensor types including SDI-12 and uses an LCD display to help simplify device setup.

With the portable computing devices and wireless communication systems are popularly used, the power consumption became one of the major targets of VLSI design. However, multiplier is always a fundamental component and influences the power consumption and performance much in many DSP and multimedia applications. Therefore, multiplier is the crucial design and need to be concerned at first. In these systems, the data width of input data is various because the different applications are operated in the same system. According to this characteristic of input data, this paper presents architecture of reconfigurable multiplier without the necessity to completely reconfigure the internal layout of a programmable device. The multiplier employs the Booth algorithm which reduces the partial products to half to implement the sign multiplication. In order to reduce power consumption, the proposed multiplier introduces the clock gating technique to disable the circuit which does not need to be computed. Moreover, the energy-efficient multiplier presented in this thesis can perform multiplication with different data widths to further decrease power dissipation and enhance performance. In this work, we proposed two versions of multipliers. The first version is reconfigurable pipelined Booth multiplier, which can perform one n by n multiplication or two n/2 by n/2 multiplications concurrently. When the multiplier performs n-bit multiplication, it can reduce power consumption by disabling the unnecessary blocks according to the input data. The second version further deploys the truncated functionality to provide different way to make multiplication more energy-efficient. Experiment shows that the proposed multipliers can perform multiplication with less energy and lower power dissipation. It is certain that the more functions the design provides, the more area it will cost.

Quadrature digital modulation techniques are widely used in modern communication systems because of their high performance and flexibility. However, these advantages come at the cost of high power consumption. As a result, power consumption has to be taken into account as a main design factor of the modulator.<p>In this thesis, a low-power quadrature digital modulator in 0.18um CMOS is presented with the target system clock speed of 150 MHz. The quadrature digital modulator consists of several key blocks: quadrature direct digital synthesizer (QDDS), pulse shaping filter, interpolation filter and inverse sinc filter. The design strategy is to investigate different implementations for each block and compare the power consumption of these implementations. Based on the comparison results, the implementation that consumes the lowest power will be chosen for each block. First of all, a novel low-power QDDS is proposed in the thesis. Power consumption estimation shows that it can save up to 60% of the power consumption at 150 MHz system clock frequency compared with one conventional design. Power consumption estimation results also show that using two pulse shaping blocks to process I/Q data, cascaded integrator comb (CIC) interpolation structure, and inverse sinc filter with modified canonic signed digit (MCSD) multiplication consume less power than alternative design choices. These low-power blocks are integrated together to achieve a low-power modulator. The power consumption estimation after layout shows that it only consumes about 95 mW at 150 MHz system clock rate, which is much lower than similar commercial products. <p>The designed modulator can provide a low-power solution for various quadrature modulators. It also has an output bandwidth from 0 to 75 MHz, configurable pulse shaping filters and interpolation filters, and an internal sin(x)/x correction filter.

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Quadrature digital modulation techniques are widely used in modern communication systems because of their high performance and flexibility. However, these advantages come at the cost of high power consumption. As a result, power consumption has to be taken into account as a main design factor of the modulator.<p>In this thesis, a low-power quadrature digital modulator in 0.18um CMOS is presented with the target system clock speed of 150 MHz. The quadrature digital modulator consists of several key blocks: quadrature direct digital synthesizer (QDDS), pulse shaping filter, interpolation filter and inverse sinc filter. The design strategy is to investigate different implementations for each block and compare the power consumption of these implementations. Based on the comparison results, the implementation that consumes the lowest power will be chosen for each block. First of all, a novel low-power QDDS is proposed in the thesis. Power consumption estimation shows that it can save up to 60% of the power consumption at 150 MHz system clock frequency compared with one conventional design. Power consumption estimation results also show that using two pulse shaping blocks to process I/Q data, cascaded integrator comb (CIC) interpolation structure, and inverse sinc filter with modified canonic signed digit (MCSD) multiplication consume less power than alternative design choices. These low-power blocks are integrated together to achieve a low-power modulator. The power consumption estimation after layout shows that it only consumes about 95 mW at 150 MHz system clock rate, which is much lower than similar commercial products. <p>The designed modulator can provide a low-power solution for various quadrature modulators. It also has an output bandwidth from 0 to 75 MHz, configurable pulse shaping filters and interpolation filters, and an internal sin(x)/x correction filter.

In nanometer technologies, process variation control and low power have emerged as the first order design goal after high performance. Process variations cause high variability in performance and power consumption of an IC, which affects the overall yield. Short channel effects (SCEs) deteriorate the MOSFET performance and lead to higher leakage power. Double gate devices suppress SCEs and are potential candidates for replacing Bulk technology in nanometer nodes. Threshold voltage control in planar asymmetric double gate transistor (IGFET) using a fourth terminal provides an effective means of combating process variations and low power design. In this thesis, using various case studies, we analyzed the suitability of IGFET for variation control and low power design. We also performed an extensive comparison between IGFET and Bulk for reducing variability, improving yield and leakage power reduction using power gating. We also proposed a new circuit topology for IGFET, which on average shows 33.8 percent lower leakage and 34.9 percent lower area at the cost of 2.8 percent increase in total active mode power, for basic logic gates. Finally, we showed a technique for reducing leakage of minimum sized devices designed using new circuit topology for IGFET.