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No description available.

Power consumption is a critical design issue in embedded processors. As part of our low power processor design project, this thesis work aims to reduce power consumption on two typical processor components: Register File (RF), and Arithmetic and Logic Unit (ALU). Register File is one of the most power hungry components in the processor, consuming about 20% of the processor power. The ALU is the working horse in the processor, responsible for almost all basic computing operations. Although ALU does not consume as high power as the register file, we observe that it can be power intensive in terms of power dissipation per silicon area unit and may result in a thermal hot spot in the processor. Existing approaches to reduce power on the register file and ALU are effective. However, most of them either entail extensive hardware design efforts, or require a significant amount of work on post-compilation software code modification. The approaches proposed in this thesis avoid such problems. We only customize the internal structure of the processor components and keep the components’ interface to other system parts intact, so that the customization to a component is transparent to its external hardware design and no modification/alteration to other hardware components or to the software code is required. This customization strategy is well suitable to our whole low power processor design project and can be applied to any customization of an existing system for a given application. We have applied our customization approaches to a set of benchmarks in a variety of application domains. Our experimental results show that the power savings on register file are in a range from 18.8% to 45.5%, an average of 29.7% register file power can be saved. For the arithmetic and logic unit, the power savings are from 43.5% to 49.6% and the average saving is 46.9% as compared to the original designs. We also combine the customization of both the ALU and the register file. With the customizing of the ALU and the register file simultaneously, the processor power consumption can be reduced from 3.9% to 10.1%; on average, 6.44% processor power can be saved. Most importantly, the power saving achievement is at the cost of neither hardware complexity nor processor performance, and the implementation is extremely straightforward and can be easily incorporated into a processor design environment, such as ASIPMeister (a design tool, to automatically generate a VHDL model for application specificinstruction set processors) used in our research.

With the emergence of portable computing and communication systems, power consumption has become one of the major objectives during VLSI design. Furthermore, multipliers are always fundamental building blocks and the bottleneck in terms of power consumption in many DSP and multimedia applications. Therefore, it is crucial to minimize the power consumption of multipliers in the system for low-power VLSI design. Besides, energy-efficient multiplier is greatly desirable for DSP systems and computer architectures. In many of these systems, the dynamic-range of input operands for multiplier is usually very small. In addition, the least significant bits of output products are often rounded or truncated to avoid growth in word size. Based on these features, this thesis presents an approach to design low-power and reconfigurable signed pipelined multipliers. The approach dynamically detects input range of the multiplier and disables the switching operations of non-effective ranges to decrease the power consumption. Moreover, the proposed approach can reconfigure the output precision of the multiplier to save power consumption. We apply this approach to two architectures: array-based and Booth-based architecture. Experimental results show that the proposed array-based pipelined multiplier leads to up 47% power saving and Booth-based multiplier leads to up 30% power saving with a little additional area and delay overheads. Besides, in order to accord with the low cost and high profit-making goal of systematic products and shorten construction period, we have designed a low-power multiplier generator. User could use the user interface to configure the multiplier size, low power architecture and the precision that user need. The generator will create the hardware architecture of low-power multiplier automatically.

With shrinking feature size and growing integration density in the Deep Sub- Micron (DSM) technologies, the global buses are fast becoming the "weakest-links" in VLSI design. They have large delays and are error-prone. Especially, in system-onchip (SoC) designs, where parallel interconnects run over large distances, they pose difficult research and design problems. This work presents an approach for evaluating the data carrying capacity of such wires. The method treats the delay and reliability in interconnects from an information theoretic perspective. The results point to an optimal frequency of operation for a given bus dimension for maximum data transfer rate. Moreover, this optimal frequency is higher than that achieved by present day designs which accommodate the worst case delays. This work also proposes several novel ways to approach this optimal data transfer rate in practical designs.From the analysis of signal propagation delay in long wires, it is seen that the signal delay distribution has a long tail, meaning that most signals arrive at the output much faster than the worst case delay. Using communication theory, these "good" signals arriving early can be used to predict/correct the "few" signals that arrive late. In addition to this correction based on prediction, the approaches use coding techniques to eliminate high delay cases to generate a higher transmission rate. The work also extends communication theoretic approaches to other areas of VLSI design. Parity groups are generated based on low output delay correlation to add redundancy in combinatorial circuits. This redundancy is used to increase the frequency of operation and/or reduce the energy consumption while improving the overall reliability of the circuit.

In this thesis, a low-power current-mode instrumentation amplifier is proposed for the portable physiological signal recording system. This proposed instrumentation amplifier is used as a front-end amplifier of physiological signal recording system. In general, the physiological signal is very small, for example, the electrocardiogram (ECG) signals. Therefore, the system needs a front-end amplifier to amplify small physiological signals so that it is easier to analyze the signals. Besides, the system will be operated for a longer period because of the proposed amplifier¡¦s low-power property. The circuit theorem, design process and simulation, circuit layout as well as the measurement results all have detailed description in this study. Moreover, a specific physiological signal recording system prototype is proposed. This proposed instrumentation amplifier has used TSMC 0.35 £gm 2P4M CMOS process technology.

Power consumption is a critical design issue in embedded processors. As part of our low power processor design project, this thesis work aims to reduce power consumption on two typical processor components: Register File (RF), and Arithmetic and Logic Unit (ALU). Register File is one of the most power hungry components in the processor, consuming about 20% of the processor power. The ALU is the working horse in the processor, responsible for almost all basic computing operations. Although ALU does not consume as high power as the register file, we observe that it can be power intensive in terms of power dissipation per silicon area unit and may result in a thermal hot spot in the processor. Existing approaches to reduce power on the register file and ALU are effective. However, most of them either entail extensive hardware design efforts, or require a significant amount of work on post-compilation software code modification. The approaches proposed in this thesis avoid such problems. We only customize the internal structure of the processor components and keep the components’ interface to other system parts intact, so that the customization to a component is transparent to its external hardware design and no modification/alteration to other hardware components or to the software code is required. This customization strategy is well suitable to our whole low power processor design project and can be applied to any customization of an existing system for a given application. We have applied our customization approaches to a set of benchmarks in a variety of application domains. Our experimental results show that the power savings on register file are in a range from 18.8% to 45.5%, an average of 29.7% register file power can be saved. For the arithmetic and logic unit, the power savings are from 43.5% to 49.6% and the average saving is 46.9% as compared to the original designs. We also combine the customization of both the ALU and the register file. With the customizing of the ALU and the register file simultaneously, the processor power consumption can be reduced from 3.9% to 10.1%; on average, 6.44% processor power can be saved. Most importantly, the power saving achievement is at the cost of neither hardware complexity nor processor performance, and the implementation is extremely straightforward and can be easily incorporated into a processor design environment, such as ASIPMeister (a design tool, to automatically generate a VHDL model for application specificinstruction set processors) used in our research.

Since the introduction of Complementary-Metal-Oxide-Semiconductor (CMOS) technology, the chip industry has enjoyed many benefits of transistor feature size scaling, including higher speed and device density and improved energy efficiency. However, in the recent years, the IC designers have encountered a few roadblocks, namely reaching the physical limits of scaling and also increased device leakage which has resulted in a slow-down of supply voltage and power density scaling. Therefore, there has been an extensive hunt for alternative circuit architectures and switching devices that can alleviate or eliminate the current crisis in the semiconductor industry. The Nano-Electro-Mechanical (NEM) relay is a promising alternative switch that offers zero leakage and abrupt turn-on behaviour. Even though these devices are intrinsically slower than CMOS transistors, new circuit design techniques tailored for the electromechanical properties of such devices can be leveraged to design medium performance, ultra-low power integrated circuits. In this thesis, we deal with a new generation of such devices that is built in the back end of line (BEOL) CMOS process and is an ideal option for full integration with current CMOS transistor technology. Simulation and verification at the circuit and system level is a critical step in the design flow of microelectronic circuits, and this is especially important for new technologies that lack the standard design infrastructure and well-known verification platforms. Although most of the physical and electrical properties of NEM structures can be simulated using standard electronic automation software, there is no report of a reliable behavioural model for NEMS switches that enable large circuit simulations. In this work, we present an optimised model of a BEOL nano relay that encompasses all the electromechanical characteristics of the device and is robust and lightweight enough for VLSI applications that require simulation of thousands of devices. To verify the performance of the proposed model, complex logic circuits built exclusively with relays, and also, hybrid CMOS-NEM circuits are simulated and verified. Finally, these novel topologies are reviewed and discussed as low-power alternatives to current CMOS topologies.

No description available.

Ultra-Wideband (UWB) technologies are at the forefront of wireless communications, offering the possibility to provide extremely high data rate wireless solutions. In addition to high data rate applications, UWB technologies also offer an extremely low cost alternative for many low data rate systems. In this thesis, we describe the design of a CMOS pulse generator for impulse based UWB systems. The structure of our pulse generator is based on the topology of a single tap CMOS power amplifier. By increasing the number of taps on a CMOS power amplifier, it is possible to generate sub-nanosecond pulses with a desired shape. A power saving scheme that significantly reduces the power consumed at low data rates is also described. The versatility of our design lies in the ability to support dynamically varying output power levels and center frequencies. Our pulse generator design is extended to a rectified cosine generator, necessary for a multiband approach. The performance of our pulse generators is estimated through simulation with a target technology of TSMC 0.18 µm CMOS at a supply voltage of 1.8 V. The simulation results indicate that our pulse generator produces high fidelity Gaussian monocycle pulses with a pulse width of approximately 160 ps and a peak output power of more than 10 mW. We believe that our design of a CMOS pulse generator for UWB systems is a feasible option for many applications in which power and cost are most important. / Master of Science