No description available.

No regime em nanoescala da tecnologia VLSI, o desempenho dos circuitos é cada vez mais afetado pelos fenômenos de variabilidade, tais como variações de parâmetros de processo, ruído da fonte de alimentação, ruído de acoplamento e mudanças de temperatura, entre outros. Variações de fabricação podem levar a diferenças significativas entre circuitos integrados concebidos e fabricados. Devido à diminuição das dimensões dos componentes, o impacto das variações de dimensão crítica tende a aumentar a cada nova tecnologia, uma vez que as tolerâncias de processo não sofrem escalonamento na mesma proporção. Muitos estudos sobre a forma como a variabilidade intrínseca dos processos físicos afeta a funcionalidade e confiabilidade dos circuitos têm sido realizados nos últimos anos. Uma vez que as variações de processo se tornam um problema mais significativo devido à agressiva redução da tecnologia, uma mudança da análise determinística para a análise estatística de projetos de circuitos pode reduzir o conservadorismo e o risco que está presente ao se aplicar a técnica tradicional. O objetivo deste trabalho é propor um método capaz de predizer a variabilidade no atraso de redes de transistores e portas lógicas sem a necessidade da realização de simulações estatísticas consideradas caras em termos computacionais. Este método utiliza o modelo de atraso de Elmore e a técnica de Asymptotic Waveform Evaluation (AWE), considerando as resistências dos transistores obtidas em função das variações das tensões de limiar dos transistores no arranjo. Uma pré-caracterização foi realizada em algumas portas lógicas de acordo com a variabilidade de seu desempenho causados por variações da tensão de limiar dos transistores a partir de simulações Monte Carlo. Uma vez que existem vários tipos de arranjos de redes de transistores e esses arranjos apresentam um comportamento diferente em termos de atraso, consumo de energia, área e variabilidade dessas métricas, torna-se muito útil identificar os circuitos nos quais as redes de transistores são menos influenciadas pelas variações em seus parâmetros. O modelamento da variabilidade do atraso é feita através de 2K simulações DC para a rede “pull-up”, 2N simulações DC para a rede “pull-down” (K e N são os números de transistores de cada rede) e uma simulação transiente para cada porta lógica, o que leva apenas alguns segundos no total. O objetivo de toda a análise é fornecer orientações para a geração de redes lógica ótimas que oferecem baixa sensibilidade às variações de seus parâmetros. / In the nanoscale regime of VLSI technology, circuit performance is increasingly affected by variational effects such as process variations, power supply noise, coupling noise and temperature changes. Manufacturing variations may lead to significant discrepancies between designed and fabricated integrated circuits. Due to the shrinking of design dimensions, the relative impact of critical dimension variations tends to increase with each new technology generation, since the process tolerances do not scale in the same proportion. Many studies on how the intrinsic variability of physical processes affect the functionality and reliability of the circuits have been done in recent years. Since the process variations become a more significant problem because of the aggressive technology scaling, a shift from deterministic to statistical analysis for circuit designs may reduce the conservatism and risk that is present while applying the traditional technique. The purpose of the work is to propose a method that accounts for the deviation in the performance of transistors networks and logic gates without the need of performing computationally costly simulations. The estimation method developed uses the Elmore Delay model and the Asymptotic Waveform Evaluation (AWE), by considering the resistances of transistors obtained as functions of threshold voltages variations of the transistors in the arrangement. A pre-characterization was performed in some logic gates according to their performance variability caused by variations in the threshold voltage of the transistors by running Monte Carlo simulations. Since there are several kinds of transistor networks arrangements and they present different behavior in terms of delay, power consumption, area and variability of these metrics, it is very useful to identify circuits with such arrangements of transistors that are less influenced by variations in their parameters. The delay variability modeling relies on (2K) DC simulations for the pull-up network, (2N) DC simulations for the pull-down network (K and N are the number of transistors in the pull-up and pull-down network, respectively) and on a single transient simulation for each gate, which take only a few seconds altogether. The goal of the whole analysis is to provide guidelines for the generation of optimal logic networks that present low sensitivity to variations in their parameters.

No regime em nanoescala da tecnologia VLSI, o desempenho dos circuitos é cada vez mais afetado pelos fenômenos de variabilidade, tais como variações de parâmetros de processo, ruído da fonte de alimentação, ruído de acoplamento e mudanças de temperatura, entre outros. Variações de fabricação podem levar a diferenças significativas entre circuitos integrados concebidos e fabricados. Devido à diminuição das dimensões dos componentes, o impacto das variações de dimensão crítica tende a aumentar a cada nova tecnologia, uma vez que as tolerâncias de processo não sofrem escalonamento na mesma proporção. Muitos estudos sobre a forma como a variabilidade intrínseca dos processos físicos afeta a funcionalidade e confiabilidade dos circuitos têm sido realizados nos últimos anos. Uma vez que as variações de processo se tornam um problema mais significativo devido à agressiva redução da tecnologia, uma mudança da análise determinística para a análise estatística de projetos de circuitos pode reduzir o conservadorismo e o risco que está presente ao se aplicar a técnica tradicional. O objetivo deste trabalho é propor um método capaz de predizer a variabilidade no atraso de redes de transistores e portas lógicas sem a necessidade da realização de simulações estatísticas consideradas caras em termos computacionais. Este método utiliza o modelo de atraso de Elmore e a técnica de Asymptotic Waveform Evaluation (AWE), considerando as resistências dos transistores obtidas em função das variações das tensões de limiar dos transistores no arranjo. Uma pré-caracterização foi realizada em algumas portas lógicas de acordo com a variabilidade de seu desempenho causados por variações da tensão de limiar dos transistores a partir de simulações Monte Carlo. Uma vez que existem vários tipos de arranjos de redes de transistores e esses arranjos apresentam um comportamento diferente em termos de atraso, consumo de energia, área e variabilidade dessas métricas, torna-se muito útil identificar os circuitos nos quais as redes de transistores são menos influenciadas pelas variações em seus parâmetros. O modelamento da variabilidade do atraso é feita através de 2K simulações DC para a rede “pull-up”, 2N simulações DC para a rede “pull-down” (K e N são os números de transistores de cada rede) e uma simulação transiente para cada porta lógica, o que leva apenas alguns segundos no total. O objetivo de toda a análise é fornecer orientações para a geração de redes lógica ótimas que oferecem baixa sensibilidade às variações de seus parâmetros. / In the nanoscale regime of VLSI technology, circuit performance is increasingly affected by variational effects such as process variations, power supply noise, coupling noise and temperature changes. Manufacturing variations may lead to significant discrepancies between designed and fabricated integrated circuits. Due to the shrinking of design dimensions, the relative impact of critical dimension variations tends to increase with each new technology generation, since the process tolerances do not scale in the same proportion. Many studies on how the intrinsic variability of physical processes affect the functionality and reliability of the circuits have been done in recent years. Since the process variations become a more significant problem because of the aggressive technology scaling, a shift from deterministic to statistical analysis for circuit designs may reduce the conservatism and risk that is present while applying the traditional technique. The purpose of the work is to propose a method that accounts for the deviation in the performance of transistors networks and logic gates without the need of performing computationally costly simulations. The estimation method developed uses the Elmore Delay model and the Asymptotic Waveform Evaluation (AWE), by considering the resistances of transistors obtained as functions of threshold voltages variations of the transistors in the arrangement. A pre-characterization was performed in some logic gates according to their performance variability caused by variations in the threshold voltage of the transistors by running Monte Carlo simulations. Since there are several kinds of transistor networks arrangements and they present different behavior in terms of delay, power consumption, area and variability of these metrics, it is very useful to identify circuits with such arrangements of transistors that are less influenced by variations in their parameters. The delay variability modeling relies on (2K) DC simulations for the pull-up network, (2N) DC simulations for the pull-down network (K and N are the number of transistors in the pull-up and pull-down network, respectively) and on a single transient simulation for each gate, which take only a few seconds altogether. The goal of the whole analysis is to provide guidelines for the generation of optimal logic networks that present low sensitivity to variations in their parameters.

No regime em nanoescala da tecnologia VLSI, o desempenho dos circuitos é cada vez mais afetado pelos fenômenos de variabilidade, tais como variações de parâmetros de processo, ruído da fonte de alimentação, ruído de acoplamento e mudanças de temperatura, entre outros. Variações de fabricação podem levar a diferenças significativas entre circuitos integrados concebidos e fabricados. Devido à diminuição das dimensões dos componentes, o impacto das variações de dimensão crítica tende a aumentar a cada nova tecnologia, uma vez que as tolerâncias de processo não sofrem escalonamento na mesma proporção. Muitos estudos sobre a forma como a variabilidade intrínseca dos processos físicos afeta a funcionalidade e confiabilidade dos circuitos têm sido realizados nos últimos anos. Uma vez que as variações de processo se tornam um problema mais significativo devido à agressiva redução da tecnologia, uma mudança da análise determinística para a análise estatística de projetos de circuitos pode reduzir o conservadorismo e o risco que está presente ao se aplicar a técnica tradicional. O objetivo deste trabalho é propor um método capaz de predizer a variabilidade no atraso de redes de transistores e portas lógicas sem a necessidade da realização de simulações estatísticas consideradas caras em termos computacionais. Este método utiliza o modelo de atraso de Elmore e a técnica de Asymptotic Waveform Evaluation (AWE), considerando as resistências dos transistores obtidas em função das variações das tensões de limiar dos transistores no arranjo. Uma pré-caracterização foi realizada em algumas portas lógicas de acordo com a variabilidade de seu desempenho causados por variações da tensão de limiar dos transistores a partir de simulações Monte Carlo. Uma vez que existem vários tipos de arranjos de redes de transistores e esses arranjos apresentam um comportamento diferente em termos de atraso, consumo de energia, área e variabilidade dessas métricas, torna-se muito útil identificar os circuitos nos quais as redes de transistores são menos influenciadas pelas variações em seus parâmetros. O modelamento da variabilidade do atraso é feita através de 2K simulações DC para a rede “pull-up”, 2N simulações DC para a rede “pull-down” (K e N são os números de transistores de cada rede) e uma simulação transiente para cada porta lógica, o que leva apenas alguns segundos no total. O objetivo de toda a análise é fornecer orientações para a geração de redes lógica ótimas que oferecem baixa sensibilidade às variações de seus parâmetros. / In the nanoscale regime of VLSI technology, circuit performance is increasingly affected by variational effects such as process variations, power supply noise, coupling noise and temperature changes. Manufacturing variations may lead to significant discrepancies between designed and fabricated integrated circuits. Due to the shrinking of design dimensions, the relative impact of critical dimension variations tends to increase with each new technology generation, since the process tolerances do not scale in the same proportion. Many studies on how the intrinsic variability of physical processes affect the functionality and reliability of the circuits have been done in recent years. Since the process variations become a more significant problem because of the aggressive technology scaling, a shift from deterministic to statistical analysis for circuit designs may reduce the conservatism and risk that is present while applying the traditional technique. The purpose of the work is to propose a method that accounts for the deviation in the performance of transistors networks and logic gates without the need of performing computationally costly simulations. The estimation method developed uses the Elmore Delay model and the Asymptotic Waveform Evaluation (AWE), by considering the resistances of transistors obtained as functions of threshold voltages variations of the transistors in the arrangement. A pre-characterization was performed in some logic gates according to their performance variability caused by variations in the threshold voltage of the transistors by running Monte Carlo simulations. Since there are several kinds of transistor networks arrangements and they present different behavior in terms of delay, power consumption, area and variability of these metrics, it is very useful to identify circuits with such arrangements of transistors that are less influenced by variations in their parameters. The delay variability modeling relies on (2K) DC simulations for the pull-up network, (2N) DC simulations for the pull-down network (K and N are the number of transistors in the pull-up and pull-down network, respectively) and on a single transient simulation for each gate, which take only a few seconds altogether. The goal of the whole analysis is to provide guidelines for the generation of optimal logic networks that present low sensitivity to variations in their parameters.

Ce travail de thèse traite des différents phénomènes de dégradation que peuvent subir les transistors MOS suivant leurs applications sur les technologies CMOS avec mémoires non-volatiles embarquées. Les transistors MOS pour application aux mémoires non volatiles à stockage de charge qui sont enclins à des mécanismes de dégradation spécifiques liés à l’utilisation de la haute tension, ont été étudiés. De plus, des variations de procédés de fabrication ou d’architectures, peuvent avoir un impact sur les mécanismes de dégradation des transistors MOS. En effet, plusieurs modifications des étapes de fabrication peuvent être apportées dans le but d’améliorer les performances des MOSFETs. Le cas des transistors digitaux pour application faible consommation a été considéré ici avec comme objectif principal d’augmenter la mobilité des porteurs dans le canal des transistors MOS. Aussi, suite à certaines limites de l’architecture conventionnelle des transistors MOS, des études ont été menées sur les transistors analogiques et digitaux présentant de nouvelles architectures ayant pour but la suppression de l’effet « hump » ou la réduction de l’aire totale du transistor en déplaçant le contact de grille au-dessus de la zone active. / This thesis focuses on various degradation phenomena that can impact MOS transistors according to their applications on CMOS technologies with embedded non-volatile memories. The transistors used in order to apply potentials greater than 10V in programming and erasing steps of charge storage non-volatile memories have been studied. These transistors are impacted by specific degradation mechanisms due to the use of high voltage. Moreover, manufacturing processes can be modified in order to improve MOSFETs performances, and thus, these variations may have an impact on the degradation mechanisms of MOS transistors. Therefore, several process steps of digital transistor for low power application were changed in order to increase carrier mobility. Furthermore, due to limitations of MOS transistors conventional architecture, new architectures have been proposed for analog and digital transistors in order to remove the "hump" effect or reduce the total area of transistor by moving the gate contact over active area.

Le travail de recherche présenté dans ce manuscrit contribue à une étude générale de la susceptibilité électromagnétique (EM) d'un transistor MOS (Metal Oxide Semiconductor) dans une gamme de fréquences allant de 10 MHz à 1 GHz. Ce composant est destiné à un usage général pour des applications analogiques et numériques. Le but principal de ce travail est d'apporter une compréhension fine des mécanismes physiques mis en jeu au sein du composant lorsque ce dernier est soumis à une agression EM injectée en mode conduit au niveau de sa grille. Notre étude porte sur l'élaboration d'un modèle physique, essentiellement basé sur les variations de charges au sein du composant électronique. Cette approche permet à la fois de comprendre le fonctionnement nominal du transistor et la modification de son comportement lors d'un dysfonctionnement. En effet, la compréhension des mécanismes physiques mis en jeu est la base de la compréhension de la susceptibilité EM. Pour mettre en œuvre ce type d'approche, nous avons choisi d'étudier un type de susceptibilité correspondant à la modification de son point de fonctionnement sous agression EM. Cette modification du point de fonctionnement peut induire un dysfonctionnement du circuit dans lequel est implanté le transistor. Le phénomène physique à l'origine duquel les signaux parasites EM modifient le point de fonctionnement d'un composant électronique est le phénomène de redressement. Ce phénomène apparaît lorsqu'une distorsion est créée au sein du composant. C'est aussi pourquoi les non-linéarités du dispositif sont directement responsables de son observation. Ainsi, pour comprendre finement et physiquement l'effet induit par une agression EM, il est nécessaire de mettre en place une méthode d'étude. Celle-ci est basée sur une mesure des formes d'onde des courants à tous les accès du transistor. En effet, la visualisation de ces courants renseigne sur l'évolution des charges au sein de la structure. De plus, une telle mesure donne accès à une large palette d'observables (valeurs moyennes des courants, distorsions des courants, valeurs crêtes des courants, etc..). Dans un premier temps, les différentes mesures des formes d'onde des courants ont été réalisées lorsqu'une impulsion de tension était appliquée sur la grille du composant avec des temps de montée variables et choisis par rapport au temps de réponse du transistor. Cela nous a permis d'approfondir la compréhension du fonctionnement transitoire fort signal du MOSFET. Dans un second temps, nous avons mesuré les courants lors de l'application d'un signal EM à la grille du composant. En support à ces mesures nous avons utilisé deux outils de calcul : analytique et numérique. La méthode analytique permet la prédiction et l'identification des grandeurs du composant mises en jeu dans le mécanisme de la modification du comportement du transistor. La méthode numérique par simulation électrique permet, quant à elle, de prédire les effets de l'agression EM. Une étape de caractérisation statique et dynamique du composant a également été nécessaire pour enrichir la compréhension des phénomènes observés et fournir les entrées au modèle. / The research work presented here contributes to an overall study of the electromagnetic (EM) susceptibility of Metal Oxide Semiconductor Field Effect Transistors (MOSFET's), in a frequency range from 10 MHz to 1 GHz. This device is used for general purpose: analog and digital applications. The main aim of this study is to provide a detailed understanding of the physical mechanisms involved in the device when the Radio-Frequency (RF) interference is superimposed on the gate terminal. Our study focuses on the development of a physical model, based essentially on the charge variations within the electronic device. This approach allows to understand its behavior with and without the RF interference. Indeed, the knowledge of the involved physical mechanisms is the basic understanding of EM susceptibility. When RF interference is superimposed on the MOSFET terminals, various susceptibility effects take place depending on RF power level, frequency and the transistor operation region. Due to the nonlinearity of the MOS current-voltage characteristics, RF excitations cause distorted drain current waveform which leads to a bias point shift. This modification of the average drain current is called rectification effect. So we developed a method to clearly understand the effect induced by the EM interference. This method is based on the measurement of the currents waveforms to all of the transistor access. In fact, these currents waveforms measurements give us information on the charge variations within the electronic device. Moreover, such a measurement provides access to a wide range of current information (average values, distortion, peak values, etc.). Initially, the different currents waveforms measurements were made when a voltage ramp was applied to the device gate with variable rise time in respect to the transistor response time. This allowed us to understand the large signal transient response of the MOSFET. Secondly, we measured the currents waveforms when an EM interference was injected to the gate terminal. In support of these measurements we used two computation tools: analytical and numerical. The analytical method allows prediction and identification of the quantities of the device involved in the modification of transistor's behavior. The numerical method allows electrical simulation to predict the effects of EM aggression. A static and dynamic characterization of the component was also necessary to understand the observed phenomenon and provide data to the electrical model.

No description available.

L'étude de la fiabilité représente un enjeu majeur de la qualification des technologies de l'industrie de la microélectronique. Elle est traditionnellement étudiée en suivant la dégradation des paramètres des transistors au cours du temps, qui sert ensuite à construire des modèles physiques expliquant le vieillissement des transistors. Nous avons fait le choix dans ces travaux d'étudier la fiabilité des transistors à l'échelle microscopique, en nous intéressant aux mécanismes de ruptures de liaisons atomiques à l'origine de la création des défauts de l'oxyde de grille. Nous avons tout d'abord identifié la nature des défauts et modéliser leurs dynamiques de capture de charges afin de pouvoir reproduire leur impact sur des mesures électriques complexes. Cela nous a permis de développer une nouvelle méthodologie de localisation des défauts, le long de l'interface Si-SiO2, ainsi que dans le volume de l'oxyde. La mesure des dynamiques de créations de défauts pour des stress de type porteurs chauds et menant au claquage de l'oxyde de grille nous a permis de développer des modèles de dégradation de l'oxyde, prédisant les profils de défauts créés à l'interface et dans le volume de l'oxyde. Nous avons enfin établi un lien précis entre l'impact de la dégradation d'un transistor sur la perte de fonctionnalité d'un circuit représentatif du fonctionnement d'un produit digital.L'étude et la modélisation de la fiabilité à l'échelle microscopique permet d'avoir des modèles plus physiques, offrant ainsi une plus grande confiance dans les extrapolations de durées de vie des transistors et des produits. / Reliability study is a milestone of microelectronic industry technology qualification. It is usually studied by following the degradation of transistors parameters with time, used to build physical models explaining transistors aging. We decided in this work to study transistors reliability at a microscopic scale, by focusing on atomic-bond-breaking mechanisms, responsible of defects creation into the gate-oxide. First, we identified defects nature and modeled their charge capture dynamics in order to reproduce their impact on complex electrical measurements degradation. This has allowed us developing a new methodology of defects localization, along the Si/SiO2 interface, and in the volume of the gate-oxide. Defects creation dynamics measurement, for Hot Carrier stress and stress conditions leading to the gate-oxide breakdown, has allowed us developing gate-oxide degradation models, predicting generated defect profiles at the interface and into the volume of the gate-oxide. Finally, we established an accurate link between a transistor degradation impact on circuit functionality loss.Reliability study and modeling at a microscopic scale allows having more physical models, granting a better confidence in transistors and products lifetime extrapolation.

Cette thèse est une tentative vers la conception de la bande Ka émetteur-récepteur RF pour les réseaux de capteurs sans fil (WSN), pour lesquelles la consommation d'énergie, le coût et la taille sont des paramètres critiques. Au sens de la consommation d'énergie, un transmetteur RF est la partie la plus cruciale d'un nœud de capteur. Nous avons choisi STMicroelectronics 90nm global purpose (GP) pour atteindre la technologie CMOS à faible puissance, faible coût et de petite taille. Pour la première fois, nous avons introduit la bande Ka dans le context de WSN, a fin de bénéficier de l'immunité élevée du réseau et la petite taille antenne. Étant donné que la technologie que nous avons choisi et du kit associé fonderie de conception n'est pas pour la conception RF, nous avons été obligés de mettre au point un outil de conception individuelle pour la bande à ondes millimétriques. De cette façon, nous avons développé une solution simple et précise le modèle MOS transistor, comprenant charge et le modèle de capacité, modèle de bruit et le modèle complet des effets parasites. Nous avons proposé une nouvelle structure pour les inducteurs de la ligne de transmission et un modèle précis de RLGC a été développé pour la conception et la simulation de ces inducteurs. Et puis par la simulation de la pleine d'onde (full wave) électromagnétique dans le logiciel HFSS, nous avons extrait des parameters du modele d'incucteurs , et d'autres éléments passifs, telles que des pads RF et T-jonctions. Comme notre première expérience, nous avons conçu et optimisé une LNA à 30 GHz, en utilisant notre outil de conception. Le LNA conçu a été fabriqué dans STMicroelectronics 90nm global dans le processus de GP CMOS et a été mesurée dans le laboratoire IMEP. Les résultats des mesures montrent 10dB gain de puissance et de 4,8 dB figre bruit (noise figure) avec 4mW DC la consommation de puissance. Dans l'étape suivante, nous avons conçu et optimisé mieux 30GHz LNA. La simulation post-layout montre 13.9dB gain de puissance et 3.6d figre bruit, avec seulement 3 mW de consommation de puissance. Nous avons proposé un lien simple radio et un structure simple a ete presente pour le récepteur_émetteur. Dans le récepteur, nous avons utilisé la structure hétérodyne, ou dans la quelle nous avons utilise de l'idee de Mixer Harmonique paire et oscillateur couple, à surmonter de nombreux problèmes se pose en mm bande des ondes dans la technologie CMOS. Le Mixer a été conçu en utilisant les résultats d'analyse et de simulation dans le kit de conception de fonderie: 4dB gain de conversion et de 5,8 double side band figre de bruit avec 2.2Mw consommation de puissance, un excellent résultat en comparaison avec les œuvres similaires rapports comme IF Stage 2GHz qui a été conçu comme multi-slice-amplificateur de la chaîne de detection pour accroître (ugmenter)la performance du récepteur et d'atteindre plus faible consommation d'énergie. Enfin, le récepteur a été simulé dans MATLAB et--87dBm de sensibilité, 890KHz de bande passante, avec 6.65mW consommation d'énergie sont obtenus. L'émetteur a été conçu aussi simple que possible, en utilisant idée power oscillateur, délivrant 6mW puissance RF de l'antenne. L'émetteur a généralement les 25% de power efficacité qui est très bon résultat en comparaison avec les œuvres déclarées.

Les produits issus des technologies Silicium tendent à exploiter au maximum les performancesdes transistors MOS tout en les soumettant à des profils de mission très agressifs du point de vuede la fiabilité. Les concepteurs sont ainsi à la recherche du meilleur compromis entre performanceet fiabilité.Historiquement, l’étude de la fiabilité du transistor MOS et le développement des modèlessous jacents ont été menés sur la base de contrainte de vieillissement statique. Avec le développementdes produits à hautes performances dans le domaine de la radiofréquence (RF), laquestion de la fiabilité pour ce type d’application se pose. Ainsi, une extension des modèles defiabilité doit être réalisée afin de quantifier le vieillissement des paramètres clés RF soumis àdes contraintes statiques mais également RF. C’est cette extension de la fiabilité des transistorsMOS dans le domaine RF qui constitue le sujet de ce travail de thèse.Dans ce manuscrit, le fonctionnement du transistor MOS est décrit et sa fiabilité est introduite.Les différents mécanismes de dégradation sont étudiés et leurs modèles associés décrits.Sont ensuite présentés un banc de mesure et une méthodologie nécessaire à l’étude du vieillissementdes transistors dans le domaine RF, ainsi qu’à l’extension des modèles de fiabilité audomaine RF. / Products using nowadays silicon technology are generally targeting aggressive specificationsand push the developers to determine the best compromise between performance and reliability.Main front-end degradation mechanisms are historically studied and modeled under static stressconditions and focus on the static MOS transistor parameters.With the development of product targeting high performances in the radio frequency (RF)domain, the reliability is becoming a first order concern. Thus an extension of the actual staticreliability models must be done to quantify the aging of key RF parameters under static andRF stress. In this context, this work focuses on the extension of the MOS transistor reliabilityregarding the study of RF parameters and also the application of RF stress.After describing the MOS transistor properties, the reliability aspect is introduced and theemphasis is put on the different degradation mechanisms and their associated models. Thisallows the development of an experimental setup and the required methodology to investigatethe device aging in the RF domain and to extend actual static models.