Neuromorphic engineering is the research field dedicated to the study and design of brain-inspired hardware and software tools. Recent advances in emerging nanoelectronics promote the implementation of synaptic connections based on memristive devices. Their non-volatile modifiable conductance was shown to exhibit the synaptic properties often used in connecting and training neural layers. With their nanoscale size and non-volatile memory property, they promise a next step in designing more area and energy efficient neuromorphic hardware. My research deals with the challenges of harnessing memristive device properties that go beyond the behaviors utilized for synaptic weight storage. Based on devices that exhibit non-linear state changes and volatility, I present novel architectures and algorithms that can harness such features for computation. The crossbar architecture is a dense array of memristive devices placed in-between horizontal and vertical nanowires. The regularity of this structure does not inherently provide the means for nonlinear computation of applied input signals. Introducing a modulation scheme that relies on nonlinear memristive device properties, heterogeneous state patterns of applied spatiotemporal input data can be created within the crossbar. In this setup, the untrained and dynamically changing states of the memristive devices offer a useful platform for information processing. Based on the MNIST data set I'll demonstrate how the temporal aspect of memristive state volatility can be utilized to reduce system size and training complexity for high dimensional input data. With 3 times less neurons and 15 times less synapses to train as compared to other memristor-based implementations, I achieve comparable classification rates of up to 93%. Exploiting dynamic state changes rather than precisely tuned stable states, this approach can tolerate device variation up to 6 times higher than reported levels. Random assemblies of memristive networks are analyzed as a substrate for intrinsic computation in connection with reservoir computing; a computational framework that harnesses observations of inherent dynamics within complex networks. Architectural and device level considerations lead to new levels of task complexity, which random memristive networks are now able to solve. A hierarchical design composed of independent random networks benefits from a diverse set of topologies and achieves prediction errors (NRMSE) on the time-series prediction task NARMA-10 as low as 0.15 as compared to 0.35 for an echo state network. Physically plausible network modeling is performed to investigate the relationship between network dynamics and energy consumption. Generally, increased network activity comes at the cost of exponentially increasing energy consumption due to nonlinear voltage-current characteristics of memristive devices. A trade-off, that allows linear scaling of energy consumption, is provided by the hierarchical approach. Rather than designing individual memristive networks with high switching activity, a collection of less dynamic, but independent networks can provide more diverse network activity per unit of energy. My research extends the possibilities of including emerging nanoelectronics into neuromorphic hardware. It establishes memristive devices beyond storage and motivates future research to further embrace memristive device properties that can be linked to different synaptic functions. Pursuing to exploit the functional diversity of memristive devices will lead to novel architectures and algorithms that study rather than dictate the behavior of such devices, with the benefit of creating robust and efficient neuromorphic hardware.

Zinc oxide (ZnO) is perhaps one of the most widely studied material in the last two decades. It has received so much of attention because of its incredible potential for wide ranging applications. ZnO is a wide band gap semiconductor (Eg = 3.37 eV at 300 K) with a rather large excitonic binding energy (~60 meV). This combination of properties makes it an ideal choice for several optoelectronic devices that can easily work at room temperature. ZnO is a truly multifunctional material possessing several desirable electrical, optical, optoelectronic, and piezoelectric properties. In addition, it is highly amenable to production of various kinds of nanostructures such as nanorods, nanotubes, nanoribbons, nanoneedles, etc., which makes it even more desirable for nanoscale devices. Examples of ZnO based nanodevices could include photodiodes, photodetectors, nano-lasers, field-emission devices and memristors. In order to make such devices, one could need device quality nanostructures that must be reproducible and cost effective. Naturally, one has to look for a synthesis process that has great controls and is relatively inexpensive. The study provided here shows that among the various methods available for ZnO synthesis, the microwave-assisted chemical synthesis offers outstanding advantages in terms of rapid growth of nanostructures, economical use of energy and excellent controls of process parameters. In order to produce device quality ZnO nanostructures using microwave-assisted synthesis, one has to study the effect of various process parameters and optimise them for the desired growth. Therefore, in the current study, first, a systematic study was undertaken to synthesize ZnO nanostructures both in a aqueous and non-aqueous medium and their characterization was carried out in order to understand the effect of microwave power, time of irradiation, pressure, solvent and salt concentration, etc. The goal was to develop synthesis protocols for various kinds of nanostructures that could guarantee reproducibility, good yield, and device quality structures. This study has led to successful growth of ZnO nanostructures on various substrates, vertically aligned ZnO nanorods and templated arrays of desired structures, all with outstanding properties of the structures as confirmed by XRD, MicroRaman, photoluminescence, cathodoluminescence, FESEM, TEM, PFM studies and pole figure analysis. Piezoelectric force microscopy (PFM) and physical property measurement system (PPMS, Quantum Design), have been used to study the multifunctional properties of ZnO nanostructures. The PFM is a powerful technique to measure the local piezoelectric coefficient of nanostructures and nanoscale thin films. PFM works on the converse piezoelectric effect in which electric potential is applied and mechanical strain is measured using a cantilever deflection. The PFM (Brucker’s AFM dimension Scan Assist) was used to characterize individual ZnO nanorods. Extensive studies were carried out with PFM measurements and it was observed that the nanorods consistently showed high piezoelectric coupling coefficients (d33~50-154 pm/V). It was also found that the variation in d33 depended on morphology and size of nanostructure. The multifunctional properties were observed in small ZnO nanocrystals (NCs). Such high values of piezoelectric coupling coefficients open the door for novel ZnO based nanoscale sensors and actuators. The synthesized ZnO nanostructures were further optimized and characterized keeping in view three device applications namely Field emission, Memristors and Gas Sensors. The fabrication and characterization of these three devices with ZnO nanostructure was carried out using electron beam lithography and direct laser writing micromachining. Device fabrication using lithography involved several steps such as substrate cleaning, photoresist spin coating, pre-baking, post-baking, pattern writing, developing, sputtering/deposition of material for lift-off, ZnO growth, and overlay lithography. For field emission devices, high quality, well aligned, c-axis oriented ZnO nano-needles were grown on sputter coated Ti/Pt (20nm/100nm) on SiO2/Si substrate by rapid microwave-assisted method in aqueous medium. The diameter of the tip was found to be 1~2 nm and the length of the rod was approximately 3~5μm. For a particular batch the tip size, morphology, and lengths were found to be the same and highly repeatable. Pole figure analysis revealed that nanorods were highly oriented towards <002> direction. Field-emission measurements using the ZnO nanoneedles arrays as cathode showed very low turn-on electric field of 0.9 V/μm and a very high field enhancement factor ~ 20200. Such a high emission current density, low turn-on electric field, and high field enhancement factor are attributed to the high aspect ratio, narrow tip size, high quality and single crystallinity of the nanoneedles. The high emission current density, high stability, low threshold electric field (0.95 V/μm) and low turn-on field make the ZnO nanoneedle arrays one of the ideal candidates for field-emission displays and field emission sensors. In the suitability of ZnO nanostructures for memristor application it was found that the single crystalline ZnO nanorods were not suitable as they did not show memristive behaviour but the ZnO nanorods with native defects exhibited considerable memristive behaviour. Therefore the microwave-assisted grown ZnO nanorods with defects were used to fabricate memristive devices. Single and multiple ZnO nanorods based memristors were fabricated using electron beam lithography. These devices were characterized electrically by measuring the hysteresis in the I/V characteristics. A high degree of repeatability has been established in terms of growth, device fabrication, and measurements. The switching in single nanorod based devices was found to have “ON-to- OFF” resistance ratio of approximately 104 and current switching ratio (ION/IOFF) of 106. Gas sensing based on electrical resistance change depends on absorption and desorption rate of gases on the analyte which is governed by surface properties, morphologies and activation energy. Therefore, various morphologies of nanostructure were grown for gas sensing application. Through experimentation, the emphasis shifted to c-axis oriented ZnO nanostructures on SiO2 substrate for gas sensing. The c-axis orientation of ZnO nanostructures was preferred mainly due to its huge surface area. The measurements showed that the c-axis oriented ZnO nanorods were excellent hydrogen sensors, able to detect H2 as low concentration as 2 ppm, even when the sensing temperature is as low as 200 ˚C. However, oxygen sensing was achieved at a higher temperature (300 ˚C). Thus, the study undertaken in this thesis presents a microwave based rapid and economical method for synthesizing high quality, device grade ZnO nanostructures, their extensive characterization that shows the multifunctional properties of these structures, and there examples of varied device applications of the synthesized nanostructures as field emitters, memristors, and gas sensors.

Os avanços da indústria de semicondutores nas últimas décadas foram baseados fortemente na contínua redução de tamanho dos dispositivos CMOS fabricados. Os usos de dispositivos CMOS dependem profundamente da lógica de portas E/OU/INV. À medida que os dispositivos CMOS estão atingindo oslimites fisicos, pesquisadores aumento esforço para prolongar a vida útil da tecnologia CMOS. Também é necessário investigar dispositivos alternativos, que em muitos casos implicam no uso de operações lógicas básicas diferentes. Como as ferramentas comerciais de síntese não são capazes de manipular eficientemente estas tecnologias Esta tese de doutorado foca em produzir algoritmos eficientes para projeto de circuitos tanto em CMOS quanto em novas tecnologias, integrando estes algorithmos em fluxos de projeto. Para esta tarefa, aplicamos a técnica da composição functional, para sintetizar eficiente tanto em CMOS quanto em tecnologias emergentes. A composição funcional é uma abordagem de síntese de baixo para cima, provendo flexibilidade para implementar algoritmos com resultados ótimos ou sub-ótimos para diferentes tecnologias. A fim de investigar como a composição funcional se compara às abordagens de síntese estado-da-arte, propomos aplicar esse paradigma de síntese em seis cenários diferentes. Dois deles se concentram em circuitos baseados em CMOS e outros quatro em circuitos baseados em tecnologias emergentes. Em relação a circuitos baseados em CMOS, investigamos a composição funcional para fatoração de funções multi-saídas, aplicadas em um fluxo de resíntese. Também manipulamos funções aproximadas, a fim de sintetizar módulos de redundância tripla aproximada. No que diz respeito as tecnologias emergentes, exploramos a composição funcional através de diodos spintrônicos e outras abordagens promissoras com base em diferentes implementações de lógica: a lógica de limiar, lógica majoritária e lógica de implicação. Resultados apresentam uma melhoria considerável em relação aos métodos estadoda- arte tanto para aplicações CMOS quanto aplicações de tecnologias emergentes, demonstrando a capacidade de lidar com diferentes tecnologias e mostrando a possibilidade de melhorar tecnologias ainda não exploradas. / The advances in semiconductor industry over the last decades have been strongly based on continuous scaling down of dimensions in manufactured CMOS devices. The use of CMOS devices profoundly relies on AND/OR/Inverter logic. As the CMOS scaling is reaching its physical limits, researchers increase the effort to prolong the CMOS life. Also, it is necessary to investigate alternative devices, which in many cases implies the use of different basic logic operations. As the commercial synthesis tools are not able to handle these technologies efficiently, there is an opportunity to research alternative logic implementations better suited for these new devices. This thesis focuses on presenting efficient algorithms to design circuits in both CMOS and new technologies while integrating these algorithms into regular design flows. For this task, we apply the functional composition technique, to efficiently synthesize both CMOS and emerging technologies. The functional composition is a bottom-up synthesis approach, providing flexibility to implement algorithms with optimal or suboptimal results for different technologies. To investigate how the functional composition compares to the state-of-the-art synthesis methods, we propose to apply this synthesis paradigm into six different scenarios. Two of them focus on CMOS-based circuits, and other four are based on emerging technologies. Regarding CMOSbased circuits, we investigate functional composition to investigate multi-output factorization in a circuit resynthesis flow. Also, we manipulate approximate functions to synthesize approximate triple modular redundancy (ATMR) modules. Concerning emerging technologies, we explore functional composition over spin-diode circuits and other promising approaches based on different logic implementations: threshold logic, majority logic, and implication logic. Results present a considerable improvement over the state-of-the-art methods for both CMOS and emerging technologies applications, demonstrating the ability to handle different technologies and showing the possibility to improve technologies not explored yet.

In today's nanoscale era, scaling down to even smaller feature sizes poses a significant challenge in the device fabrication, the circuit, and the system design and integration. On the other hand, nanoscale technology has also led to novel materials and devices with unique properties. The memristor is one such emergent nanoscale device that exhibits non-linear current-voltage characteristics and has an inherent memory property, i.e., its current state depends on the past. Both the non-linear and the memory property of memristors have the potential to enable solving spatial and temporal pattern recognition tasks in radically different ways from traditional binary transistor-based technology. The goal of this thesis is to explore the use of memristors in a novel computing paradigm called "Reservoir Computing" (RC). RC is a new paradigm that belongs to the class of artificial recurrent neural networks (RNN). However, it architecturally differs from the traditional RNN techniques in that the pre-processor (i.e., the reservoir) is made up of random recurrently connected non-linear elements. Learning is only implemented at the readout (i.e., the output) layer, which reduces the learning complexity significantly. To the best of our knowledge, memristors have never been used as reservoir components. We use pattern recognition and classification tasks as benchmark problems. Real world applications associated with these tasks include process control, speech recognition, and signal processing. We have built a software framework, RCspice (Reservoir Computing Simulation Program with Integrated Circuit Emphasis), for this purpose. The framework allows to create random memristor networks, to simulate and evaluate them in Ngspice, and to train the readout layer by means of Genetic Algorithms (GA). We have explored reservoir-related parameters, such as the network connectivity and the reservoir size along with the GA parameters. Our results show that we are able to efficiently and robustly classify time-series patterns using memristor-based dynamical reservoirs. This presents an important step towards computing with memristor-based nanoscale systems.

Associative Memories (AMs) are essential building blocks for brain-like intelligent computing with applications in artificial vision, speech recognition, artificial intelligence, and robotics. Computations for such applications typically rely on spatial and temporal associations in the input patterns and need to be robust against noise and incomplete patterns. The conventional method for implementing AMs is through Artificial Neural Networks (ANNs). Improving the density of ANN based on conventional circuit elements poses a challenge as devices reach their physical scalability limits. Furthermore, stored information in AMs is vulnerable to destructive input signals. Novel nano-scale components, such as memristors, represent one solution to the density problem. Memristors are non-linear time-dependent circuit elements with an inherently small form factor. However, novel neuromorphic circuits typically use memristors to replace synapses in conventional ANN circuits. This sub-optimal use is primarily because there is no established design methodology to exploit the memristor's non-linear properties in a more encompassing way. The objective of this thesis is to explore denser and more robust AM designs using memristor networks. We hypothesize that such network AMs will be more area-efficient than the traditional ANN designs if we can use the memristor's non-linear property for spatial and time-dependent temporal association. We have built a comprehensive simulation framework that employs Genetic Programming (GP) to evolve AM circuits with memristors. The framework is based on the ParadisEO metaheuristics API and uses ngspice for the circuit evaluation. Our results show that we can evolve efficient memristor-based networks that have the potential to replace conventional ANNs used for AMs. We obtained AMs that a) can learn spatial and temporal correlation in the input patterns; b) optimize the trade-off between the size and the accuracy of the circuits; and c) are robust against destructive noise in the inputs. This robustness was achieved at the expense of additional components in the network. We have shown that automated circuit discovery is a promising tool for memristor-based circuits. Future work will focus on evolving circuits that can be used as a building block for more complicated intelligent computing architectures.

Les nouvelles techniques de fabrication nanométriques comme l'auto-assemblage ou la nanoimpression permettent de réaliser des matrices régulières (crossbars) atteignant des densités extrêmes (jusqu'à 1012 nanocomposants/cm2) tout en limitant leur coût de fabrication. Cependant, il est attendu que ces technologies s'accompagnent d'une augmentation significative du nombre de défauts et de dispersions de caractéristiques. La capacité à exploiter ces crossbars est alors conditionnée par le développement de nouvelles techniques de calcul capables de les spécialiser et de tolérer une grande densité de défauts. Dans ce contexte, l'approche neuromimétique qui permet tout à la fois de configurer les nanodispositifs et de tolérer leurs défauts et dispersions de caractéristiques apparaît spécialement pertinente. L'objectif de cette thèse est de démontrer l'efficacité d'une telle approche et de quantifier la fiabilité obtenue avec une architecture neuromimétique à base de crossbar de memristors, ou neurocrossbar (NC). Tout d'abord la thèse introduit des algorithmes permettant l'apprentissage de fonctions logiques sur un NC. Par la suite, la thèse caractérise la tolérance du modèle NC aux défauts et aux variations de caractéristiques des memristors. Des modèles analytiques probabilistes de prédiction de la convergence de NC ont été proposés et confrontés à des simulations Monte-Carlo. Ils prennent en compte l'impact de chaque type de défaut et de dispersion. Grâce à ces modèles analytiques il devient possible d'extrapoler cette étude à des circuits NC de très grande taille. Finalement, l'efficacité des méthodes proposées est expérimentalement démontrée à travers l'apprentissage de fonctions logiques par un NC composé de transistors à nanotube de carbone à commande optique (OG-CNTFET).

Os avanços da indústria de semicondutores nas últimas décadas foram baseados fortemente na contínua redução de tamanho dos dispositivos CMOS fabricados. Os usos de dispositivos CMOS dependem profundamente da lógica de portas E/OU/INV. À medida que os dispositivos CMOS estão atingindo oslimites fisicos, pesquisadores aumento esforço para prolongar a vida útil da tecnologia CMOS. Também é necessário investigar dispositivos alternativos, que em muitos casos implicam no uso de operações lógicas básicas diferentes. Como as ferramentas comerciais de síntese não são capazes de manipular eficientemente estas tecnologias Esta tese de doutorado foca em produzir algoritmos eficientes para projeto de circuitos tanto em CMOS quanto em novas tecnologias, integrando estes algorithmos em fluxos de projeto. Para esta tarefa, aplicamos a técnica da composição functional, para sintetizar eficiente tanto em CMOS quanto em tecnologias emergentes. A composição funcional é uma abordagem de síntese de baixo para cima, provendo flexibilidade para implementar algoritmos com resultados ótimos ou sub-ótimos para diferentes tecnologias. A fim de investigar como a composição funcional se compara às abordagens de síntese estado-da-arte, propomos aplicar esse paradigma de síntese em seis cenários diferentes. Dois deles se concentram em circuitos baseados em CMOS e outros quatro em circuitos baseados em tecnologias emergentes. Em relação a circuitos baseados em CMOS, investigamos a composição funcional para fatoração de funções multi-saídas, aplicadas em um fluxo de resíntese. Também manipulamos funções aproximadas, a fim de sintetizar módulos de redundância tripla aproximada. No que diz respeito as tecnologias emergentes, exploramos a composição funcional através de diodos spintrônicos e outras abordagens promissoras com base em diferentes implementações de lógica: a lógica de limiar, lógica majoritária e lógica de implicação. Resultados apresentam uma melhoria considerável em relação aos métodos estadoda- arte tanto para aplicações CMOS quanto aplicações de tecnologias emergentes, demonstrando a capacidade de lidar com diferentes tecnologias e mostrando a possibilidade de melhorar tecnologias ainda não exploradas. / The advances in semiconductor industry over the last decades have been strongly based on continuous scaling down of dimensions in manufactured CMOS devices. The use of CMOS devices profoundly relies on AND/OR/Inverter logic. As the CMOS scaling is reaching its physical limits, researchers increase the effort to prolong the CMOS life. Also, it is necessary to investigate alternative devices, which in many cases implies the use of different basic logic operations. As the commercial synthesis tools are not able to handle these technologies efficiently, there is an opportunity to research alternative logic implementations better suited for these new devices. This thesis focuses on presenting efficient algorithms to design circuits in both CMOS and new technologies while integrating these algorithms into regular design flows. For this task, we apply the functional composition technique, to efficiently synthesize both CMOS and emerging technologies. The functional composition is a bottom-up synthesis approach, providing flexibility to implement algorithms with optimal or suboptimal results for different technologies. To investigate how the functional composition compares to the state-of-the-art synthesis methods, we propose to apply this synthesis paradigm into six different scenarios. Two of them focus on CMOS-based circuits, and other four are based on emerging technologies. Regarding CMOSbased circuits, we investigate functional composition to investigate multi-output factorization in a circuit resynthesis flow. Also, we manipulate approximate functions to synthesize approximate triple modular redundancy (ATMR) modules. Concerning emerging technologies, we explore functional composition over spin-diode circuits and other promising approaches based on different logic implementations: threshold logic, majority logic, and implication logic. Results present a considerable improvement over the state-of-the-art methods for both CMOS and emerging technologies applications, demonstrating the ability to handle different technologies and showing the possibility to improve technologies not explored yet.

Os avanços da indústria de semicondutores nas últimas décadas foram baseados fortemente na contínua redução de tamanho dos dispositivos CMOS fabricados. Os usos de dispositivos CMOS dependem profundamente da lógica de portas E/OU/INV. À medida que os dispositivos CMOS estão atingindo oslimites fisicos, pesquisadores aumento esforço para prolongar a vida útil da tecnologia CMOS. Também é necessário investigar dispositivos alternativos, que em muitos casos implicam no uso de operações lógicas básicas diferentes. Como as ferramentas comerciais de síntese não são capazes de manipular eficientemente estas tecnologias Esta tese de doutorado foca em produzir algoritmos eficientes para projeto de circuitos tanto em CMOS quanto em novas tecnologias, integrando estes algorithmos em fluxos de projeto. Para esta tarefa, aplicamos a técnica da composição functional, para sintetizar eficiente tanto em CMOS quanto em tecnologias emergentes. A composição funcional é uma abordagem de síntese de baixo para cima, provendo flexibilidade para implementar algoritmos com resultados ótimos ou sub-ótimos para diferentes tecnologias. A fim de investigar como a composição funcional se compara às abordagens de síntese estado-da-arte, propomos aplicar esse paradigma de síntese em seis cenários diferentes. Dois deles se concentram em circuitos baseados em CMOS e outros quatro em circuitos baseados em tecnologias emergentes. Em relação a circuitos baseados em CMOS, investigamos a composição funcional para fatoração de funções multi-saídas, aplicadas em um fluxo de resíntese. Também manipulamos funções aproximadas, a fim de sintetizar módulos de redundância tripla aproximada. No que diz respeito as tecnologias emergentes, exploramos a composição funcional através de diodos spintrônicos e outras abordagens promissoras com base em diferentes implementações de lógica: a lógica de limiar, lógica majoritária e lógica de implicação. Resultados apresentam uma melhoria considerável em relação aos métodos estadoda- arte tanto para aplicações CMOS quanto aplicações de tecnologias emergentes, demonstrando a capacidade de lidar com diferentes tecnologias e mostrando a possibilidade de melhorar tecnologias ainda não exploradas. / The advances in semiconductor industry over the last decades have been strongly based on continuous scaling down of dimensions in manufactured CMOS devices. The use of CMOS devices profoundly relies on AND/OR/Inverter logic. As the CMOS scaling is reaching its physical limits, researchers increase the effort to prolong the CMOS life. Also, it is necessary to investigate alternative devices, which in many cases implies the use of different basic logic operations. As the commercial synthesis tools are not able to handle these technologies efficiently, there is an opportunity to research alternative logic implementations better suited for these new devices. This thesis focuses on presenting efficient algorithms to design circuits in both CMOS and new technologies while integrating these algorithms into regular design flows. For this task, we apply the functional composition technique, to efficiently synthesize both CMOS and emerging technologies. The functional composition is a bottom-up synthesis approach, providing flexibility to implement algorithms with optimal or suboptimal results for different technologies. To investigate how the functional composition compares to the state-of-the-art synthesis methods, we propose to apply this synthesis paradigm into six different scenarios. Two of them focus on CMOS-based circuits, and other four are based on emerging technologies. Regarding CMOSbased circuits, we investigate functional composition to investigate multi-output factorization in a circuit resynthesis flow. Also, we manipulate approximate functions to synthesize approximate triple modular redundancy (ATMR) modules. Concerning emerging technologies, we explore functional composition over spin-diode circuits and other promising approaches based on different logic implementations: threshold logic, majority logic, and implication logic. Results present a considerable improvement over the state-of-the-art methods for both CMOS and emerging technologies applications, demonstrating the ability to handle different technologies and showing the possibility to improve technologies not explored yet.

<p>U radu je razmatran problem dizajna i minimizacije rekurzivne<br />Bulove formule konstruisane za proizvoljnu Bulovu funkciju y:BN<br />&rarr;B.<br />U cilju rešavanja ovog problema, predstavljene su dve algoritamske<br />heuristike za minimizaciju rekurzivne Bulove formule. Minimizacija<br />rekurzivne Bulove formule vrši se korišćenjem regularnih poredaka<br />pozitivnih proizvod termova. U disertaciji je dokazano kako je ova<br />regularnost poredaka zapravo potreban i dovoljan uslov da željena<br />Bulova funcija y bude korektno predstavljena rekurzivnom Bulovom<br />formulom konstruisanom na osnovu tih poredaka. Pokazano je i kako<br />predstavljeni algoritmi daju bolje rezultate za veći broj instanci<br />problema u poređenju sa algoritmima dostupnim u literaturi.</p> / <p>In this thesis, the problem of design and minimization of recursive Boolean<br />formula, based on an arbitrary Boolean function y:BN<br />&rarr;B , is considered. As a<br />solution of a problem, two heuristic algorithms that minimize the length of<br />recursive Boolean formula, were presented. Minimization, itself, is done by<br />using regular orders of positive product terms. In the thesis it was proved that<br />the regularity of orders represents necessary and sufficient condition for<br />correct representation of Boolean function y by recursive Boolean formula<br />based on such regular order. Developed algorithms are compared with other<br />heuristic algorithms for recursive Boolean formula minimization, available in<br />the literature, and it is shown how algorithms proposed in this thesis provide<br />better results for more problem instances.</p>

The aim of the study presented in this thesis is to explore the electrical and physical properties of films of tin and lead clusters. Understanding the novel conductance properties of cluster films and related phenomenon such as coalescence is important to fabricate any cluster based devices. Coalescence is an important phenomenon in metallic cluster films. Due to coalescence the morphology of the films changes with time which changes their properties and could lead to failure in cluster devices. Coalescence is studied in Sn and Pb cluster films deposited on Si$_3$N$_4$ surfaces using Ultra High Vacuum (UHV) cluster deposition system. The conductance of the overall film is linked to the conductance of the individual necks between clusters by simulations. It is observed that the coalescence process in Sn and Pb films follows a power law in time with an exponent smaller than reported in literature. These results are substantiated by the results from previous experimental and Kinetic Monte Carlo (KMC) simulation studies at UC. Percolating films of Sn show unique conductance properties. These films are characterized using various electrode configurations, applied voltages and temperatures. The conductance measurements are performed by depositing clusters on prefabricated gold electrodes on top of Si$_3$N$_4$ substrates. Sn cluster films exhibit a variety of conductance behaviours during and after the end of deposition. It is observed that the evolution of conductance during the onsets at percolation threshold is dependent on the film morphology. Samples showing difference responses in onset also behave differently after the end of deposition. Therefore all samples were categorized according to their onset behaviour. After the end of deposition, when a bias voltage is applied, the conductance of Sn films steps up and down between various well-defined conductance levels. It is also observed that in many cases the conductance levels between which these devices jump are close to integral multiples of the conductance quantum. There are many possible explanations for the steps in conductance. One of the explanations is formation and breaking of conducting paths in the cluster films by electric field induced evaporation and electromigration respectively. The stepping behaviour is similar to that in non-volatile memory devices and hence very interesting to explore due to potential applications.