A differential current-mode track-and-hold (T/H) amplifier is used to sample an analog input signal. A new closed-loop current-mode architecture has been developed that overcomes the stability problems associated with closed-loop architectures. The T/H circuit has been fabricated in a 0.35-��m quad-metal, double-poly CMOS process. The measured total harmonic distortion (THD) is -81dB and -65dB with an input signal frequency of 100KHz and 10MHz, respectively. This is the best performance reported to date for a CMOS implementation. / Graduation date: 2003

An analysis that accounts for the effect of standard electrostatic discharge (ESD) structures on critical LNA specifications of noise figure, input matching and gain is presented. It is shown that the ESD structures degrade LNA performance particularly for higher frequency applications. Two LNAs, one with ESD protection and one without, which operate at 2.4 GHz have been fabricated in a 0.l5��m CMOS process. The LNAs feature one of the best reported performances for CMOS LNAs to date. The LNA with ESD protection achieves a gain of 12dB, a NF of 2.77dB and an IIP3 of 2.4dBm with a power consumption of 4.65mW. The LNA without ESD protection achieves a gain of 14dB, a NF of 2.36dB and an 11P3 of -2.2dBm with a power consumption of 4.65mW. / Graduation date: 2002

Graduation date: 2001

Thesis (M.S.)--Brigham Young University. Dept. of Electrical and Computer Engineering, 2006. / Includes bibliographical references (p. 53-54).

Thesis (Ph. D.)--University of Washington, 2006. / Vita. Includes bibliographical references (leaves 98-102).

Thesis (Ph. D.)--University of Washington, 2006. / Vita. Includes bibliographical references (p. 97-101).

Originally presented as the author's thesis (Swiss Federal Institute of Technology), Diss. ETH No. 16683. / Summary in Italian and English; text in English. Includes bibliographical references (p. 171-177).

M.S. / Computer Science / Software has been developed to analyze the power requirements of NMOS integrated circuits. Power usage is calculated for the entire chip. Current flow through each metal segment of VDD and GND lines is also calculated. The program, Pwranal, takes CIF format files as input and analyzes DC power requirements in the IC. Power estimates are worst case numbers. Power requirements may be less than the estimate but will not be more. Heuristics based on circuit topology are used to generate a more refined estimate of power needs. Initial values of nodes can be specified to provide an even more refined worst case power estimate. Current density is calculated and warning messages are displayed when it exceeds safe values. Maximum voltage drop in the VDD and GND lines is also calculated. An output summary is sent to the terminal. An optional CIF format output file can also be generated that contains detailed information about power distribution within the circuit.

The purpose of this work is to develop a new model for LDD n-MOSFET degradation in drain current under long-term AC use conditions for lifetime projection which includes a self-limiting effect in the hot-electron induced device degradation. Experimental results on LDD n-channel MOSFETs shows that the maximum drain current degradation is a function of the AC average substrate current under the various AC stress conditions but not a function of frequency or waveforms or different measurement configurations. An empirical model is constructed for circuit applications. It is verified that the self-limiting in drain current is due to the thermal re-emission of a trapped-hot-electron in the oxide. Results show that self-heating during AC stress releases trapped electrons, which in turn limits the maximum amount of drain current degradation. Moreover, tunneling to and from traps model is employed to visualize the internal mechanism of thermal recovery of electrons under different bias conditions. Although the LDD device structure can reduce the hot electron effect, various processing technologies can also affect the device reliability. A carbon doped LDD device with the first and the second level metal and passivation layer but without any final anneal shows that a significant reduction in the shifts of the threshold voltage of MOSFETs with time can be achieved. However, the long-term reliability projection of nMOSFETs based on DC stress tests alone is shown to be overly pessimistic. / Graduation date: 1992

Clock-feedthrough effects, channel-length modulation and device mismatch are the main causes of the inaccuracy of Switched-Current (SI) circuits. In this paper, these non-ideal effects are analyzed. A high-performance current mirror, namely regulated cascode current mirror, which eliminates drain voltage variation problem is introduced. By using this current mirror as a basic memory cell, a clock-feedthrough cancellation circuit is developed, which ideally solves the clock-feedthrough and drain voltage variation problems. A fifth-order SI lowpass Chebyshev ladder filter is built using the proposed cancellation circuit and implemented in a two-micron P-well standard digital CMOS process by MOSIS. Another emerging technique, dynamic current mirrors or current copiers, is introduced. Improved dynamic current mirror cell and dynamic current mirror-based integrators have been developed. / Graduation date: 1992