A successful transition from fossil fuels to renewable energies such as wind and solar will require the implementation of high-energy-density storage technologies. Promising energy storage technologies include lithium-ion batteries, metal-air batteries, and hydrogen production via photoelectrochemical water splitting. While these technologies differ substantially in their mode of operation, they often involve transition-metal oxides as a component. Thus, fundamental materials research on metal oxides will continue to provide much needed advances in these technologies. In this thesis, the electrochemical and electrocatalytic properties of Fe- and Mn-substituted layered LiNiO₂ materials were investigated. These materials were prepared by heating mixed nitrate precursors in O₂ atmosphere at 700-850 °C for 12 h with intermediate grindings. The products were chemically delithiated with NO₂BF₄, and the delithiated samples were annealed at moderate temperatures in order to transform them to a spinel-like phase. Samples were characterized by inductively coupled plasma analysis and Rietveld refinement of the X-ray diffraction patterns, which were found to be in reasonably close agreement regarding lithium stoichiometry. Spinel-like materials were found to possess an imperfect spinel structure when heated at lower temperatures and a significant amount of NiO impurity was formed when heated to higher temperatures. This structural disorder was manifested during electrochemical cycling -- only Mn-rich compositions showed reversible capacities at a voltage of around 4.5 V. The layered materials exhibited significant capacity loss upon cycling, and this effect was magnified with increasing Fe content. These materials were further investigated as catalysts for the oxygen evolution reaction (OER). All samples containing Mn exhibited low OER activity. In addition, delithiation degraded catalyst performance and moderate temperature annealing resulted in further degradation. Because delithiation significantly increased surface area, activities were compared to the relative to BET surface area. Li₀.₉₂Ni₀.₉Fe₀.₁O₂ exhibited significantly higher catalytic activity than Li₀.₈₉Ni₀.₇Fe₀.₃O₂. This prompted testing of Li[subscript x]Ni₁₋[subscript y]Fe[subscript y]O₂ (y = 0, 0.05, 0.1, 0.2, and 0.3) samples. It was found that a Fe content of approximately 10% resulted in the highest OER activity, with decreased activities for both larger and smaller Fe contents. These results were found to be consistent with studies of Fe substituted nickel oxides and oxyhydroxides, suggesting a similar activation mechanism. / text

Experiments were conducted on current-mirror MOSFETs to examine their suitability for use in radiation environments. These devices, which allow low loss load current sensing (defined by a current-ratio n'), are an important element of many power integrated circuits (PICs). Total-dose testing demonstrated that the current ratio was virtually unaffected for many operating conditions. In all cases, changes were largest when sense resistance was largest and minimal when sense voltage was approximately equal to the load source's voltage. In addition, testing verified the feasibility of using sense-cell MOSFETs for applications which require radiation exposure. A constant-current op-amp circuit showed minimal current shifts, using proper circuit design, following total-dose exposure. Dose-rate testing showed the feasibility of using sense voltage to trigger g&d2; protection through drain-source voltage clamping, providing a relatively inexpensive alternative to voltage derating.

Fast neutron irradiation tests were performed to determine the correlation of change of drain-source resistance and neutron fluence for power MOSFETs. The Objectives of the tests were: (1) to detect and measure the degradation of critical MOSFET device parameters as a function of neutron fluence (2) to compare the experimental results and the theoretical model. In general, the drain-source resistance increased from 1 Ohm to 100 Ohm after exposure to fast neutron fluence of 3 x 1014 neut/cm2, and decreased by a factor of five after high temperature annealing.

Many high performance amplifiers use power MOSFETs in their output stages, especially in operational amplifier applications whenever high current or power is needed. MOSFETs have advantages over bipolar transistors in amplifier output stage because MOSFETs are majority carrier devices. The result is wide frequency response, fast switching and better linearity than power bipolar transistors. But unlike bipolar circuits, which are relatively tolerant of ionizing radiation, MOSFETs may suffer severe parametric degradation at low total-dose levels. The effects of ionizing radiation on MOSFETs are discussed, and the performance of an amplifier circuit that uses a complementary MOSFET source follower in its output stage is simulated to examine the effect of MOSFET radiation damage on amplifier performance. An increase in power dissipation was the most significant degradation caused by ionizing radiation.

Clean and affordable energy, especially solar energy, is becoming more and more important as our annual total energy consumption keeps rising. However, to make solar energy more affordable and accessible, the cost for fabrication, transportation and assembly of all components need to be reduced. As a crucial component for solar cells, transparent conductive electrode (TCE) can determine the cost and performance. A light weight, easy-to-fabricate and cost-effective new generation TCE is thus needed. While indium-doped tin oxide (ITO) has been the most widely used material for commercial applications as TCEs, its cost has gone up due to the limited global supply of indium. This is not only due to the scarcity of the element itself, but also the massive production of various opto-electronic devices such as TVs, smartphones and tablets. In order to reduce the cost for fabricating large area solar cells, substitute materials for ITO should be developed. These materials should have similar optical transmittance in the visible wavelength range, as well as similar electrical conductivity (sheet resistance) to ITO. This work starts with synthesizing ITO-replacing nano-materials, such as copper nanowires (CuNWs), derivative zinc oxide (ZnO) thin films, reduced graphene oxide (rGO) and so on. Further, we applied various deposition techniques, including spin-coating, spray-coating, Mayer-rod coating, filtration and transferring, to coat transparent substrates with these materials in order to fabricate TCEs. We characterize these materials and analyze their electrical/optical properties as TCEs. Additionally, these fabricated single-material-based TCEs were tested in various lab conditions, and their shortcomings (instability, rigidity, etc.) were highlighted. In order to address these issues, we hybridized the different materials to combine their strengths and compared the properties to single-material based TCEs. The multiple hybridized TCEs have comparable optical/electrical metrics to ITO. The doped-ZnO TCEs exhibit high optical transmittance over 90% in the visible range and low sheet resistance under 200Ω/sq. For CuNW-based composite electrodes, ~ 85% optical transmittance and ~ 25Ω/sq were observed. Meanwhile, the hybridization of materials adds additional features such as flexibility or resistance to corrosion. Finally, as a proof of concept, the CuNW-based composite TCEs were tested in dye-sensitized solar cells (DSSCs), showing similar performance to ITO based samples.

• Abstract Integrated digital imaging systems are widely used in consumer electronics today. Current digital image sensors have a linear respeiiSt. The limited dynamic range of linear digital image sensors results in saturation when the input dynamic range of the scene is larger than that of the camera. This limitation could be overcome using pixels with an output that is proportional to the logarithm of the detected photocurrent. Conventional CMOS pixels with a logarithmic response, using a transistor operating in the sub-threshold region, are capable of capturing wide dynamic range scenes with more than six decades of illumination intensity. But these pixels suffer from fixed pattern noise, slow response and low sensitivity. A five transistor (5T) pixel circuit for a standard 0.35-fLm CMOS process which integrates the photocurrent linearly and capable of a logarithmic response is described in the thesis. A key component of the 5T pixel is a time-dependent reference voltage. This voltage is applied to the gate of one of the transistors inside each pixel in the array for the duration of the exposure to generate a logarithmic response. A model derived to generate the reference voltage is described. Improvements were made to the reference voltage model to take into consideration the non-ideal effects such as charge feedthrough and threshold voltage variations. A potential problem associated with successfully tonemapping low photo currents with the 5T pixel has been described and a method to calculate the optimal value of reference current Iret proposed. This was shown to lead to an optimum photoresponse. Measurement results from fabricated 1-D and 2-D arrays of 5T pixels are presented and analysed. An overall DR of 97-dB (almost 5 decades) has been achieved from 100 mlux to 6.7 Klux. The slope of the logarithmic photoresponse was shown to be adjustable and controlled by the slope parameter S in the reference voltage model. A large output swing of over 1 V due to the large photoresponse slope in the logarithmic region results in greater signal-to-noise ratio compared to the conventional logarithmic pixel based on the subthreshold transistor operation (60 m V/decade). Digital and analogue reference voltage generating techniques are described with circuits implemented in 0.35-fLm CM OS process. Finally, a 5T NMOS pixel that is capable of WDR imaging with superior low-light performance (23 mlux) and greater DR (1l0-dB) than the 5T PMOS pixel is described. [ a

Thesis advisor: Dunwei Wang / Solar water splitting refers to the reaction that converts solar energy into chemical fuel. It is an attractive means to store solar energy. This process, analogous to nature photosynthesis, uses semiconductor to capture and convert solar irradiation and, as such, is called artificial photosynthesis. Despite its promising prospect, the lack of materials that can satisfy all requirements to achieve efficient solar water splitting becomes an important challenge. In this thesis, we aim to develop a strategy of forming heteronanostructure to tackle the challenge faced by metal oxide-based photoanode for water oxidation. The challenge associated with metal oxide-based photoanodes and current approach to alleviate the challenge is first discussed. We propose a strategy of combining multiple components to form heteronanostructure to meet the challenges, in particular the charge transport issue. By introducing a dedicated charge transporter, we fabricate various heteronanostructure including TiO₂/TiSi₂, Fe₂O₃/TiSi₂ and Fe₂O₃/AZO nanotubes to improve the charge collection and therefore overall efficiency. Additionally, the growth of several important metal oxides by atomic layer deposition is developed and its utilization as photoanode for water splitting is studied for the first time. Because this strategy is based on the rational design and synthesis of materials, it has the potential to produce electrodes with a combination of properties that have not been exhibited simultaneously by single-component materials. In addition, the strategy is highly versatile and can incorporate the latest developments produced by parallel efforts. We are confident that the rational design and synthesis of materials such as the strategy proposed here will play an increasingly more important role in energy research. / Thesis (PhD) — Boston College, 2012. / Submitted to: Boston College. Graduate School of Arts and Sciences. / Discipline: Chemistry.

University of Macau / Faculty of Science and Technology. / Department of Electrical and Computer Engineering

by Man-chung Suen. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1994. / Includes bibliographical references (leaves [123]-[126]). / Acknowledgement --- p.ii / Abstract --- p.iii / List of Tables --- p.vii / List of Figures --- p.xii / Chapter 1 --- Introduction --- p.1 / Chapter 2 --- Approach to Find the Equivalent Models --- p.5 / Chapter 2.1 --- Scattering Parameters of the Microstrip Structure --- p.5 / Chapter 2.2 --- Optimization Process --- p.7 / Chapter 2.3 --- Summary --- p.8 / Chapter 3 --- Microstrip Discontinuities Being Modelled --- p.9 / Chapter 3.1 --- Right-Angled Bend --- p.9 / Chapter 3.2 --- T-Junction --- p.10 / Chapter 3.3 --- Tapered Line --- p.10 / Chapter 4 --- Deficiency of Lumped Equivalent Circuits --- p.13 / Chapter 4.1 --- Scattering Parameter of the T-Network --- p.13 / Chapter 4.2 --- Optimization Result for the T-Network --- p.14 / Chapter 4.3 --- Summary --- p.15 / Chapter 5 --- Proposed Wideband Equivalent Circuits --- p.17 / Chapter 5.1 --- Model of a Uniform Non-Homogeneous Microstrip Line --- p.17 / Chapter 5.2 --- Right-Angled Bend --- p.22 / Chapter 5.2.1 --- Circuit 1L --- p.24 / Chapter 5.2.2 --- Circuit 2L --- p.25 / Chapter 5.2.3 --- Circuit 3L --- p.26 / Chapter 5.2.4 --- Circuit 4L --- p.27 / Chapter 5.3 --- T-Junction --- p.28 / Chapter 5.3.1 --- Circuit IT --- p.28 / Chapter 5.3.2 --- Circuit 2T --- p.31 / Chapter 5.3.3 --- Circuit 3T --- p.31 / Chapter 5.3.4 --- Circuit 4T --- p.34 / Chapter 5.4 --- Tapered Line --- p.36 / Chapter 5.4.1 --- Circuit It -n =3 --- p.37 / Chapter 5.5 --- Summary --- p.38 / Chapter 6 --- Performance of the Equivalent Circuits --- p.39 / Chapter 6.1 --- Right-Angled Bend --- p.40 / Chapter 6.1.1 --- Without Conductor Loss --- p.40 / Chapter 6.1.2 --- With Conductor Loss --- p.48 / Chapter 6.2 --- T-Junction --- p.49 / Chapter 6.2.1 --- Without Conductor Loss --- p.53 / Chapter 6.2.2 --- With Conductor Loss --- p.63 / Chapter 6.3 --- Tapered Line --- p.69 / Chapter 6.3.1 --- Without Conductor Loss --- p.69 / Chapter 6.3.2 --- With Conductor Loss --- p.72 / Chapter 6.4 --- Summary --- p.73 / Chapter 7 --- Modelling Performance Using TEM Approximation --- p.77 / Chapter 7.1 --- Right-Angled Bend --- p.77 / Chapter 7.1.1 --- Without Conductor Loss --- p.78 / Chapter 7.1.2 --- With Conductor Loss --- p.87 / Chapter 7.2 --- T-Junction --- p.92 / Chapter 7.2.1 --- Without Conductor Loss --- p.92 / Chapter 7.2.2 --- With Conductor Loss --- p.104 / Chapter 7.3 --- Tapered Line --- p.115 / Chapter 7.3.1 --- Without Conductor Loss --- p.116 / Chapter 7.3.2 --- With Conductor Loss --- p.117 / Chapter 7.4 --- Summary --- p.117 / Chapter 8 --- Conclusion --- p.120 / Bibliography --- p.123

Mak Wing-sum. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2000. / Includes bibliographical references (leaf [68]). / Abstracts in English and Chinese. / List of Figures --- p.I / List of Tables --- p.III / ACKNOWLEDGMENTS / ABSTRACT / Chapter Chapter I --- Introduction / Chapter 1.1 --- Introduction - Low Power --- p.I-1 / Chapter 1.2 --- Power Consumption in cmos Circuit --- p.I-1 / Chapter 1.2.1 --- Static Power Dissipation --- p.I-2 / Chapter 1.2.2 --- Dynamic Power Dissipation --- p.I-5 / Chapter 1.2.3 --- Short Circuit Power Dissipation --- p.I-8 / Chapter 1.3 --- Total Power Consumption of a CMOS Circuit --- p.I-10 / Chapter 1.4 --- Objective of the Project --- p.I-10 / Chapter CHAPTER II --- Background : Low Power Electronic - Adiabatic Logic / Chapter 2.1 --- Low Power Design --- p.II-12 / Chapter 2.2 --- Adiabatic Switching --- p.II-12 / Chapter 2.3 --- Adiabatic Logic --- p.II-14 / Chapter 2.4 --- History of Adiabatic Logic --- p.II-17 / Chapter CHAPTER III --- Adiabatic Quasi-Static CMOS Inverter / Chapter 3.1 --- Building Block of AqsCMOS Logic --- p.III -18 / Chapter 3.2.1 --- AqsCMOS Inverter --- p.III -20 / Chapter 3.2.2 --- Diodes of AqsCMOS Inverter --- p.III -22 / Chapter 3.3 --- Pipeline Clocking of AqsCMOS Inverter Chain --- p.III -23 / Chapter Chapter IV --- Power Clock Generator / Chapter 4.1 --- Inductor - Capacitor Oscillator --- p.IV -24 / Chapter 4.2 --- Power Clock Generator / Chapter 4.2.1 --- Structure of Power Clock Generator --- p.IV / Chapter 4.2.2 --- power Consumption of Power Clock Generator --- p.IV -27 / Chapter Chapter V --- Adiabatic QuasI-Static CMOS Multiplier / Chapter 5.1 --- Baugh - Wooley Multiplier --- p.V-32 / Chapter 5.2 --- Structure of Multiplier --- p.V-34 / Chapter Chapter VI --- Simulations / Chapter 6.1 --- AqsCMOS Inverter / Chapter 6.1.1 --- Logic Alignment of AqsCMOS Inverter --- p.VI -38 / Chapter 6.1.2 --- Practical Implementation of AqsCMOS Inverter --- p.VI -39 / Chapter 6.1.3 --- Pipeline Clocking of AqsCMOS Inverter Chain --- p.VI / Chapter 6.2 --- Power Clock Generator --- p.VI -42 / Chapter 6.3 --- AqsCMOS Pipeline Multiplier --- p.VI -45 / Chapter 6.3.1 --- power estimation of multiplier --- p.VI -46 / Chapter ChapterVII --- evaluations / Chapter 7.1 --- Testing Modules of AqsCMOS Inverter Chain --- p.VII -51 / Chapter 7.2 --- Evaluation of AqsCMOS Multiplier Testing Modulus / Chapter 7.2.1 --- Multiplier Chips Implementation --- p.VII -54 / Chapter 7.2.2 --- AQSCMOS Vs CMOS MULTIPLIER --- p.VII -55 / Chapter 7.2.3 --- Input Current Measurement --- p.VII -58 / Chapter 7.3 --- Power Measurement --- p.VII -63 / Chapter Chapter VIII --- Conclusions and Fiirthfr Developments / Chapter 8.1 --- Conclusions --- p.VIII -65 / Chapter 8.1.1 --- AqsCMOS Inverter --- p.VIII -65 / Chapter 8.1.2 --- Power Clock Generator --- p.VIII -65 / Chapter 8.1.3 --- AQSCMOS MULTIPLIER --- p.VIII -66 / Chapter 8.2 --- Further Development --- p.VIII -66 / Appendix I micro-photography of aqscmos multiplier / Appendix II micro-Photography of CMOS multiplier / Appendix III micro-photography of AqsCMOS inverter chain testing modules / Appendix IV power - meter simulation approach / Appendix V Measurement Setting of AqsCMOS & CMOS Multipliers / Reference