Ku Man-Ho. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1995. / Includes bibliographical references (leaves 86-87). / Chapter 1. --- Introduction / Chapter 1.1. --- Introduction --- p.1 / Chapter 1.2. --- Power Noise --- p.2 / Chapter 1.3. --- High Speed Output Driver Design --- p.3 / Chapter 2. --- Power Bus Noise Analysis / Chapter 2.1. --- Introduction --- p.7 / Chapter 2.2. --- The Power bus model of a packed VLSI chip --- p.7 / Chapter 2.3. --- The effects of bonding wire on Power bus --- p.11 / Chapter 2.4. --- Noise analysis of multi-driver switching --- p.15 / Chapter 3. --- Effects of Power bus noise / Chapter 3.1. --- Introdcution --- p.22 / Chapter 3.2. --- Digital noise definition --- p.22 / Chapter 3.3. --- Static CMOS Inverter --- p.23 / Chapter 3.4. --- Dynamic gate --- p.32 / Chapter 4. --- Output Driver Design / Chapter 4.1. --- Introduction --- p.37 / Chapter 4.2. --- Optimum Discharge Current Waveform --- p.37 / Chapter 4.3. --- Simple Inverter Output driver --- p.40 / Chapter 4.4. --- Weighted and Distributed Driver --- p.42 / Chapter 4.5. --- Short circuit current prevention circuit --- p.50 / Chapter 5.6. --- Adaptive output driver --- p.52 / Chapter 5. --- Test chip Implementation / Chapter 5.1. --- Introduction --- p.57 / Chapter 5.2. --- Output Driver Circuit Design --- p.57 / Chapter 5.3. --- Simulation Results --- p.62 / Chapter 5.4. --- Test chip circuit --- p.65 / Chapter 5.5. --- Physical design --- p.67 / Chapter 6. --- Test Chip evaluation / Chapter 6.1. --- Introduction --- p.75 / Chapter 6.2. --- Rise time and overshoot Test --- p.76 / Chapter 6.3. --- Switching noise --- p.79 / Chapter 6.4. --- Driving Test --- p.82 / Chapter 7. --- Conslusions --- p.84 / Chapter 8. --- References --- p.86 / Chapter 9. --- Appendix A --- p.88 / Chapter 10. --- Appendix B --- p.91 / Chapter 11. --- Appendix C --- p.100 / Chapter 12. --- Appendix D --- p.101 / Chapter 13. --- Appendix E --- p.102

Ho Kin-Pui. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2002. / Includes bibliographical references (leaves 92-95). / Abstracts in English and Chinese. / Abstract --- p.2 / 摘要 --- p.4 / Acknowledgements --- p.5 / Table of Contents --- p.6 / List of Figures --- p.10 / List of Tables --- p.14 / Chapter Chapter 1 --- Introduction --- p.15 / Overview --- p.15 / Objective --- p.17 / Thesis Organization --- p.17 / Chapter Chapter 2 --- Fundamentals of Operational Amplifier --- p.19 / Chapter 2.1 --- Definitions of Commonly Used Figures --- p.19 / Chapter 2.1.1 --- Input Differential Voltage Range --- p.19 / Chapter 2.1.2 --- Maximum Output Voltage Swing --- p.20 / Chapter 2.1.3 --- Input Common Mode Voltage Range --- p.20 / Chapter 2.1.4 --- Input Offset Voltage --- p.20 / Chapter 2.1.5 --- Gain Bandwidth Product --- p.21 / Chapter 2.1.6 --- Phase Margin --- p.22 / Chapter 2.1.7 --- Slew Rate --- p.22 / Chapter 2.1.8 --- Settling Time --- p.23 / Chapter 2.1.9 --- Common Mode Rejection Ratio --- p.23 / Chapter 2.2 --- Frequency Compensation of Operational Amplifier --- p.24 / Chapter 2.2.1 --- Overview --- p.24 / Chapter 2.2.2 --- Miller Compensation --- p.25 / Chapter Chapter 3 --- CMOS Current Feedback Operational Amplifier --- p.27 / Chapter 3.1 --- Introduction --- p.27 / Chapter 3.2 --- Current Feedback Operational Amplifier with Active Current Mode Compensation --- p.28 / Chapter 3.2.1 --- Circuit Description --- p.29 / Chapter 3.2.2 --- Small Signal analysis --- p.32 / Chapter 3.2.3 --- Simulation Results --- p.34 / Chapter Chapter 4 --- Reversed Nested Miller Compensation --- p.38 / Chapter 4.1 --- Introduction --- p.38 / Chapter 4.2 --- Frequency Response --- p.39 / Chapter 4.2.1 --- Gain-bandwidth product --- p.40 / Chapter 4.2.2 --- Right half complex plane zero --- p.40 / Chapter 4.2.3 --- The Pair of Complex Conjugate Poles --- p.42 / Chapter 4.3 --- Components Sizing --- p.47 / Chapter 4.4 --- Circuit Simulation --- p.48 / Chapter Chapter 5 --- Enhancement Technique for Reversed Nested Miller Compensation --- p.54 / Chapter 5.1 --- Introduction --- p.54 / Chapter 5.2 --- Working principle of the proposed circuit --- p.54 / Chapter 5.2.1 --- The introduction of nulling resistor --- p.55 / Chapter 5.2.2 --- The introduction of a voltage buffer --- p.55 / Chapter 5.2.3 --- Small Signal Analysis --- p.57 / Chapter 5.2.4 --- Sign Inversion of the RHP Zero with Nulling Resistor --- p.59 / Chapter 5.2.5 --- Frequency Multiplication of the Complex Conjugate Poles --- p.60 / Chapter 5.2.6 --- Stability Conditions --- p.63 / Chapter 5.3 --- Performance Comparison --- p.67 / Chapter 5.4 --- Conclusion: --- p.70 / Chapter 5.4.1 --- Circuit Modifications: --- p.70 / Chapter 5.4.2 --- Advantages: --- p.71 / Chapter Chapter 6 --- Physical Design of Operational Amplifier --- p.72 / Chapter 6.1 --- Introduction --- p.72 / Chapter 6.2 --- Transistor Layout Techniques --- p.72 / Chapter 6.2.1 --- Multi-finger Layout Technique --- p.72 / Chapter 6.2.2 --- Common-Centroid Structure --- p.73 / Chapter 6.3 --- Layout Techniques of Passive Components --- p.74 / Chapter 6.3.1 --- Capacitor Layout --- p.74 / Chapter 6.3.2 --- Resistor Layout --- p.75 / Chapter Chapter 7 --- Measurement Results --- p.77 / Chapter 7.1 --- Overview --- p.77 / Chapter 7.2 --- Measurement Results for the Current Feedback Operational Amplifier --- p.77 / Chapter 7.2.1 --- Frequency Response of the inverting amplifier --- p.77 / Chapter 7.3 --- Measurement Results for the Three-Stage Operational Amplifier --- p.80 / Chapter 7.3.1 --- Input Offset Voltage Measurement --- p.80 / Chapter 7.3.2 --- Input Common Mode Range Measurement --- p.80 / Chapter 7.3.3 --- Gain Band width Measurement --- p.81 / Chapter 7.3.4 --- DC Gain measurement --- p.85 / Chapter 7.3.5 --- Slew Rate Measurement --- p.87 / Chapter 7.3.6 --- Phase Margin --- p.88 / Chapter 7.3.7 --- Performance Summary --- p.89 / Chapter Chapter 8 --- Conclusions --- p.90 / Chapter Chapter 9 --- Appendix --- p.96

by Cheuk-Him, To. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1998. / Includes bibliographical references. / Abstract also in Chinese. / ACKNOWLEDGMENT --- p.I / ABSTRACT (ENGLISH) --- p.II / ABSTRACT (CHINESE) --- p.III / CONTENTS --- p.IV / TABLE OF FIGURES --- p.VI / Chapter CHAPTER 1 --- INTRODUCTION --- p.1-1 / Chapter 1.1 --- Introduction --- p.1-1 / Chapter 1.2 --- Different types of DCO --- p.1-2 / Chapter 1.2.1 --- Divided by N counter --- p.1-2 / Chapter 1.2.2 --- Increment-decrement counter --- p.1-2 / Chapter 1.2.3 --- Controlled delay ring oscillator --- p.1-4 / Chapter 1.3 --- Problems suffered from these circuits --- p.1-4 / Chapter 1.4 --- Characteristics of the proposed circuit --- p.1-5 / Chapter CHAPTER 2 --- BACKGROUND THEORY --- p.2-1 / Chapter 2.1 --- Ring Oscillator --- p.2-1 / Chapter 2.2 --- Differential Pair --- p.2-1 / Chapter 2.3 --- Injection Locked Oscillator (ILO) --- p.2-2 / Chapter 2.4 --- Digital Controlled Oscillator --- p.2-3 / Chapter CHAPTER 3 --- DESIGN --- p.3-1 / Chapter 3.1 --- Circuit Description --- p.3-1 / Chapter 3.1.1 --- D/A converter --- p.3-2 / Chapter 3.1.2 --- Injection Locked Oscillator (ILO) --- p.3-3 / Chapter 3.2 --- Design Characteristics --- p.3-5 / Chapter 3.2.1 --- D/A converter --- p.3-5 / Chapter 3.2.2 --- ILO --- p.3-7 / Chapter 3.2.3 --- Physical Design (Layout Drawing) --- p.3-8 / Chapter CHAPTER 4 --- RESULTS --- p.4-1 / Chapter 4.1 --- Chip1 --- p.4-1 / Chapter 4.1.1 --- Simulation --- p.4-3 / Chapter 4.1.2 --- Measurement --- p.4-15 / Chapter 4.1.3 --- Evaluation --- p.4-23 / Chapter 4.2 --- Chip2 --- p.4-25 / Chapter 4.2.1 --- Simulation --- p.4-25 / Chapter 4.2.2 --- Measurement --- p.4-36 / Chapter 4.2.3 --- Evaluation --- p.4-47 / Chapter CHAPTER 5 --- CONCLUSION --- p.5-1 / REFERENCES: --- p.1 / APPENDIX: --- p.1

by Kelvin Cheung Ka Wai. / Thesis submitted in: June 1997. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1998. / Includes bibliographical references. / ACKNOWLEDGEMENTS --- p.i / ABSTRACT --- p.ii / TABLE OF CONTENTS --- p.iii / LIST OF FIGURES --- p.vi / TIST OF TABLES --- p.viii / Chapter 1. --- INTRODUCTION --- p.1-1 / Chapter 1.1 --- Introduction --- p.1-1 / Chapter 1.2 --- Objective --- p.1-1 / Chapter 1.3 --- Static CMOS Logic and Dynamic Logic --- p.1-1 / Chapter 1.3.1 --- static CMOS logic circuit --- p.1-1 / Chapter 1.3.2 --- Dynamic logic --- p.1-2 / Chapter 1.4 --- Power Consumption in Static CMOS Integrated Circuit --- p.1-4 / Chapter 1.4.1 --- Static power dissipation --- p.1 -4 / Chapter 1.4.2 --- Dynamic power dissipation --- p.1 -6 / Chapter 1.4.2.1 --- Short circuit current --- p.1 -6 / Chapter 1.4.2.2 --- Charging and discharging of load capacitances --- p.1-6 / Chapter 1.4.2.3 --- Total power consumption --- p.1-8 / Chapter 1.5 --- Adiabatic Logic --- p.1-8 / Chapter 1.5.1 --- Low power electronics --- p.1-8 / Chapter 1.5.2 --- History of adiabatic logic --- p.1 -9 / Chapter 1.6 --- Resources --- p.1-10 / Chapter 1.6.1 --- Computing instrument --- p.1-10 / Chapter 1.6.2 --- CAD tools --- p.1-10 / Chapter 1.6.3 --- Fabrication --- p.1-11 / Chapter 1.7 --- Organisation of the Thesis --- p.1-11 / Chapter 2. --- BACKGROUND THEORIES --- p.2-1 / Chapter 2.1 --- Limit of energy dissipation --- p.2-1 / Chapter 2.2 --- Reversible Electronics --- p.2-1 / Chapter 2.2.1 --- Reversibility --- p.2-1 / Chapter 2.2.2 --- Adiabatic Switching --- p.2-3 / Chapter 2.2.2.1 --- Conventional Charging --- p.2-3 / Chapter 2.2.2.2 --- Adiabatic Charging --- p.2-4 / Chapter 2.2.3 --- Reversible devices --- p.2-5 / Chapter 2.3 --- Compatibility to CMOS Logic --- p.2-6 / Chapter 3. --- ADIABATIC QUASI-STATIC CMOS --- p.3-1 / Chapter 3.1 --- Swinging between 0 and 1 by Harmonic Motion --- p.3-1 / Chapter 3.1.1 --- Starting from a simple pendulum --- p.3-1 / Chapter 3.1.2 --- Inductor-capacitor oscillator --- p.3-2 / Chapter 3.2 --- Redistribution of Charge --- p.3-3 / Chapter 3.3 --- Adiabatic Quasi-static Logic --- p.3-4 / Chapter 3.3.1 --- False reversible inverter --- p.3-4 / Chapter 3.3.2 --- Adiabatic inverter --- p.3-5 / Chapter 3.3.3 --- Effective capacitance --- p.3-7 / Chapter 3.3.4 --- Logic alignment --- p.3-8 / Chapter 3.3.5 --- Cascading the adiabatic inverters --- p.3-10 / Chapter 3.3.5.1 --- Compensated cascading --- p.3-10 / Chapter 3.3.5.2 --- Balanced cascading --- p.3-11 / Chapter 3.4 --- Frequency Control --- p.3-12 / Chapter 3.5 --- Compatibility of AqsCMOS with Static CMOS Logic --- p.3-13 / Chapter 4. --- ADIABATIC QUASI-STATIC CMOS INVERTERS --- p.4-1 / Chapter 4.1 --- Design --- p.4-1 / Chapter 4.1.1 --- Realisation of current direction control device --- p.4-1 / Chapter 4.1.2 --- Implementation of AqsCMOS inverter by current direction control device --- p.4-2 / Chapter 4.1.3 --- Layout --- p.4-3 / Chapter 4.1.3.1 --- Horizontal Transistor Diode --- p.4-3 / Chapter 4.1.3.2 --- Transistor pair --- p.4-9 / Chapter 4.2 --- Capacitance Calculation --- p.4-9 / Chapter 4.2.1 --- Non-switching device --- p.4-10 / Chapter 4.2.2 --- Switching device --- p.4-11 / Chapter 4.3 --- Clocking Scheme --- p.4-13 / Chapter 4.4 --- Energy Loss of AqsCMOS inverter --- p.4-14 / Chapter 5. --- ADIABATIC CLOCKS GENERATOR --- p.5-1 / Chapter 5.1 --- Introduction --- p.5-1 / Chapter 5.2 --- Full Adiabatic Clocks Generator --- p.5-1 / Chapter 5.2.1 --- Sizes of the transistors used --- p.5-2 / Chapter 5.2.2 --- Energy consumption of full adiabatic clocks generator --- p.5-3 / Chapter 5.3 --- Half Adiabatic Clocks Generator --- p.5-4 / Chapter 5.3.1 --- Transistor sizing --- p.5-5 / Chapter 5.3.2 --- Energy consumption of the half adiabatic clock generator --- p.5-5 / Chapter 5.3.3 --- Weakness of the half adiabatic clocks generator --- p.5-6 / Chapter 5.4 --- Automatic Adiabatic Clocks Generator --- p.5-6 / Chapter 5.4.1 --- Operation of automatic adiabatic clocks generator --- p.5-7 / Chapter 5.4.2 --- Energy consumption of automatic adiabatic clocks generator --- p.5-9 / Chapter 6. --- EVALUATION --- p.6-1 / Chapter 6.1 --- Introduction --- p.6-1 / Chapter 6.2 --- Simulation Results --- p.6-1 / Chapter 6.2.1 --- Adiabatic clocks generators --- p.6-1 / Chapter 6.2.2 --- Adiabatic quasi-static CMOS inverters --- p.6-4 / Chapter 6.2.2.1 --- Functional evaluation --- p.6-4 / Chapter 6.2.2.2 --- Performance evaluation --- p.6-6 / Chapter 6.3 --- Test Circuit - Pendulum --- p.6-8 / Chapter 6.3.1 --- Layout --- p.6-8 / Chapter 6.3.2 --- Test circuit of pendulum --- p.6-10 / Chapter 6.3.3 --- Module 1 - Full adiabatic clocks generator (fclk) --- p.6-11 / Chapter 6.3.4 --- Module 2 - Half adiabatic clocks generator (hclk) --- p.6-13 / Chapter 6.3.5 --- Module 3 to 5- Adiabatic inverter chains --- p.6-14 / Chapter 6.3.5.1 --- DC characteristics --- p.6-14 / Chapter 6.3.5.2 --- AC characteristics --- p.6-14 / Chapter 6.3.6 --- Power dissipation --- p.6-17 / Chapter 7 --- CONCLUSIONS --- p.7-1 / Chapter 7.1 --- Introduction --- p.7-1 / Chapter 7.2 --- Design --- p.7-1 / Chapter 7.2.1 --- Adiabatic quasi-static CMOS logic --- p.7-1 / Chapter 7.2.2 --- Adiabatic quasi-static CMOS inverters --- p.7-2 / Chapter 7.2.3 --- Adiabatic clocks generator --- p.7-2 / Chapter 7.3 --- Function --- p.7-3 / Chapter 7.4 --- Power Dissipation --- p.7-3 / Chapter 7.5 --- Discussion --- p.7-3 / Chapter 7.6 --- Further Development --- p.7-3 / Chapter 7.7 --- Conclusion --- p.7-4 / Chapter 8. --- REFERENCES --- p.8-1 / APPENDIX I TABLE OF PTN LAYOUT PENDULUM --- p.I-1 / APPENDIX II PHOTOGRAPHS OF PENDULUM --- p.II-1

by Chung-Yuk Or. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1998. / Includes bibliographical references (leaves 95-[98]). / Abstract also in Chinese. / Chapter 1 --- Introduction --- p.1 / Chapter 2 --- Fully Differential CMOS Operational Amplifier Design --- p.4 / Chapter 2.1 --- Wide-Swing Current Mirror --- p.5 / Chapter 2.2 --- Wide-Swing Biasing Network --- p.8 / Chapter 2.3 --- Fully differential folded-cascode operational amplifier --- p.13 / Chapter 2.3.1 --- Small-Signal Analysis --- p.16 / Chapter 2.4 --- Gain-boost technique --- p.18 / Chapter 2.4.1 --- Frequency Response --- p.24 / Chapter 2.5 --- Common-Mode Feedback Network --- p.26 / Chapter 2.5.1 --- Continuous-Time CMFB Circuit --- p.27 / Chapter 2.5.2 --- Discrete-Time CMFB circuit --- p.33 / Chapter 2.6 --- Design Flow of the Operational Amplifier --- p.35 / Chapter 3 --- Physical Design of the Operational Amplifier --- p.39 / Chapter 3.1 --- Layout Level Design --- p.40 / Chapter 3.2 --- Layout Techniques --- p.42 / Chapter 3.3 --- Input Protection Circuitry --- p.47 / Chapter 4 --- Simulation Results --- p.49 / Chapter 4.1 --- Simulation of the Operational Amplifier --- p.49 / Chapter 4.2 --- Simulation of Auxiliary Amplifiers --- p.57 / Chapter 4.3 --- Simulation of the Common-Mode Feedback Circuit --- p.62 / Chapter 5 --- Measurement Results --- p.70 / Chapter 5.1 --- Transient Response Measurement --- p.70 / Chapter 5.2 --- Frequency Response Measurement --- p.74 / Chapter 5.3 --- Power Consumption Measurement --- p.78 / Chapter 5.4 --- Performance Evaluation --- p.81 / Chapter 6 --- Layout Driven Operational Amplifiers Macromodelling --- p.82 / Chapter 6.1 --- Motivations --- p.83 / Chapter 6.2 --- Methodology --- p.84 / Chapter 6.3 --- Macromodelling the operational amplifier --- p.85 / Chapter 6.4 --- Simulation Results --- p.88 / Chapter 6.5 --- Conclusions --- p.92 / Chapter 7 --- Conclusions --- p.93 / Bibliography --- p.95 / A Layout Diagrams and Chip Micrograph --- p.99

Controlling the electronic structure and requisite charge transfer at and across interfaces is a grand challenge of materials science. Despite decades of research and numerous successes in the fields microelectronics and photovoltaics much work remains to be done. In many applications, whether they be in microelectronics, photovoltaics or display technology there is a demand for multiple functions at a single interface. Historically, existent materials were either discarded as an option due to known properties or tested with some application based figure of merit in mind. Following this, the quality of the material and/or the preparation of the surface/interface to which the material would be deposited was optimized. As the microelectronics and photovoltaics industries have matured, continued progress (faster, lower power transistors and more efficient, cheaper, abundant solar cells) will require new materials (possibly not previously existent) that are fundamentally better for their application than their highly optimized existent counter parts. The manifestation of this has been seen in the microelectronics field with introduction of hafnium silicates to replace silica (which had previously been monumentally successful) as the gate dielectrics for the most advanced transistors. Continued progress in efficient, cheap, abundant photovoltaics will require similar advances. Advances will be needed in the area of new abundant absorbers that can be deposited cheaply which result in materials with high efficiencies. In addition, selective contacts capable of extracting charge from efficient absorbers with low ohmic losses and low recombination rates will be needed. Presented here are two approaches to the multifunctional interface problem, first the use of amorphous alloys that open up the accessible composition space of thin films significantly and second the use of bilayers that loosen the requirements of a single film at an interface.

Metal-oxide thin films are used in a wide variety of electronic devices. Although many techniques have been developed to deposit thin films of metal oxides, there is still a need for alternative cost- and energy-effective deposition methods. Deposition of metal oxide thin films from aqueous solutions of all-inorganic metal salts is a viable method that meets these needs. Although many aqueous-deposited metal-oxide thin films have been successfully incorporated into functioning devices, many of the mechanisms that occur as precursors transition to metal oxides are not well understood. The work presented in this dissertation is primarily concerned with examining the processes that occur as metal oxide thin films form from spin-deposited aqueous precursor solutions with a particular focus on the role of H2O in these processes. Chapter I summarizes methods for thin film deposition, and describes the use of aqueous metal salt solutions as viable precursors for the deposition of metal oxide thin films. Chapter II investigates the precursor chemistry, film-formation processes and properties of LaAlO3 thin films deposited from aqueous precursors. This chapter also serves as general guide to the processes that occur as metal-oxide thin films form from spin-deposited aqueous precursors. Chapters III and IV focus on the effects of H2O(g) during spin-deposition of precursor thin films and during the annealing process in which precursors are converted to metal oxides, respectively. The presence of H2O(g) during spin-deposition has a striking effect on the thickness of the resulting thin films and also affects the elemental gradient and density profiles. During annealing, H2O(g) reduces the temperatures at which counterions are expelled and influences the metal-hydroxide framework formation and its condensation to a metal oxide. The data also indicate that H2O(g) enhances diffusion of gaseous byproducts from within the films. Chapter V focuses on precursor concentration and its impact on the thermal evolution of thin films. The processes involved in the conversion of precursors to metal oxide thin films occur at lower temperatures as precursor concentration decreases. Although this is likely in part due to thickness effects, concentration-dependent precursor speciation may also be involved in lowering the temperatures at which films densify. / 2019-02-17

Tang, Xian. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2013. / Includes bibliographical references. / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese.

在過去的十年裡，隨著便攜式通訊，電腦與消費電子市場的快速發展，以及在超大規模積體電路中，越來越多的功能實現被轉移到數字領域中，這些都引起了人們對模數轉換器研究的極大關注。 / 基於過採樣與量化誤差整形技術，ΣΔ模數轉換器對與類比電路中的非理想特性具有很強的容忍度。然而，爲了優化其在功耗，硅片面積與上市時間等方面的性能，ΣΔ模數轉換器的設計需要對眾多實際問題做出折中考慮。本文在不同的設計層次上提出了一些創新，包括算法，架構及電路設計，從而提升其在通訊，語音與傳感等應用領域中的性能指標。 / 本文第一部份提出的新技術主要解決運用於低中頻無線接收器中開關電容型正交帶通ΣΔ模數轉換器的I/Q通道的不匹配問題。這些I/Q通道的不匹配將導致位於臨近信道的鏡像信號，自鏡像信號及量化噪聲混疊至輸入信道，從而降低模數轉換器的動態範圍。為此，本文提出了一種新的動態單元匹配技術與一種雙線性技術來解決上述問題。同時通過在I/Q信道間複用運算放大器，比較器與數模轉換器，芯片的面積得到了大幅的降低。基於以上技術，在0.18微米CMOS工藝上設計實現了開關電容型正交帶通ΣΔ模數轉換器的測試樣片，其鏡像抑制比可達到73dB，這是迄今為止公開發表論文中報告的最高值。 / 在本文的第二部份，我們關注ΣΔ模數轉換器在音頻領域的應用。其對動態範圍與功耗提出的較高要求為級聯型連續時間ΣΔ模數轉換器帶來了機遇。然而，相比于單環型，級聯型連續時間ΣΔ模數轉換器對於電阻-電容時間常數的偏離及有限的運放低頻增益等非理想特性表現得更加敏感，因為這些不理想因素將影響量化噪聲在模擬與數字路徑中的精確抵消。為此，我們提出了使用脈寬調製技術來對片上的電阻-電容時間常數進行自動調整。基於脈寬調製技術，我們可以使用在離散時間電路中常用的相關雙採樣技術來提高運放的有效低頻增益。同時我們提出了一種有限運放帶寬補償技術來節省芯片的功耗。另外，本文對基於連續時間ΣΔ模數轉換器的脈寬調製技術，相關雙採用技術，反混疊濾波，噪聲與抖動效應等方面均做出了詳盡的仿真與分析。最後我們對一顆基於0.18微米CMOS工藝設計的樣片進行了測試。測試結果表明，採用本文提出的技術可以將ΣΔ模數轉換器的動態範圍提高28dB以上。 / 本文的第三部份展示了一種可用於單端或差分電容傳感器的高精度電容-數字轉換器。在傳統的電容-數字轉換器中，由電容底板開關引入的電荷注入與數字輸出結果及被感知電容的容值有關。當被感知電容的容值變化範圍較大時，這些電荷注入將產生很大的非線性。對此本文提出了一種新的開關控制與校準算法。我們對一顆基於0.18微米CMOS工藝設計的二階電容-數字轉換器樣片進行了測試。測試結果表明，其在0.5毫秒的測試時間內可達到53.2aFrms的精度。同時本文提出的技術可以在0.5pF至3.5pF的較寬電容範圍內，使得電容-數字轉換器在單端電容傳感模式下的線性度（準確度）從9.3位提高至12.3位；在差分電容傳感模式下的線性度（準確度）從10.1位提高至13.3位。最後，本文對連接微機電電容型壓力傳感器和加速度傳感器的實際應用情境進行了測試。 / The rapid growth of the market for portable, battery operated systems for communications, computer and consumer electronics (3C), and the trend of moving functionality to the digital domain in very large scale integration (VLSI) systems have resulted in an enormously increasing interest in analog-to-digital converter (ADC) design. / Combining both oversampling and quantization error shaping techniques, delta sigma (ΔΣ) ADCs achieve a high degree of insensitivity to analog circuit imperfections. Nevertheless, the design of CMOS ΔΣ ADCs involves a number of practical issues and trade-offs that must be taken into account in order to optimize their performance in terms of power consumption, silicon area, and time-to-market deployment. This thesis proposes a number of novel performance-enhancement techniques on different design levels, including algorithm, architecture and circuit level, for ΔΣ ADCs in various application circumstances, such as telecom, audio, sensor, and so on. / First, novel techniques are proposed to mitigate I/Q mismatches in switched-capacitor quadrature bandpass Delta-Sigma modulators (DSMs) used in low-IF wireless receivers. The I/Q mismatches result in a nearby channel at the image frequency, the mirrored image of the desired signal around its center frequency (self-image) and the quantization noise to corrupt the desired signal, degrading the dynamic range of the modulator. A dynamic element matching scheme and a bilinear scheme are the proposed solution to reduce all the above-mentioned I/Q mismatch effects. Furthermore, a multiplexing scheme for the sharing of op-amps, quantizers and DACs between the I and Q channels is investigated for smaller chip area. A prototyping DSM was designed and fabricated in a 0.18 ưm CMOS, measuring an image rejection ratio of 73 dB, being the best reported. / Second, a pulse-width-modulation (PWM) technique is proposed for on-chip automatic RC time constant tuning for cascaded continuous-time (CT) DSMs for audio application. The demand for high signal-to-noise-plus-distortion ratio (SNDR) and low power brings a wealth of opportunities to the CT DSMs. In CT DSMs, cascading low-order stages provides an effective way to achieve stable high-order modulation. However, compared to CT single-loop modulators, CT cascaded modulators are more sensitive to variation of RC time constant and finite dc gain of the opamps as these nonidealities affect the precise cancellation of the quantization noises between the analog and digital paths. In the CT cascaded modulator presented here, we propose to apply a PWM technique for on-chip automatic RC time constant tuning. The application of PWM in turn enables the use of the correlated double sampling (CDS) technique, which is conventionally confined to discrete-time circuits, to boost the effective dc gain. The PWM further allows the use of a finite-opamp-bandwidth compensation technique for power saving. Analysis on PWM tuning, CDS, anti-aliasing filtering, noise and jitter in the CT modulator are presented and verified with extensive simulations. Measurement results on a prototype CT cascaded 2-2 DSM in a 0.18ưm CMOS show that the proposed techniques can improve the dynamic range (DR), SNDR and spurious-free dynamic range (SFDR) of the modulator by at least 28 dB. / Third, a high-precision capacitance-to-digital converter (CDC) is proposed, which can be configured to interface with single-ended or differential capacitive sensors. In the conventional CDC, charge injection from bottom-plate switches depends on the digital output and the value of the sensing capacitor. Nonlinearity is resulted especially when the varying ranging of the sensing capacitor is wide. In this thesis, new switching and calibration schemes are proposed to reduce these charge injection. A prototyping 2nd order CDC employing the proposed techniques is fabricated in a 0.18ưm CMOS process and achieves a 53.2aFrms resolution in a 0.5ms measuring time. The proposed techniques improve the CDC's linearity from 9.3 bits to 12.3 bits in the single-ended sensing mode, and from 10.1 bits to 13.3 bits in the differential sensing mode, with a wide sensing capacitor range from 0.5 to 3.5pF. The CDC is also demonstrated with real-life pressure (single-ended) and acceleration (differential) sensors. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Li, Bing. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2013. / Includes bibliographical references. / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstracts also in Chinese. / Abstracts of thesis entitled: --- p.I / 摘 要 --- p.V / Contents --- p.VII / List of Figures --- p.XI / List of Tables --- p.XVI / Acknowledgement --- p.XVII / Chapter CHAPTER 1. --- Introduction --- p.1 / Chapter 1.1 --- Motivation --- p.1 / Chapter 1.2 --- Original contributions and outline of the thesis --- p.2 / References --- p.1 / Chapter CHAPTER 2. --- A High Image-Rejection SC Quadrature Bandpass DSM for Low-IF Receivers --- p.3 / Chapter 2.1 --- Mismatch in Complex Gain Blocks --- p.6 / Chapter 2.2 --- Mismatches in QBDSM --- p.8 / Chapter 2.3 --- Proposed High Image-Rejection QBDSM --- p.13 / Chapter 2.3.1 --- Technique to remove I/Q mismatches in the first complex resonator (for P1 in Fig. 2.6) --- p.13 / Chapter 2.3.2 --- Technique to remove I/Q mismatches in the Feedback DAC (for B in Fig. 2.6) --- p.19 / Chapter 2.3.3 --- Technique to remove I/Q mismatches in the Input Coefficient (for A1 in Fig. 2.6) --- p.20 / Chapter 2.3.4 --- Summary and Simulation Results --- p.27 / Chapter 2.4 --- I/Q Multiplexing Schemes and Circuit Implementation of the QBDSM --- p.34 / Chapter 2.5 --- Measurement Results Analysis --- p.40 / Chapter 2.6 --- Conclusions --- p.47 / Chapter APPENDIX I: --- I/Q MISMATCHES IN LOW-IF RECEIVERS --- p.48 / Chapter A. --- I/Q Mismatch in Mixer --- p.48 / Chapter B. --- I/Q Mismatch in Polyphase Filter --- p.49 / Chapter C. --- I/Q Mismatch in QBDSM --- p.50 / Chapter D. --- I/Q Imbalance Analysis for whole receiver --- p.51 / Chapter APPENDIX II: --- IRR Measurement Method --- p.52 / References --- p.56 / Chapter CHAPTER 3. --- A Continuous-time Cascaded Delta-Sigma Modulator with PWM-Based Automatic RC Time Constant Tuning and Correlated Double Sampling --- p.59 / Chapter 3.1 --- PWM for on-chip RC Time Constant Tuning --- p.61 / Chapter 3.1.1 --- Integrator Gain Error --- p.64 / Chapter 3.1.2 --- Automatic Generation of PWM Clock --- p.65 / Chapter 3.1.3 --- Modulator Architecture --- p.66 / Chapter 3.1.4 --- Anti-aliasing Filtering --- p.68 / Chapter 3.1.5 --- Noise Analysis --- p.69 / Chapter 3.2 --- Proposed SRMC Integrator with CDS --- p.71 / Chapter 3.2.1 --- Analysis on the opamp gain enhancement --- p.73 / Chapter 3.2.2 --- Simulation Results --- p.75 / Chapter 3.3 --- Compensation for Finite-Opamp-Bandwidth-Induced Error --- p.76 / Chapter 3.3.1 --- Compensation for fininte opamp bandwidth --- p.77 / Chapter 3.3.2 --- Behavorial Simulation Results --- p.79 / Chapter 3.4 --- Jitter Analysis --- p.80 / Chapter 3.4.1 --- Jitter on Rising Edges --- p.81 / Chapter 3.4.2 --- Duty cycle jitter --- p.84 / Chapter 3.5 --- Prototyping Modulator Design --- p.85 / Chapter 3.6 --- Measurement Results --- p.89 / Chapter 3.7 --- Summary --- p.95 / References --- p.97 / Chapter CHAPTER 4. --- A High-Linearity Capacitance to Digital Converter with Techniques Suppressing Charge Injection from Bottom-Plate Switches --- p.105 / Chapter 4.1 --- Introduction --- p.105 / Chapter 4.2 --- Proposed CDC Switching and Calibration Schemes --- p.107 / Chapter 4.2.1 --- Single-Ended Sensing Mode --- p.107 / Chapter 4.2.2 --- Differential Sensing Mode --- p.111 / Chapter 4.3 --- Circuit Implementation --- p.114 / Chapter 4.4 --- Measurement Results --- p.117 / Chapter 4.5 --- Conclusion --- p.125 / Chapter APPENDIX: The cross section of NPN transistor in triple-well CMOS process --- p.126 / References --- p.127 / Chapter CHAPTER 5. --- Conclusions and future works --- p.129 / Chapter 5.1 --- Conclusions --- p.129 / Chapter 5.2 --- Future works --- p.130 / Chapter APPENDIX: --- A typical CMOS fabrication process flow (1 poly/2 M, twin well CMOS) --- p.131

With the number of transistors integrated into a single integrated circuit (IC) crossing the one-billion mark and complementary metal-oxide-semiconductor (CMOS) technology scaling pushing device dimensions ever-so-close to atomic scales, variability in transistor performance is becoming the dominant constraint in modern-day CMOS IC design. Developing novel approaches for device characterization, which allow a detailed study of electrical transistor characteristics across large statistical sample sets, is crucial for the proper identification, characterization, and modeling of different physical sources of device variability. On-chip characterization methodologies have the potential to address all of these issues by enabling the characterization of large statistical device sample sets, while also allowing for high measurement quality and throughput. In this work, a fully-integrated system for on-chip combined capacitance-voltage (C-V) and current-voltage (I-V) characterization of a large integrated test transistor array implemented in a 45-nm bulk CMOS process is presented. On-chip I-V characterization is implemented using a four-point Kelvin measurement technique with 12-bit sub-10 nA current measurement resolution, 10-bit sub-1 mV voltage measurement resolution, and sampling speeds on the order of 100 kHz. C-V characterization is performed using a novel leakage- and parasitics-insensitive charge-based capacitance measurement (CBCM) technique with atto-Farad resolution. The on-chip system is employed in developing a comprehensive CMOS transistor variability characterization methodology, studying both random and systematic sources of quasi-static device variability. For the first time, combined C-V/I-V characterization of circuit-representative devices is demonstrated and used to extract variations in the under- lying physical parameters of the device. Additionally, the fast current sampling capabilities of the system are used for the characterization of random telegraph noise (RTN) in small area devices. An automated methodology for the extraction of RTN parameters is developed, and the statistics of RTN are studied across device type, bias, and geometry.