Que son intérêt soit environnemental ou économique, qu’elle s’applique aux macro, micro ou nano systèmes,la récupération d’énergie est une solution permettant de s’affranchir du remplacement, de la recharge ou même de l’utilisation de piles. Cette thèse s’inscrit dans le cadre d’une collaboration entre Oxylane (Decathlon) etle CEA et son objectif est la conception d’un circuit électronique de gestion permettant de récupérer l’énergie mécanique humaine pendant une pratique sportive afin d’alimenter un capteur communicant sans fil. Le système électronique développé dans ce travail exploite l’énergie électrique issue de récupérateurs piézoélectriques,l’extrait et la met en forme grâce à une technique d’extraction efficace et un circuit de puissance approprié.Face au comportement aléatoire de l’être humain fournissant une énergie mécanique intermittente et irrégulière,la topologie Flyback et la technique d’extraction SECE ("Synchronous Electric Charge Extraction") sont utilisés. Le récupérateur est déchargé à son maximum de tension par l’intermédiaire d’une inductance couplée et de deux transistors MOSFETs commandés. Ce travail propose une nouvelle variante de SECE : la technique MS-SECE ("Multi-Shot Synchronous Electric Charge Extraction") permet de transférer l’énergie en plusieurs paquets afin de diminuer les pertes résistives ou le volume du circuit magnétique. Afin de satisfaire la contrainte d’encombrement de l’application visée par Oxylane, un circuit de récupération implémentant cette nouvelle technique est fabriqué en technologie intégrée CMOS 0,35 μm. L’ASIC possède une consommation très faible(1 μW) et commande le circuit de puissance et quelques composants discrets. De cette façon, l’énergie électrique est convertie efficacement vers une capacité réservoir sous 3V. De plus, grâce à ses deux modes de fonctionnement("passif non-optimisé" et "actif optimisé") utilisés successivement, le circuit démarre sans énergie initiale et fonctionne sans batterie rechargeable. Le système final est compatible avec une grande variété de récupérateur piézoélectriques, notamment lorsque leur tension de sortie est élevée (>50V), et permet l’autonomie en énergie d’un capteur communicant sans fil consommant environ 100 μW. / No matter what its purpose is, economic or environmental, energy harvesting is a relevant solution to replaceor to get rid of primary batteries. This thesis is part of a collaborative laboratory between the CEA and Oxylane(Decathlon) and its aim is the design of a power management circuit which harvests mechanical energy fromhuman movements during sport practice in order to power aWireless Sensor Node (WSN). The electronic circuitwhich has been developed in this work recovers energy from piezoelectric harvesters, extracts and conditionsit thanks to an efficient energy extraction technique and to an appropriate power circuit. In response to therandom behavior of human body which supplies an intermittent and irregular energy, the Flyback topology andthe Synchronous Electric Charge Extraction technique (SECE) are employed. The energy harvester is dischargedat its maximum voltage through a coupled-inductor and two MOSFETs transistors. This work proposes a newextraction technique, derived from SECE : MS-SECE ("Multi-Shot Synchronous Electric Charge Extraction")transfers the energy in several magnetic discharges which decreases the resistive losses or the size of the magneticcomponent. In order to satisfy the size constraints aimed by Oxylane, an integrated circuit, fabricated in theAMS 0,35 μm CMOS technology, implements the MS-SECE autonomously. This very low power (1 μW) ASICcontrols the power circuit and a couple of external components. This way, the electrical energy is efficientlyconverted towards a buffer capacitor under 3V. Furthermore, thanks to its two operating modes (passive/nonoptimizedand active/optimized) successively employed, the circuit self-starts and works without battery orinitial energy. The complete system is compatible with a large variety of piezoelectric harvesters, especiallywhen their output voltages are large (>50V). Finally, it enables the complete autonomy of a WSN consumingaround 100 μW.

Delamination and cracks within the multilayer structure are typical failure modes observed in microelectronic and micro electro mechanical system (MEMS) devices and packages. As destructive detection methods consume large numbers of devices during reliability tests, non-destructive techniques (NDT) are critical for measuring the size and position of internal defects throughout such tests. There are several established NDT methods; however, some of them have significant disadvantages for detecting defects within multilayer structures such as those found in MEMS devices. This thesis presents research into the application of transient infrared thermography as a non-destructive method for detecting and measuring internal defects, such as delamination and cracks, in the multilayer structure of MEMS devices. This technique works through the use of an infrared imaging system to map the changing temperature distribution over the surface of a target object following a sudden change in the boundary conditions, such as the application of a heat source to an external surface. It has previously been utilised in various applications, such as damage assessment in aerospace composites and verification of printed circuit board solder joint manufacture, but little research of its applicability to MEMS structures has previously been reported. In this work, the thermal behaviour of a multilayer structure containing defects was first numerically analysed. A multilayer structure was then successfully modelled using COMSOL finite element analysis (FEA) software with pulse heating on the bottom surface and observing the resulting time varying temperature distribution on the top. The optimum detecting conditions such as the pulse heating energy, pulse duration and heating method were determined and applied in the simulation. The influences of thermal properties of materials, physical dimensions of film, substrate and defect and other factors that will influence the surface temperature gradients were analytically evaluated. Furthermore, a functional relationship between the defect size and the resulting surface temperature was obtained to improve the accuracy of estimating the physical dimensions and location of the internal defect in detection. Corresponding experiments on specimens containing artificially created defects in macro-scale revealed the ability of the thermographic method to detect the internal defect. The precision of the established model was confirmed by contrasting the experimental results and numerical simulations.

The PhD thesis focuses on the always-on low power SRAM memories (essentially low dynamic power) in thin CMOS technology node CMOS 32nm and beyond. It reviews the state of the art of the eSRAM and describes different techniques to reduce the static and dynamic power consumption with respect the variability issue. Main techniques of power reduction are reviewed with their contributions and their limitations. It presents also a discussion about a statistical variability modeling and the variability effects on the yield. An original low power architecture based on 5T-Portless bit-cell is presented, with current mode read/write operations, as an ideal candidate for the always-on SRAM memories. A test chip implementation in CMOS 32nm of the 5T-Porless is designed and a comparison with an existing 6T SRAM memory is presented based on simulation. Some test chip functionality results and power consumption are performed. Finally the conclusion highlights the major contributions of the study and discusses the various simplification assumptions to see possible limitations. It is concluded affirmatively about industrial interest of the 5T-Portless SRAM for always-on embedded applications. Perspectives concern the analytical modeling for statistical behavior of SRAM as the Monte-Carlo approach is no more practicable. The migration of the 5T-Portless SRAM may be already considered in advanced nodes.

De plus en plus d'applications spécifiques embarquées exigent de larges blocs de mémoires statiques SRAM. En particulier il y a un besoin de mémoires inconditionnellement actives pour lesquelles la consommation d'énergie est un paramètre clé. Par exemple les réseaux sans fil hétérogènes sont caractérisés par plusieurs interfaces tournées vers des réseaux différents, donc de multiples adresses IP simultanées. Une grande quantité de mémoire est mobilisée et pose un sérieux problème de consommation d'énergie vis-à-vis de l'autonomie de système mobile. La stratégie classique d'extinction des blocs mémoire momentanément non opérationnelle ne permet qu'une réduction faible en consommation et limite les performances dynamiques du système. Il y a donc un réel besoin pour une mémoire toujours opérationnelle avec un très faible bilan énergétique. Par ailleurs les technologies CMOS avancées posent le problème de la variabilité et la conception de mémoire SRAM doit aboutir à un niveau de fiabilité très grand. La thèse discute les verrous techniques et industriels concernant la mémoire embarquée SRAM très faible consommation. Le cas de la mémoire toujours opérationnelle représente un défi pertinent. Un état de l'art balaie les architectures SRAM avec plusieurs points de vue. Une discussion à propos de la modélisation analytique statistique comme moyen de simplification de la conception en 32nm a été développée. Une cellule alternative aux 6T, 7T et 8T, laquelle est appelée 5T-Portless présente des avantages et des performances qui repose sur son fonctionnement en mode courant à l'origine de la réduction significative de la consommation dynamique ajoutée à une cellule intrinsèquement peu fruiteuse. Un démonstrateur de 64kb (1024x64b) en CMOS32nm a été réalisé, les résultats de mesure confirment l'intérêt industriel de cette mémoire. / The PhD thesis focuses on the always-on low power SRAM memories (essentially low dynamic power) in thin CMOS technology node CMOS 32nm and beyond. It reviews the state of the art of the eSRAM and describes different techniques to reduce the static and dynamic power consumption with respect the variability issue. Main techniques of power reduction are reviewed with their contributions and their limitations. It presents also a discussion about a statistical variability modeling and the variability effects on the yield. An original low power architecture based on 5T-Portless bit-cell is presented, with current mode read/write operations, as an ideal candidate for the always-on SRAM memories. A test chip implementation in CMOS 32nm of the 5T-Porless is designed and a comparison with an existing 6T SRAM memory is presented based on simulation. Some test chip functionality results and power consumption are performed. Finally the conclusion highlights the major contributions of the study and discusses the various simplification assumptions to see possible limitations. It is concluded affirmatively about industrial interest of the 5T-Portless SRAM for always-on embedded applications. Perspectives concern the analytical modeling for statistical behavior of SRAM as the Monte-Carlo approach is no more practicable. The migration of the 5T-Portless SRAM may be already considered in advanced nodes.