[pt] Este trabalho descreve a modelagem e simulação em tempo de um microcomputador destinado a controlo de processos industriais. O objetivo desejado foi obter dados que permitissem a depuração lógica da arquitetura e projeto lógico considerando a interação temporal entre os sinais do microcomputador. O nível de detalhe observado no desenvolvimento do modelo foi de sistema no que se refere a pastilhas em LSI e de porta lógica quando pastilhas CI foram utilizadas. O programa simulador foi implementado na linguagem SIMSCRIPT II. O simulador será utilizado para desenvolvimento de programas de suporte e microprogramação. / [en] The modelling and simulation of a microcomputer oriented to control of industrial processes is described. The purpose is twofold: first, to permit debugging of the desired microcomputer´s architecture and logic desing, and secondly, to aid in the development of the microprograms to be used with the actual microcomputer. The system model contains assumed LSI and IC chips which are in turn simulated with the aid of the digital computer language SIMSCRIPT II. The LSI´s are simulated at the system level, while the IC´s are simulated down to the gate level.

A power distribution design engineering workstation is used as the basis for a restoration management system. The complete system contains three separate programs. The three programs are the Telephone Operator program, the additions to the design workstation, and the statistical collection program. The use of graphical interaction as a method of improving the restoration process will be presented. A method of contextual based editing is presented as an aid to the workstation based program. Records of the outages are kept by the system. The outage records are used to create statistical tables for the representation of each set of stored data. / Master of Science

The Altair 680b Cross-Assembler is a program written in the Nova Assembly Language. It can be used to assemble Altair 680b assembly language programs. The object code can be punched on paper-tape for execution on the Altair 680b microcomputer. This report describes the design and working of the Cross-Assembler. A program listing and a few sample runs are also included. / Thesis / Master of Science (MSc)

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SoCs (System on Chips) are complex designs with heterogeneous modules (CPU, memory, etc.) integrated in them. Verification is one of the important stages in designing an SoC. Verification is the process of checking if the transformation from architectural specification to design implementation is correct. Verification involves creating the following components: (i) a testplan that identifies the conditions to be verified, (ii) a testcase that generates the stimuli to verify the conditions identified, and (iii) a test-bench that applies the stimuli and monitors the output from the design. Verification consumes upto 70% of the total design time. This is largely due to the complex and manual nature of the verification task. To reduce the time spent in verifying the design, the components used for verification can be generated automatically or created at an abstract level (to reduce the complexity) and reused. In this work we present a methodology to synthesize testcases from reusable code segments and abstract specifications. Our methodology consists of the following major steps: (i) identifying the structure of testcases, (ii) identifying code segments of testcases that can be reused from one SoC to another, (iii) identifying properties of an SoC and its modules that can be used to synthesize the SoC specific code segments of the testcase, and (iv) proposing a synthesizer that uses the code segments, the properties and the abstract specification to synthesize testcases. We discuss two specific classes of testcases. These are testcases for verifying the memory modules and the testcases for verifying the data transfer modules. These are considered since they form a significantly large subset of the device functionality. We implement a prototype testcase generator and also present an example to illustrate the use of methodology for each of these classes. The use of our methodology enables (i) the creation of testcases automatically that are correct by construction and (ii) reuse of the testcase code segments from one SoC to another. Some of the properties (of the modules and the SoC) presented in our work can be easily made part of the architectural specification, and hence, can further reduce the effort needed to create them.