Integrated Circuit (IC) designs are increasingly moving towards Intellectual Property (IP) reuse for various targeted products and market segments. Therefore, there is a need to share and synergize internal bus architectures to enable the reuse of IP blocks for various ASIC and SoC applications. Due to the different market segments of various ASICs and SoCs, design teams and architects have opted to use customized internal bus architectures to suit the respective targeted features for their market segments. As a result, many ASIC and SoC companies that produce microprocessors for computers, microcontrollers for consumer electronics as well as memory and I/O controller chipsets have opted to use different internal interfaces, designs and IPs for the different products that they sell. A modular and configurable bus architecture that is flexible and capable of supporting IPs from various ASICs and SoCs would serve to solve many of the problems relating to IP reuse for various applications from a front end design perspective. There are several approaches to resolve this, for example, using a standard existing open source bus, a new all-encompassing bus that covers the needs of the majority of designs and a customization of a particular bus level such as the interface layer, where part of the bus features are fixed and the rest of them are determined by individual design groups. This research covers the analysis of existing bus architectures in industry and considers the various options for bus architecture optimization for design modularity, bus performance and IP reuse with existing technology. The architecture definition, design, logic simulation and performance comparisons of the proposed bus architecture on industry standard RTL design and validation tools was then conducted.

A preliminary system design and human factors analysis of a home computer workstation has been presented. Systems are proposed for families modifying existing furniture, as well as those purchasing new workstations. The systems are designed to meet standard human factors criteria to minimize potential injuries and discomfort. In both cases, the design assures enough flexibility to suit all members of the family. Environmental factors such as noise and light are discussed, as well as personal preference, safety, and budget. A description of the workspace requirements, the human factors criteria, and the cost analysis included. / Master of Science

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An Apple microcomputer and a three axis milling machine are the basis for a CAD/CAM system with the capability of drilling and contour milling operations. The milling machine axes are driven by three stepper motors under the control of the Apple microcomputer and the ISAAC data acquisition module. An interactive part design program using high resolution color graphics has been developed. It employs lines, circles and points to define the geometry for the part. The design is entered at the CRT and stored as a CAM database on the user disc. Once the design is complete it is postprocessed and the milling machine and the Apple are connected through the ISAAC module. The raw part is set up on the mill and control of contouring is by the Apple microcomputer. The software has been designed to operate very similar to the EZCAM interactive part design software available on the Bridgeport CNC Mark II Series milling machine. It has been developed using Applesoft BASIC language and the 6502 Assembly language.

The combination of artificial intelligence and robotics led to more flexibility and powerful mobile robot applications. The robot and its environment were simulated with a microcomputer to gather statistical information. An application was demonstrated in the laboratory with a mobile robot. The robot recognized an obstacle in its path and generated the necessary changes in its environment so that it could successfully complete a required task.

The rapid proliferation of microprocessor based products has increased the need of Microcomputer Development Systems. The IBM PC's software architecture is modified to make it an Intel Series III compatible development system. Universal development interface (UDI) is used to allow all Intel languages and object modules to execute on the IBM PC. The development languages available are the 8086/8088 assembly language, with F0RTRAN-86 and Pascal-86 as the high level languages. The exact working and operating procedures of the software development tools, like an assembler, compiler, linker, locater, hex to object converter and a debugger are explained in detail. Mathematical support is either through an 8087 or its emulator. Detailed explanation of high level language program execution is given, including the run time support needed. A serial loader program is also available to downline load programs from the IBM PC development system to other target machines, like the SDK-86 single board computer. / M.S.

Sports organizations, like other businesses, have a need to ingest data and therefrom to produce serviceable information for purposes of communications and decision making. However, sports personnel and general business personnel typically differ in educational background and computer experience, the sports person often unaware of the advantages offered by computers. Consequently, this thesis's purpose is to: l. Introduce sports organizations to the potential usefulness of small computer systems, 2. Present a definitional review of basic small computer hardware components and software concepts, 3. Provide a methodical procedure for planning and selecting a computer system appropriate for the organization's data processing requirements, and 4. Illustrate, via case study, use of the proposed methodology in an actual organized sports environment. / Master of Science

This thesis presents methodologies for the operation of a programming/documentation system for a Texas Instruments Model 530 programmable controller. The methodologies include: 1) a means to store information about the structure of a ladder diagram and display the ladder diagram on a CRT screen, 2) a means to convert the ladder diagram information into its equivalent Boolean code, and 3) a means to convert Boolean code into its equivalent ladder diagram information. / Master of Science