The thesis deals with the design and realization of electronic security system (ESS) for the house. ESS evaluates signals from radar move-detection sensors also allows connection of other types of move-detection, magnetic contacts, laser gates and smoke detector. The interruption is signaled via SMS sent to the owner of the building and via acoustic warning. The security system also allows the connection temperature sensors, as well as monitoring electricity consumption or central control home appliances and other devices. These features are optional, they can be used to remotely monitor the status of the object respectively its management even via SMS.

This project deals with the design of an autonomous microprocessor controlled testing unit for automatic controlling the output of the tested device, depending on the excitation of its inputs. There are possible realizations of testing unit hardware functional blocks described. Possible options are objectively analyzed in accord with the project specification and with regard to the mutual compatibility of individual blocks, availability, price and desired functionality. The most appropriate selected solution is implemented using the specific circuit elements. The output of the project is realized functional testing unit and elaborated product documentation. There was control software for the microprocessor of the unit written. The software implements an interpreter for the test algorithm execution, carries out the test evaluation and stores a record of the test process to the file. There was also the utility for a PC, which allows uploading tests to the testing unit via USB created.

This thesis is focused on design and prototyping of solar panel position control system for an obtaining of the maxima renewable energy from sun. In this thesis, various ways of solar panel positioning are considered and analyzed. Consequently, a construction arrangement of the positioner is presented. It is mechanically adapted to obtain the maximum efficiency in typical environment corresponding with the Central European geographical latitude. Different methods of sun monitoring are considered and analyzed. On the basis of this analysis, a proper prototype of sun monitor for exact positioning with disturbance filtering has been constructed. Following part of work is devoted to stable, fully automated, control subsystem for reliable functionality of solar system. A suitable microprocessor with a robust firmware has been implemented to this control unit. Finally, system parameters measurement and closing analysis of gained renewable energy and backflow computation is presented in the end of this diploma thesis.

The first part of the work was dealing in general with switched power supply and types of battery chargers. The second part is made by my own design of microprocessor driven battery charger. The design is based on datasheets and recommended circuit connection. The electrical scheme and also the printed circuit board was designed in Eagle 5.11.0 design system. The battery charger is capable of charging these types of batteries: lead acid, NiMH, NiCd, LiPol a alkaline accumulators, and the maximal output current from charger is 3A. The software implementation and design are also part of this master‘s thesis.

The thesis deals with the design and realization of electronic security system (ESS) for the house. ESS evaluates signals from radar move-detection sensors also allows connection of other types of move-detection, magnetic contacts, laser gates and smoke detector. The interruption is signaled via SMS sent to the owner of the building and via acoustic warning. The security system also allows the connection temperature sensors, as well as monitoring electricity consumption or central control home appliances and other devices. These features are optional, they can be used to remotely monitor the status of the object respectively its management even via SMS.

This master´s thesis is dealing with the theory of Li-ion accumulators and theirs charching. In this thesis has been designed accumulator tester for automatic charging and discharging of Li-ion accumulator. This tester is controlled by microprocessor.

The main purpose of this project is to design and implement a system for controlling targets on a shooting range. This consists of the main control unit and some motor-turning targets. Both control unit and targets are battery powered and use wireless data transfer. This work describes the selection of the proper platform for wireless communication and design of the hardware and software part of the system in relation to low price and high reliability of the equipment. The conclusion of this work should be the system for practical use.

The major objective of this thesis was to investigate how the use of a recently developed microprocessor-controlled limb system altered the negative mechanical work done by the intact and prosthetic limb when trans-femoral amputees terminated gait. Participants terminated gait on a level surface from their self-selected walking speed and on declined surface from slow and customary speeds, using limb system prosthesis with microprocessor active or inactive. Limb negative work, determined as the integral of the negative mechanical (external) limb power during the braking phase, was compared across surface, speed and microprocessor conditions. Halting gait was achieved predominantly from negative work done by the trailing/intact. Trailing versus leading limb mechanical work imbalance was similar to how able body individuals halted gait. Importantly, the negative limb work performed on the prosthetic side when terminating gait on declined surface was increased when the microprocessor was active for both slow and customary speeds (no difference on level surface) but no change on intact limb. This indicates the limb system’s ‘ramp-descent mode’ effectively/dynamically altered the hydraulic resistances at the respective joints with evidence indicating changes at the ankle were the key factor for increasing the prosthetic limb negative work contribution. Findings suggest that trans-femoral amputees became more assured using their prosthetic limb to arrest body centre of mass velocity when the limb system’s microprocessor was active. More generally findings suggest, trans-femoral amputees should obtain clinically significant biomechanical benefits from using a limb system prosthesis for locomotion involving adapting to their everyday walking where adaptations to an endlessly changing environment are required. / Higher Committee of Education Development in IRAQ (HCED)

The future voltage regulator module (VRM) challenges of high bandwidth control with fast transient response, high current output, simple implementation, and efficient 48V solution are tackled in this dissertation. With the push for control bandwidth to meet design specifications for microprocessor VRM with larger and faster load transients, control can be saturated and lost for a significant period of time during transient. During this time, undesirable transient responses such as large undershoot and ringback occurs. Due to the loss of control, the existing tools to study the dynamic behavior of the system, such as small signal model, are insufficient to analyze the behavior of the system during this time. In order to have a better understanding of the system dynamic performance, the operation the VRM is analyzed in the state-plane for a clear visual understanding of the steady-state and transient behaviors. Using the state-plane, a simplified state-plane trajectory control is proposed for constant on-time (COT) control to achieve the best transient possible for applications with adaptive voltage positioning (AVP). When the COT control is lost during a load step-up transient, the state-plane trajectory control will extend on-time to provide the a near optimal transient response. By observing the COT control law in the state-plane, a simplified state-plane trajectory control with analog implementation is proposed to achieve the best transient possible with smooth transitions in and out of the steady-state COT control. The concept of the simplified state-plane trajectory control is then extended to multiphase COT. For multiphase operation, additional operating behavior, such as phase overlapping during transient and interleaving during steady-state, need to be taken into consideration to design the desired state-plane trajectory control. A simple state-plane trajectory control with improved Ton extension is proposed and verified using multiphase COT control. After tackling the state-plane trajectory control for current mode COT, the idea is then extended to V2 COT. V2 COT is a more advanced current mode control which requires a more advanced state-plane trajectory control to COT. By calculating the intersection of the extended on-stage trajectory during transient and the ideal off trajectory in the form of a current limiting wall, a near optimal transient response can be achieved. For V2 COT with state-plane trajectory control, implementations using inductor vs. capacitor current, effect of component tolerance, and effect of IC delay are studied. The proposed state-plane trajectory control is then extended to enhanced V2 COT. Aside from tackling existing VRM challenges, the future datacenter 48V VRM challenge of a high efficiency, high power density solution to meet the VRM specifications is studied. The sigma converter is proposed for the 48V VRM solution due to exhibition of high efficiency and high-power density from hardware evaluation. An accurate model for the sigma converter is derived using the new modeling approach of modularizing the small signal components. Using the proposed model, the sigma converter is shown to naturally have very low output impedance, making the sigma converter suitable for microprocessor applications. The sigma converter is designed and optimized to achieve AVP and very fast transient response using both voltage-mode and current-mode controls. / Doctor of Philosophy / Microprocessors, such as central processing unit (CPU) and graphics processing unit (GPU) are the basis of today's electronics. In the recent decades, the demand for more powerful and faster data processing lead to a significant increase in power consumption by these microprocessors. Even with the introduction of multi-core processors and adaptive voltage positioning (AVP) to reduce the average power provided by the power supplies, the microprocessor can still draw a large amount of instantaneous power in a short period of time. With the microprocessors demanding high amount of current at fast slew-rate, the challenges for the next generation of microprocessor power supply, or voltage regulator modules (VRM), are fast response speed to ensure proper operation of the microprocessors, and high efficiency VRM to minimize the overall system power consumption. The challenge of a VRM with fast response speed is tackled first. To meet the AVP and transient requirements of microprocessor, the VR need to utilize high-bandwidth control methods. Of the control methods used by the industry, high control bandwidth can be easily achieved using constant on-time (COT) control. With the ever-increasing output current level and transient slew-rate requirements, COT control can saturate and lose its steady-state control for a period of time during load step-up transient. During this time, the system will operate with a fixed frequency control until COT control is recovered. Although the method is widely used in the industry, the method is too slow to meet the transient requirements. Many state-of-art methods have been proposed to resolve the load step-up transient issue of COT. However, of the methods proposed, it is difficult to optimize the transient improvement while having a simple analog implementation to ensure a fast response for the wide operating range and aggressive transient conditions observed in microprocessor VRM application. In this dissertation, COT control is studied using the state-plane to provide a clear visual understanding of the transient behavior of the control. Using the state-plane, a state-plane trajectory control is proposed to achieve near optimal load step-up transient response. The concept is then extended to multiphase VRM, which is typically used for high current applications. The state-plane trajectory control concept is then further extended to V2 COT control for VRM without AVP, such as those used by GPU and smartphone CPU. For the proposed state-plane trajectory controls, hardware implementation, evaluation, and experimental results are provided. After tackling the challenge of a VRM with fast response speed, the challenge of an efficient VRM is then tackled. In recent years, a significant amount of research has been put into studying VRM for a power delivery architecture which uses a 48V bus instead of the 12V bus. By using the 48V bus, less redundancy in the power delivery path can greatly increase the overall system efficiency if the VRM stage retains its efficiency. However, the increase in input voltage for the VRM provides an additional challenge to maintain high efficiency for the VRM stage itself. To maintain good efficiency, it is difficult to increase converter switching frequency beyond 300kHz. This limitation on switching frequency will limit the ability to achieve high bandwidth design and fast transient requirements. A 48V VRM using a different topology, the sigma converter, has demonstrated high-efficiency and high-power density, but the converter behavior and control methodology for VRM application is unclear. In this dissertation, the modeling and control of the sigma converter are studied using the proposed small-signal model. By evaluating the proposed small-signal model, the sigma converter can naturally have very low output impedance, making it an ideal candidate for 48V VRM. Then, the design guideline of the sigma converter with current-mode control is provided. With the work discussed in this dissertation, further study of the sigma converter with COT and state-plane trajectory control can be conducted in the future.

Compte tenu de la complexité des circuits intégrés de nos jours et des nœuds technologiques qui ne cessent pas de diminuer, être au rendez-vous avec les demandes de design, test et fabrication des dispositifs de haute qualité est devenu un des plus grands défis. Avoir des circuits intégrés de plus en plus performants devrait être atteint tout en respectant les contraintes de basse consommation, de niveaux de fiabilité demandés, de taux de défauts acceptables ainsi que du bas coût. Avec ce fascinant progrès de l’industrie des semi-conducteurs, les processus de fabrication sont devenus de plus en plus difficile à contrôler, ce qui rend les puces électroniques de nos jours plus disposés aux défauts physiques. Le test était et restera l’unique solution pour lutter contre l’occurrence des défauts de fabrication ; même il est devenu un facteur prédominant dans le coût totale de fabrication des circuits intégrés. Même si des solutions de test, qui existent déjà, étaient capables de satisfaire ce fameux compromis coût-qualité ces dernières années, il arrive d’observer encore des mécanismes de défauts malheureusement incontrôlables. Certains sont intrinsèquement reliés au processus de fabrication en lui-même. D’autres reviennent sans doute aux pratiques de test et surtout quand on analyse le taux de défauts détectés et le niveau de fiabilité atteint.L’objectif principal de cette thèse est d’implémenter des stratégies de test robustes et efficaces qui répondent aux lacunes des techniques de tests classiques et qui proposent des modèles de fautes plus réalistes et répondent au mieux aux attentes des fournisseurs. Dans l’objectif d’améliorer l’efficacité de test en termes de coût, capacité de couverture de faute, nous présentons divers contributions significatives qui touchent différents domaines entre-autres le test sur le terrain, les tests à hautes fréquences sous contraintes de puissance et finalement le test des chaines de scan.La partie majeure de cette thèse était consacrée pour le développement de nouvelles techniques de tests fonctionnels ciblant les systèmes à processeurs.Les méthodologies appliquées couvrent les problèmes de test sur terrain aussi bien que les problèmes de test de fabrication. Dans le premier cas, la techniques adoptée consiste à fusionner et compacter un ensemble initial de programmes fonctionnels afin d’atteindre une couverture de faute satisfaisante tout en respectant les contraintes du test sur terrain (temps de test réduit et ressource mémoire limitée). Cependant dans le deuxième cas, comme nous avons assez d’informations sur la structure du design, nous proposons un nouveau protocole de test qui va exploiter l’architecture de test existante. Dans ce contexte, nous avons validé et confirmé la relation complémentaire qui joint le test fonctionnel avec le test structurel. D’autres part, cette prometteuse approche assure un test qui respecte les limites de la consommation fonctionnelle et donc une fiabilité meilleure.La dernière contribution de cette thèse accorde toute l’attention à l’amélioration de test de la structure DFT « Design For Test » la plus utilisée qui est la chaîne de scan. Nous présentons dans cette contribution une approche de test qui cible les défauts physiques au sein de la cellule en elle-même.Cette approche représente une couverture de défauts meilleure et une longueur de test plus réduit si nous la comparons avec l’ATPG classique ciblant les mêmes défauts « Intra-cell defect ATPG ».Comme résultat majeur de cette efficace solution de test, nous avons observé une amélioration de 7.22% de couverture de défaut accompagné d’une réduction de 33.5% du temps de test en comparaison avec la couverture et le temps du test atteints par le « Cell-awer ATPG ». / In light of the aggressive scaling and increasing complexity of digital circuits, meeting the demands for designing, testing and fabricating high quality devices is extremely challenging.Higher performance of integrated circuits needs to be achieved while respecting the constraints of low power consumption, required reliability levels, acceptable defect rates and low cost. With these advances in the SC industry, the manufacturing process are becoming more and more difficult to control, making chips more prone to defects.Test was and still is the unique solution to cover manufacturing defects; it is becoming a dominant factor in overall manufacturing cost.Even if existing test solutions were able to satisfy the cost-reliability trade-off in the last decade, there are still uncontrolled failure mechanisms. Some of them are intrinsically related to the manufacturing process and some others belong to the test practices especially when we consider the amount of detected defects and achieved reliability.The main goal of this thesis is to implement robust and effective test strategies to complement the existing test techniques and cope with the issues of test practices and fault models. With the objective to further improve the test efficiency in terms of cost and fault coverage capability, we present significant contributions in the diverse areas of in-field test, power-aware at-speed test and finally scan-chain testing.A big part of this thesis was devoted to develop new functional test techniques for processor-based systems. The applied methodologies cover both in-field and end-of manufacturing test issues. In the farmer, the implemented test technique is based on merging and compacting an initial functional program set in order to achieve higher fault coverage while reducing the test time and the memory occupation. However in the latter, since we already have the structure information of the design, we propose to develop a new test scheme by exploiting the existing scan chain. In this case we validate the complementary relationship between functional and structural testing while avoiding over as well under-testing issues.The last contribution of this thesis deals with the test improvement of the most used DFT structure that is the scan chain. We present in this contribution an intra-cell aware testing approach showing higher intra-cell defect coverage and lower test length when compared to conventional cell-aware ATPG. As major results of this effective test solution, we show that an intra-cell defect coverage increase of up to 7.22% and test time decrease of up to 33.5 % can be achieved in comparison with cell-aware ATPG.