This master's thesis deals with creation of generators of the code for existing virtual platforms QEMU and OVP. This work consist of study of techniques, which are used by virtual machines for their work. Main part of this work is the design of process, which transforms input instruction sets to the code used by these virtual platforms. As the result of this work functional programs, which generate the code for these virtual platforms, was created.

With the scaling of technology nodes, modern CMOS integrated circuits face severe fundamental challenges that stem from device scaling limitations, interconnection bottlenecks and increasing manufacturing complexities. These challenges drive researchers to look for revolutionary technologies beyond the end of CMOS roadmap. Towards this end, a new nanoscale 3-D computing fabric for future integrated circuits, Skybridge, has been proposed [1]. In this new fabric, core aspects from device to circuit style, connectivity, thermal management and manufacturing pathway are co-architected in a 3-D fabric-centric manner. However, the Skybridge fabric uses only n-type transistors in a dynamic circuit style for logic and memory implementations. Therefore, it requires complicated clocking schemes to overcome signal monotonicity associated with cascading dynamic logic gates. For Skybridge’s large-scale circuits, the dynamic circuit style requires cascaded stages to be micro-pipelined, which results in large number of buffers used for storing minterms causing significant overhead in terms of area and power. Moreover, implementation of logic is limited to NAND or AND-of-NAND based logic expressions, which does not always result in compact circuits. In this work, we propose an extension of original Skybridge fabric, called NP-Dynamic-Skybridge, to solve these challenges by using both n-and p-type transistors in an innovative circuit style. Here, every stage in a given circuit is implemented by either n-type or p-type dynamic logic. Cascading n- and p-type dynamic logic effectively avoids signal monotonicity problem, and allows combinational-like circuit implementation. This helps to simplify the clocking scheme for cascaded logics requiring only one set of global precharge and evaluate clock signals. And also it expands the degree of expressing logic enabling expressions such as NOR, OR-of-NORs, in addition to those previously mentioned. Furthermore, the number of pipeline stages is significantly reduced for a given logic function, and buffer requirements are less compared with Skybridge 3D fabric thus improving on area and power metrics. Initial evaluation for NP-Dynamic-Skybridge’s 4-bit carry look-ahead adder shows up to 2x density benefits over Skybridge 3-D fabric and at least 17% power/throughput benefit.

Indiana University-Purdue University Indianapolis (IUPUI) / Feng An and Maher Rizkalla, “Temperature/CO2 Sensor Embedded System Based Communications”, enrolled in ISCA FIRST INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING AND APPLICATIONS, to be held in Orlando, September 15-17, 2010. / In this work, inter-integrated circuit mode (I2C) software was used to communicate between sensors and the embedded control system, utilizing PIC182585 MPLAB hardware. These sensors were built as part of a system on board that includes the sensors, microcontroller, and interface circuitry. The hardware includes the PIC18 processor, FPGA chip, and peripherals. A FPGA chip was used to interface the processor with the peripherals in order to operate at the same clock speed. This hardware design features high level of integration, reliability, high precision, and high speed communications. The software was first designed to operate each sensor separately, then the sensor system was integrated (to combine all sensors, microcontroller, and interfacing circuitries), and the software was updated to provide various actions if triggered by the sensors. Actions taken by the processor may include alarming signals that are based on threshold values received from the sensors, and inquiring temperature and CO2 readings. The system was designed for HVAC (heating, ventilating and air conditioning) applications and industrial settings. The overall system incorporating temperature and CO2 sensors was implemented and successfully tested. The response of the multi-sensor system was agreeable with the design parameters. The system may be expanded to include other sensors such as light senor, pressure sensor, etc. Monitoring the threshold values should add to the security features of the integrated communication system. This design features low power consumption (utilizing the sleeping mode of the processors), high speed communications, security, and flexibility to expansion.

This report discusses in great detail the various research, design, and development stages of the Produce Sorting Microcomputer developed for HAGAN ENGINEERING Inc. The two-semester Clinical Research project has been approved by the graduate committee at the School of Engineering at the University of the Pacific and fulfills the requirements towards a Master Degree in Electrical Engineering. The project was selected based on its complexity, feasibility, the time span it required to complete, and its relevance to the area of real time microcomputer design. In addition, the design constraints and specifications were to be dictated solely by HAGAN ENGINEERING Inc. and all further modifications were to be discussed and approved by HAGAN. These limitations created a professional industry-like atmosphere, which is one of the goals of the Clinical Research Program. A brief User's Manual will accompany the MC68000 board; it will contain all the vital information about the system that a programmer or a technician might need to understand the system. The manual wall contain the complete circuit schematic, a parts list, general design features, and all the software properties of the system (memory map, interrupt tables register map).

Tesis por compendio / [EN] Incorporating error detection mechanisms is a key element in the design of fault tolerant systems. For many of those systems the detection of an error (whether temporary or permanent) triggers a bunch of actions or activation of elements pursuing any of these objectives: continuation of the system operation despite the error, system recovery, system stop into a safe state, etc. Objectives ultimately intended to improve the characteristics of reliability, security, and availability, among others, of the system in question. One of these error detection elements is a watchdog processor; it is responsible to monitor the system processor and check that no errors occur during the program execution. The main drawback of the existing proposals in this regard and that prevents a more widespread use of them is the loss of performance and the increased memory consumption suffered by the monitored system. In this PhD a new technique to embed signatures is proposed. The technique is called ISIS - Interleaved Signature Instruction Stream - and it embeds the watchdog signatures interspersed with the original program instructions in the memory. With this technique it is a separate element of the system processor (a watchdog processor as such) who carries out the operations to detect errors. Although signatures are mixed with program instructions, and unlike previous proposals, the main system processor is not involved neither in the recovery of these signatures from memory nor in the corresponding calculations, reducing the performance loss. A novel technique is also proposed that enables the watchdog processor verification of the structural integrity of the monitored program checking the jump addresses used. This jump address processing technique comes to largely solve the problem of verifying a jump to a new program area when there are multiple possible valid destinations of the jump. This problem did not have an adequate solution so far, and although the proposal made here can not solve every possible jump scenario it enables the inclusion of a large number of them into the set verifiable jumps. The theoretical ISIS proposal and its error detection mechanisms are complemented by the contribution of a complete system (processor, watchdog processor, cache memory, etc.) based on ISIS which incorporates the detection mechanisms proposed here. This system has been called HORUS, and is developed in the synthesizable subset of the VHDL language, so it is possible not only to simulate the behavior of the system at the occurrence of a fault and analyze its evolution from it but it is also possible to program a programmable logic device like an FPGA for its inclusion in a real system. To program the HORUS system in this PhD a modified version of the gcc compiler has been developed which includes the generation of signatures for the watchdog processor as an integral part of the process to create the executable program (compilation, assembly, and link) from a source code written in the C language. Finally, another work developed in this PhD is the development of FIASCO (Fault Injection Aid Software Components), a set of scripts using the Tcl/Tk language that allow the injection of a fault during the simulation of HORUS in order to study its behavior and its ability to detect subsequent errors. With FIASCO it is possible to perform hundreds or thousands of simulations in a distributed system environment to reduce the time required to collect the data from large-scale injection campaigns. Results show that a system using the techniques proposed here is able to detect errors during the execution of a program with a minimum loss of performance, and that the penalty in memory consumption when using a watchdog processor is similar to previous proposals. / [ES] La incorporación de mecanismos de detección de errores es un elemento fundamental en el diseño de sistemas tolerantes a fallos en los que, en muchos casos, la detección de un error (ya sea transitorio o permanente) es el punto de partida que desencadena toda una serie de acciones o activación de elementos que persiguen alguno de estos objetivos: la continuación de las operaciones del sistema a pesar del error, la recuperación del mismo, la parada de sus operaciones llevando al sistema a un estado seguro, etc. Objetivos, en definitiva, que pretenden la mejora de las características de fiabilidad, seguridad y disponibilidad, entre otros, del sistema en cuestión. Uno de estos elementos de detección de errores es un procesador de guardia; su trabajo consiste en monitorizar al procesador del sistema y comprobar que no se producen errores durante la ejecución del programa. El principal inconveniente de las propuestas existentes a este respecto y que impiden una mayor difusión de su uso es la pérdida de prestaciones y el aumento de consumo de memoria que sufre el sistema monitorizado. En este trabajo se propone una nueva técnica de empotrado de firmas (ISIS -Interleaved Signature Instruction Stream) intercaladas dentro del espacio de la memoria del programa. Con ella un elemento separado del procesador del sistema realiza las operaciones encaminadas a detectar los errores. A pesar de que las firmas se encuentran mezcladas con las instrucciones del programa que está ejecutando, y a diferencia de las propuestas previas, el procesador principal del sistema no se involucra ni en la recuperación de las firmas ni en las operaciones de cálculo correspondientes, lo que reduce la pérdida de prestaciones. También se propone una novedosa técnica para que el procesador de guardia pueda verificar la integridad estructural del programa que monitoriza comprobando las direcciones de salto empleadas. Esta técnica de procesado de las direcciones de salto viene a resolver en gran medida el problema de la comprobación de un salto a una nueva zona del programa cuando existen múltiples posibles destinos válidos. Este problema no tenía una solución adecuada hasta el momento, y aunque la propuesta que aquí se hace no consigue resolver todos los posibles escenarios de salto sí permite incorporar un buen números de ellos al conjunto de saltos verificables. ISIS y sus mecanismos de detección de errores se complementan con la aportación de un sistema completo (procesador, procesador de guardia, memoria caché, etc.) basado en ISIS denominado HORUS. Está desarrollado en lenguaje VHDL sintetizable, de manera que es posible tanto simular el comportamiento del sistema ante la aparición de un fallo y analizar su evolución a partir de éste como programar un dispositivo lógico programable tipo FPGA para su inclusión en un sistema real. Para programar el sistema HORUS se ha desarrollado una versión modificada del compilador gcc que incluye la generación de las firmas de referencia para el procesador de guardia como parte del proceso de creación del programa ejecutable a partir de código fuente escrito en lenguaje C. Finalmente, otro trabajo desarrollado en esta tesis es el desarrollo de FIASCO (Fault Injection Aid Software COmponents), un conjunto de scripts en lenguaje Tcl/Tk que permiten la inyección de un fallo durante la simulación de HORUS con el objetivo de estudiar su comportamiento y su capacidad para detectar los errores subsiguientes. Con FIASCO es posible lanzar cientos o miles de simulaciones en un entorno distribuido para reducir el tiempo necesario para obtener los datos de campañas de inyección a gran escala. Los resultados demuestran que un sistema que utilice las técnicas que aquí se proponen es capaz de detectar errores durante la ejecución del programa con una mínima pérdida de prestaciones, y que la penalización en el consumo de memoria al usar un procesador de guardia es similar a la de las propu / [CA] La incorporació de mecanismes de detecció d'errors és un element fonamental en el disseny de sistemes tolerants a fallades. En aquests sistemes la detecció d'un error, tant transitori com permanent, sovint significa l'inici d'una sèrie d'accions o activació d'elements per assolir algun del objectius següents: mantenir les operacions del sistema malgrat l'error, la recuperació del sistema, aturar les operacions situant el sistema en un estat segur, etc. Aquests objectius pretenen, fonamentalment, millorar les característiques de fiabilitat, seguretat i disponibilitat del sistema. El processador de guarda és un dels elements emprats per a la detecció d'errors. El seu treball consisteix en monitoritzar el processador del sistema i comprovar que no es produeixen error durant l'execució de les instruccions. Els principals inconvenients de l'ús del processadors de guarda és la pèrdua de prestacions i l'increment de les necessitats de memòria del sistema que monitoritza, per la qual cossa la seva utilització no està molt generalitzada. En aquest treball es proposa una nova tècnica de encastat de signatures (ISIS - Interleaved Signature Instruction Stream) intercalant-les en l'espai de memòria del programa. D'aquesta manera és possible que un element extern al processador realitze les operacions dirigides a detectar els errors, i al mateix temps permet que el processador execute el programa original sense tenir que processar les signatures, encara que aquestes es troben barrejades amb les instruccions del programa que s'està executant. També es proposa en aquest treball una nova tècnica que permet al processador de guarda verificar la integritat estructural del programa en execució. Aquesta verificació permet resoldre el problema de com comprovar que, al executar el processador un salt a una nova zona del programa, el salt es realitza a una de les possibles destinacions que són vàlides. Fins el moment no hi havia una solució adequada per a aquest problema i encara que la tècnica presentada no resol tots el cassos possibles, sí afegeix un bon nombre de salts al conjunt de salts verificables. Les tècniques presentades es reforcen amb l'aportació d'un sistema complet (processador, processador de guarda, memòria cache, etc.) basat en ISIS i que incorpora els mecanismes de detecció que es proposen en aquest treball. A aquest sistema se li ha donat el nom de HORUS, i està desenvolupat en llenguatge VHDL sintetitzable, la qual cosa permet no tan sols simular el seu comportament davant la aparició d'un error i analitzar la seva evolució, sinó també programar-lo en un dispositiu FPGA per incloure'l en un sistema real. Per poder programar el sistema HORUS s'ha desenvolupat una versió modificada del compilador gcc. Aquesta versió del compilador inclou la generació de les signatures de referència per al processador de guarda com part del procés de creació del programa executable (compilació, assemblat i enllaçat) des del codi font en llenguatge C. Finalment en aquesta tesis s'ha desenvolupat un altre treball anomenat FIASCO (Fault Injection Aid Software COmponents), un conjunt d'scripts en llenguatge Tcl/Tk que permeten injectar fallades durant la simulació del funcionament d'HORUS per estudiar la seua capacitat de detectar els errors i el seu comportament posterior. Amb FIASCO és possible llançar centenars o milers de simulacions en entorns distribuïts per reduir el temps necessari per obtenir les dades d'una campanya d'injecció de fallades de grans proporcions. Els resultats obtinguts demostren que un sistema que utilitza les tècniques descrites és capaç de detectar errors durant l'execució del programa amb una pèrdua mínima de prestacions, i amb un requeriments de memòria similars als de les propostes anteriors. / Rodríguez Ballester, F. (2016). Detección concurrente de errores en el flujo de ejecución de un procesador [Tesis doctoral]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/63254 / Compendio

This thesis dealing with description and of autonomous solar systems and algorithms for control of decision-making mechanism. Optimal set of these machanism has effeect in raise of efficiency in hole autonomous system. In practical purposes propose create one by using microprocesor ATMEGA8, which measure all electrical data in system and control all decisions of implemented algorithm.

International Telemetering Conference Proceedings / October 26-29, 1998 / Town & Country Resort Hotel and Convention Center, San Diego, California / Although PCM/TDM framed data is one of the most prevalent formats handled by flight test ranges, it is often required to acquire and process other types. Examples of such non-standard data types are radar position information and meteorological data from both ground based and radiosonde systems. To facilitate the process and management of such non-standard data types, a micro-processor based system was developed to acquire and transform them into a standard PCM/TDM data frame. This obviated the expense of developing additional special software and hardware to handle such non-standard data types.

I projektet utreds möjligheterna kring att kunna kontrollera en generators reaktiva effektproduktion genom att styra magnetiseringsströmmen från en PLC. Som metod för styrning från PLC beslutades att en signal på 0-5V skulle användas. För att reglera magnetiseringen, och därmed i förlängningen den reaktiva effekten, beslutades att den befintliga manuella potentiometern skulle ersättas med två parallellkopplade digitala potentiometrar av typen MCP4261 som kontrollerades av en mikrokontroller. Att de digitala potentiometrarna skulle parallellkopplas beslutades efter en förstudie som visade på att det skulle resultera i en noggrannare reglering utan någon inskränkning på användbart reglerspann. Praktisk provning av mikrokontroller och digitala potentiometrar gav ett tillfredsställande och bra resultat med god upplösning. / This project investigates the possibilities of being able to control a generators reactive power production by controlling the excitation current from a PLC. As a method for controlling from PLC, it was decided that a signal of 0-5V should be used. In order to regulate the magnetization, and hence in the long term the reactive power, it was decided that the existing manual potentiometer would be replaced by two parallel-connected digital potentiometers of the type MCP4261 controlled by a microcontroller. The fact that the digital potentiometers would be connected in parallel was decided after a feasibility study which showed that in this way it would result in a more accurate regulation without any restriction on the usable control span. Practical testing of microcontrollers and digital potentiometers provided a satisfactory result with a good resolution.

Em função das limitações apresentadas pelos relés eletromecânicos, a proteção térmica de motores foi historicamente tratada como um problema de coordenação de sobrecorrente, sem levar em consideração a dinâmica e o histórico térmico envolvido na operação contínua do motor. Os atuais relés microprocessados para proteção de motores implementam equações diferenciais de primeira ordem, cujos algoritmos, processados em tempo real, possibilitam uma nova abordagem para uma adequada proteção térmica, utilizando modelos matemáticos. Especialmente para os motores industriais de grande porte e de maior importância operacional, somente os recentes relés de proteção microprocessados e seus algoritmos digitais tem sido efetivamente capazes de fornecer proteção adequada, baseados em modelos térmicos que realisticamente estimam, continuamente e em tempo real, o nível térmico atual do motor. A proteção térmica de motores de indução trifásicos tem sido uma das maiores áreas onde a proteção numérica, baseado em microprocessadores, tem proporcionado um aprimoramento do nível básico das funções de proteção de motores. O método da proteção térmica tem sido aperfeiçoado, de forma a implementar modelos que levam em consideração o aquecimento do motor devido às correntes de seqüência positiva e negativa e as características térmicas de um motor de indução. A capacidade do processamento digital de sinais tem possibilitado a implementação de novas soluções para as deficiências de proteção de motores industriais trifásicos apresentadas pelas tecnologias convencionais de proteção, até então fundamentadas em proteção de sobrecorrente. As principais funções de proteção aplicáveis para motores trifásicos industriais, bem como os aspectos do estado da arte de hardware, software e filtros digitais implementados nos atuais relés de proteção microprocessados são discutidos neste trabalho. O equacionamento de um sistema térmico de primeira ordem e os requisitos de modelo para a implementação da proteção térmica de motores são também aqui analisados. São discutidas as dinâmicas de dois modelos térmicos, um baseado em proteção por sobrecorrente e outro baseado em um sistema térmico de primeira ordem. São simulados e comparados os desempenhos destes dois diferentes algoritmos de proteção térmica de motores, quando submetidos às correntes de carga e de sobrecarga, tanto constantes como cíclicas. / On account of the limitations presented for the electromechanical relays, the motor thermal protection was historically treated as an overcurrent coordination issue, without taking into account the dynamics and the thermal historical involved in the process. The modern microprocessor-based relays for motor protection implement discrete time first-order differential equations, whose algorithms, based on the power of the real time signal processing, make possible a new approach for a proper thermal protection, applying mathematical models. Especially for large and critical operational significance industrial motors, only the recent numerical relays for motor protection and its digital algorithms has been efficiently suitable to provide an adequate protection, based in thermal models that realistically take into account, continuously and in real time, the actual motor thermal level. The thermal protection of three-phase induction motors has been one of the biggest areas where the numerical protection, based in microprocessor-based relays, has provide an improvement of the basic level of the motor protection functions. The method of the thermal protection has been improved, in such wise as to implement models that take into account the motor heating due to both positive and negative sequence currents, and the thermal characteristics of an induction motor. The capacity of the digital signal processing has made possible the implementation of new solutions for the deficiencies of three-phase industrial motors protection, established on the conventional protection technologies, till then based on overcurrent protection. The main applicable protection functions for industrial three-phase motors, as well as the aspects of the state of the art of the hardware, software and digital filters implemented in the actual microprocessor-based protection relays are discussed in this work. The derivation of a first-order thermal system and the requirements of model for the implementation of the motor thermal protection also are studied in this work. The dynamics of two thermal models, one based in overcurrent protection and another based on a first-order thermal system are analyzed. The performances of these two different algorithms of motor thermal protection are simulated and compared, when subjected to both constants and cyclic, load and overload currents.

Em função das limitações apresentadas pelos relés eletromecânicos, a proteção térmica de motores foi historicamente tratada como um problema de coordenação de sobrecorrente, sem levar em consideração a dinâmica e o histórico térmico envolvido na operação contínua do motor. Os atuais relés microprocessados para proteção de motores implementam equações diferenciais de primeira ordem, cujos algoritmos, processados em tempo real, possibilitam uma nova abordagem para uma adequada proteção térmica, utilizando modelos matemáticos. Especialmente para os motores industriais de grande porte e de maior importância operacional, somente os recentes relés de proteção microprocessados e seus algoritmos digitais tem sido efetivamente capazes de fornecer proteção adequada, baseados em modelos térmicos que realisticamente estimam, continuamente e em tempo real, o nível térmico atual do motor. A proteção térmica de motores de indução trifásicos tem sido uma das maiores áreas onde a proteção numérica, baseado em microprocessadores, tem proporcionado um aprimoramento do nível básico das funções de proteção de motores. O método da proteção térmica tem sido aperfeiçoado, de forma a implementar modelos que levam em consideração o aquecimento do motor devido às correntes de seqüência positiva e negativa e as características térmicas de um motor de indução. A capacidade do processamento digital de sinais tem possibilitado a implementação de novas soluções para as deficiências de proteção de motores industriais trifásicos apresentadas pelas tecnologias convencionais de proteção, até então fundamentadas em proteção de sobrecorrente. As principais funções de proteção aplicáveis para motores trifásicos industriais, bem como os aspectos do estado da arte de hardware, software e filtros digitais implementados nos atuais relés de proteção microprocessados são discutidos neste trabalho. O equacionamento de um sistema térmico de primeira ordem e os requisitos de modelo para a implementação da proteção térmica de motores são também aqui analisados. São discutidas as dinâmicas de dois modelos térmicos, um baseado em proteção por sobrecorrente e outro baseado em um sistema térmico de primeira ordem. São simulados e comparados os desempenhos destes dois diferentes algoritmos de proteção térmica de motores, quando submetidos às correntes de carga e de sobrecarga, tanto constantes como cíclicas. / On account of the limitations presented for the electromechanical relays, the motor thermal protection was historically treated as an overcurrent coordination issue, without taking into account the dynamics and the thermal historical involved in the process. The modern microprocessor-based relays for motor protection implement discrete time first-order differential equations, whose algorithms, based on the power of the real time signal processing, make possible a new approach for a proper thermal protection, applying mathematical models. Especially for large and critical operational significance industrial motors, only the recent numerical relays for motor protection and its digital algorithms has been efficiently suitable to provide an adequate protection, based in thermal models that realistically take into account, continuously and in real time, the actual motor thermal level. The thermal protection of three-phase induction motors has been one of the biggest areas where the numerical protection, based in microprocessor-based relays, has provide an improvement of the basic level of the motor protection functions. The method of the thermal protection has been improved, in such wise as to implement models that take into account the motor heating due to both positive and negative sequence currents, and the thermal characteristics of an induction motor. The capacity of the digital signal processing has made possible the implementation of new solutions for the deficiencies of three-phase industrial motors protection, established on the conventional protection technologies, till then based on overcurrent protection. The main applicable protection functions for industrial three-phase motors, as well as the aspects of the state of the art of the hardware, software and digital filters implemented in the actual microprocessor-based protection relays are discussed in this work. The derivation of a first-order thermal system and the requirements of model for the implementation of the motor thermal protection also are studied in this work. The dynamics of two thermal models, one based in overcurrent protection and another based on a first-order thermal system are analyzed. The performances of these two different algorithms of motor thermal protection are simulated and compared, when subjected to both constants and cyclic, load and overload currents.