This dissertation presents the design and implementation of circuits and transceivers in CMOS technology to enable many new millimeter-wave applications. A simple approach is presented for accurately modeling the millimeter-wave characteristics of transistors that are not fully captured by contemporary parasitic extraction techniques. Next, the integration of a low-power 60-GHz CMOS on-off keying (OOK) receiver in 90-nm CMOS for use in multi-gigabit per second wireless communications is demonstrated. The use of non-coherent OOK demodulation by a novel demodulator enabled a data throughput of 3.5 Gbps and resulted in the lowest power budget (31pJ/bit) for integrated 60-GHz CMOS OOK receivers at the time of publication. Also presented is the design of a high-power, high-efficiency 45-GHz VCO in 45-nm SOI CMOS. The design is a class-E power amplifier placed in a positive feedback configuration. This circuit achieves the highest reported output power (8.2 dBm) and efficiency (15.64%) to date for monolithic silicon-based millimeter-wave VCOs. Results are provided for the standalone VCO as well as after packaging in a liquid crystal polymer (LCP) substrate. In addition, a high-power high-efficiency (5.2 dBm/6.1%) injection locked oscillator is presented. Finally, the design of a 2-channel 45-GHz vector modulator in 45-nm SOI CMOS for LINC transmitters is presented. A zero-power passive IQ generation network and a low-power Gilbert cell modulator are used to enable continuous 360° vector generation. The IC is packaged with a Wilkinson power combiner on LCP and driven by external DACs to demonstrate the first ever 16-QAM generated by outphasing modulation in CMOS in the Q-band.

The objective of the research is to develop high-speed ADCs and mixed-signal demodulator for multi-gigabit communication systems using millimeter-wave frequency bands in standard CMOS technology. With rapid advancements in semiconductor technologies, mobile communication devices have become more versatile, portable, and inexpensive over the last few decades. However, plagued by the short lifetime of batteries, low power consumption has become an extremely important specification in developing mobile communication devices. The ever-expanding demand of consumers to access and share information ubiquitously at faster speeds requires higher throughputs, increased signal-processing functionalities at lower power and lower costs. In today’s technology, high-speed signal processing and data converters are incorporated in almost all modern multi-gigabit communication systems. They are key enabling technologies for scalable digital design and implementation of baseband signal processors. Ultimately, the merits of a high performance mixed-signal receiver, such as data rate, sensitivity, signal dynamic range, bit-error rate, and power consumption, are directly related to the quality of the embedded ADCs. Therefore, this dissertation focuses on the analysis and design of high-speed ADCs and a novel broadband mixed-signal demodulator with a fully-integrated DSP composed of low-cost CMOS circuitry. The proposed system features a novel dual-mode solution to demodulate multi-gigabit BPSK and ASK signals. This approach reduces the resolution requirement of high-speed ADCs, while dramatically reducing its power consumption for multi-gigabit wireless communication systems.

The objective of this research is to present a low power modem technology for a high speed millimeter wave wireless system. The first part of the research focuses on a robust ASIC design methodology. There are several aspects of the ASIC flow that require special attention such as logical synthesis, timing driven physical placement, Clock Tree Synthesis, Static Timing Analysis, estimation and reduction of power consumption and LVS and DRC closure. The latter part is dedicated to high speed baseband circuits such as Coherent and Non coherent demodulator which are critical components of a multi-gigabit wireless communication system. The demodulator operates at input data rates of multiple gigabits per second, which presents the challenge of designing the building blocks to operate at speeds of multiple GHz. The high speed complex multiplier is a major component of the non coherent demodulator. As part of the coherent demodulator the complex multiplier derotates the input sequence by multiplying with cosine and sine functions, Costas error calculator computes the phase error in the derotated input signal. The NCO (Numerically controlled Oscillator) is a look up table based system used to generate the cosine and sine functions, used by the derotator.The CIC filter is used to decimate the costas error signal as the loop bandwidth is significantly smaller compared to the sampling frequency. All these modules put together form the coherent demodulator which is an integral part of the wireless communication system. An implementation of Serdes is also presented which acts as an interface between the baseband modules and the RF front end.

Driven by the ever growing consumer wireless electronics market and the need for higher speed communications, the 60-GHz technology gifted with an unlicensed 9 GHz frequency band in the millimeter-wave spectrum has emerged as the next-generation Wi-Fi for short-range wireless communications. High-performance, cost-effective, and small form-factor 60-GHz antenna systems for portable devices are key enablers of this technology. This work presents various antenna architectures built on low-cost organic packages. Planar end-fire switched beam antenna modules that can easily conform to various surfaces inside a wireless device platform are developed. The planar antenna package is realized on thin flexible LCP dielectrics. One design is based on a planar Yagi-Uda antenna element and the second on a tapered slot antenna element. A low-loss microstrip-to-slot via transition is designed to provide wide impedance matching for end-fire antenna paradigms. The novel transition utilizes the slow-wave concept to provide unbalanced to balanced mode conversion as well as impedance matching. It is demonstrated that the planar antenna packages may be even integrated with active circuits that are cavity recessed inside the thin dielectric. A compact switched-beam antenna module is demonstrated. The first-ever integrated mm-wave active antenna module on organic package capable of generating both broadside and end-fire radiation is also developed in this work. Both broadside and end-fire radiators are co-designed and integrated into a single multilayer package to achieve optimal directivity, efficiency and frequency bandwidth and yet maintain excellent isolation between the two radiators. Post-wall cavities, image theory and dielectric slab modes concepts are invoked to optimize these functions. Active circuitry are integrated into the same package to add control functions such as beam switching, and also amplify the packaged-antenna gain when operated either as a transmitter or a receiver. A significant challenge in the design of antenna systems for wireless platforms is the assessment of embedded antenna performance, that is, the proximity effects of the platform chassis on the embedded antenna. Various antennas are mounted at different locations inside a laptop computer chassis: modeling and experimental studies are carried out to characterize this problem that is apparent to an antenna behind a radome. Air traffic control radars usually require cavity filters that can handle high power and low in-band insertion loss while providing enough out-band rejection to prevent interference with neighboring channels. Such radars that operate in the S-band consist of filter banks frequency micro electromechanical systems (RF-MEMS) switches. Evanescent-mode mode cavity resonators are loaded with RF-MEMS tuning capacitance networks to control the resonant frequency of a second-order bandpass filter. The second part is the design of a novel cavity filter architecture for enhanced selectivity near the passband. It is a second-order folded cavity resonator bandpass filter with magnetic source-load cross coupling. This filter can have at least two finite transmission zeros near the passband.

The enabling technologies and the issues of next-generation millimeter-wave wireless access network and 100G long-haul optical transport network were developed and identified. To develop a simple and cost-effective millimeter-wave optical-wireless system, all-round research on the technical challenges of optical millimeter-wave generation, transmission impairments compensation, and simple base station design were discussed. Several radio-over-fiber systems were designed to simultaneously deliver multi-band wireless services on a single optical infrastructure, enabling converged system control and quality maintenance in central office. For the 100G optical transport network, the issues related to successful implementations of transmitter, fiber link, and receiver of a 112-Gb/s polarization-division multiplexing-quadrature phase shift keying (PDM-QPSK) system were comprehensively explored. The experimental results based on the constructed 112-Gb/s testbed indicated that careful dispersion management can effectively increase nonlinearity tolerance. Furthermore, the special emphasis on the two impairments of the 100G network with reconfigurable optical add-drop multiplexers: passband narrowing and in-band crosstalk, was studied. The results demonstrated that these impairments can be readily predicted with proper experimental and simulation efforts.

With rapid advances in semiconductor technologies and packaging schemes, wireless products have become more versatile, portable, inexpensive, and user friendly over last few decades. However, the ever-growing demand of consumers to share information efficiently at higher speeds requires higher data rates, increased functionality, lower cost, and more reliability. The 60-GHz-frequency band, with 7 GHz license-free bandwidth addresses, such demands, and promises a low-cost multi-Gbps wireless transmission with a power budget in the order of 100 mW. This dissertation presents the systematic development of key building blocks and integrated 60-GHz-receiver solutions. Two different approaches are investigated and implemented in this dissertation: (1) low-cost SiGe-based direct-conversion low-power receiver front-end utilizing gain-boosting techniques in the front-end low-noise amplifier, and (2) CMOS-based heterodyne receiver front-end suitable for high-performance single-chip 60 GHz transceiver solution. The ASK receiver chip, implemented using 0.18 ?m SiGe, presents a complete antenna-to-baseband multi-gigabit 60 GHz solution with the lowest reported power budget (25 pJ/bit) to date. The subharmonic direct conversion front-end, implemented using 0.18 ?m SiGe, presents excellent conversion properties with a 4 GHz DSB RF bandwidth. On the other hand, the CMOS heterodyne implementation of the 60 GHz front-end receiver, targeted towards a robust, single-chip, high-performance, low-power, and integrated 60 GHz transceiver solution, presents the most wideband receiver front-end reported to date. Finally, different multi-band and tunable millimeter-wave circuits are presented towards the future implementation of cognitive and multi-band millimeter-wave radio.

Three 40/60-GHz optical-wireless bidirectional architectures are designed with a centralized light source in the central office based on wavelength reuse. Three super-broadband access networks are proposed and experimentally demonstrated for simultaneously delivering wired and wireless services over an optical fiber and an air link in a single transport platform. The transport feasibility in metro and wide-area access networks with multiple reconfigurable optical add-drop multiplexers (ROADMs) nodes is explored for 40-GHz and 60-GHz optical millimeter-wave signals. Additionally, the optical-wireless systems using the orthogonal frequency division multiplexing (OFDM) modulation format are analytically and experimentally demonstrated to mitigate the chromatic dispersion in optical fiber. This thesis also successfully implements the testbed trial for the delivery of uncompressed 270-Mb/s standard-definition television (SDTV) and 1.485-Gb/s high-definition television (HDTV) video signals over optical fiber and air links. The demonstration represents the first ever reported real applications over hybrid wired and wireless access networks, showing that our developed up-conversion schemes and designed architectures are highly suitable for super-broadband applications in next-generation optical-wireless access networks.

The radio frequency (RF) spectrum as a natural resource is severely under-utilized over time and space due to an inefficient licensing framework. As a result, in-creasing cellular and wireless network usage is placing significant demands on the licensed spectrum. This has led to the development of cognitive radios, software defined radios and mm-wave radios. Cognitive radios (CRs) enable more efficient spectrum usage over a wide range of frequencies and hence have emerged as an effective solution to handle huge network demands. They promise versatility, flex-ability and cognition which can revolutionize communications systems. However, they present greater challenges to the design of radio frequency (RF) front-ends. Instead of a narrow-band front-end optimized and tuned to the carrier frequency of interest, cognitive radios demand front-ends which are versatile, configurable, tun-able and capable of transmitting and receiving signals with different bandwidths and modulation schemes. The primary purpose of this thesis is to design a re-configurable, wide-band and low phase-noise fast settling frequency synthesizer for cognitive radio applications. Along with frequency generation, an area efficient multi-band low noise amplifier (LNA) with integrated built-in-self-test (BIST) and a strong immunity to interferers has also been proposed and implemented for these radios. This designed LNA relaxes the specification of harmonic content in the synthesizer output. Finally some preliminary work has also been done for mm-wave (V-band) frequency synthesis. The Key Contributions of this thesis are: A frequency synthesizer, based on a type-2, third-order Phase Locked Loop (PLL), covering a frequency range of 0.1-5.4 GHz, is implemented using a 0.13 µm CMOS technology. The PLL uses three voltage controlled oscillators (VCOs) to cover the whole range. It is capable of switching between any two frequencies in less than 3 µs and has phase noise values, compatible with most communication standards. The settling of the PLL in the desired state is achieved in dynamic multiple steps rather than traditional single step settling. This along with other circuit techniques like a DAC-based discriminator aided charge pump, fast acquisition pulse-clocked based PFD and timing synchro-negation is used to obtain a significantly reduced settling time A single voltage controlled LC-oscillator (LC-VCO) has been designed to cover a wide range of frequencies (2.0-4.1 GHz) using an area efficient and switch-able multi-tap inductor and a capacitor bank. The switching of the multi-tap inductor is done in the most optimal manner so as to get good phase-noise at the output. The multi-tap inductor provides a significant area advantage, and in spite of a degraded Q, provides an acceptable phase noise of -123 dBc/Hz and -113 dBc/Hz at an offset of 1 MHz at carrier frequencies of 2 and 4 GHz, respectively. Implemented in a 0.13 µm CMOS technology, the oscillator with ≈ 69 % tuning range, occupies an active area of only 0.095 mm2. An active inductor based noise-filter has been proposed to improve the phase-noise performance of the oscillator without much increase in the area. A variable gain multi-band low noise amplifier (LNA) is designed to operate over a wide range of frequencies (0.8 GHz to 2.4 GHz) using an area efficient switchable-π network. The LNA can be tuned to different gain and linearity combinations for different band settings. Depending upon the location of the interferers, a specific band can be selected to provide optimum gain and the best signal-to-intermodulation ratio. This is accomplished by the use of an on-chip Built-in-Self-Test (BIST) circuit. The maximum power gain of the amplifier is 19 dB with a return loss better than 10 dB for 7 mW of power consumption. The noise figure is 3.2 dB at 1 GHz and its third-order intercept point (I I P3) ranges from -15 dBm to 0 dBm. Implemented in a 0.13 µm CMOS technology, the LNA occupies an active area of about 0.29 mm2. Three different types of VCOs (stand-alone LC VCO, push-push VCO and a ring oscillator based VCO) for generating mm-wave frequencies have been implemented using 65-nm CMOS technology and their measured results have been analyzed