Neutral-point-clamped (NPC) three-level inverter is capable of handling higher dc bus voltage and producing output waveform of better quality than a conventional two-level inverter. The main objective of the present work is to analyze the existing PWM schemes for two-level and three-level inverters in terms of line current ripple, and to design new PWM techniques for the NPC inverter to reduce line current distortion. Various discontinuous PWM or bus-clamping PWM (BCPWM) methods for a two-level voltage source inverter are analyzed in terms of rms line current ripple, which is evaluated by integrating the error voltage (i.e. error between the applied and reference voltages). The BCPWM schemes can be broadly classified into continual-clamp PWM (CCPWM) and split-clamp PWM (SCPWM). It is shown that split-clamp PWM scheme leads to lower harmonic distortion than CCPWM scheme. Further, advanced bus-clamping PWM (ABCPWM) methods for a two-level inverter are also studied. These methods clamp each phase to the positive and negative DC terminals over certain intervals as in BCPWM schemes, and also switch each phase at double the nominal frequency in certain other intervals unlike in BCPWM. Analytical closed-form expressions are derived for the total rms harmonic distortion due to SCPWM, CCPWM and ABCPWM schemes. Existing sinusoidal and bus-clamping PWM schemes for three-level NPC inverters are also analyzed in the space vector domain. These methods are compared in terms of line current ripple analytically as well as experimentally. As earlier, closed-form expressions are derived for the harmonic distortion factors corresponding to centered space vector PWM (CSVPWM) and the various BCPWM methods. A three-level inverter can be viewed as an equivalent two-level inverter in each sixth of the fundamental cycle or hextant. This is widely used to simplify the control of an NPC inverter. Further, this approach makes it simple to extend the BCPWM and ABCPWM methods for two-level inverters to three-level inverters. Furthermore, the method of analysis of line current ripple for the two-level inverter can also be easily extended to the three-level case. The pivot vector, which is half the length of the longest voltage vectors produced by the NPC inverter, acts as an equivalent null vector for the conceptual two-level inverter. Each pivot vector can be produced by two inverter states termed as “pivot states”. Typically, in continuous modulation methods for NPC inverter such as sinusoidal PWM and centered space vector PWM, the switching sequence (i.e. the sequence in which the voltage vectors are applied) begins and ends with the same pivot vector in each subcycle, which is equivalent to a half-carrier cycle. To be more precise, the switching sequence starts with one pivot state and ends with the other in each subcycle. However, in case of BCPWM schemes, only one pivot state is used in a subcycle. The choice of pivot state results in a variety of BCPWM schemes for an NPC inverter. Different BCPWM schemes are evaluated in terms of rms line current ripple. The optimal BCPWM, which minimizes the rms current ripple, is determined for an NPC inverter, controlled as an equivalent two-level inverter. Further, four new switching sequences are proposed here for a three-level inverter, controlled as a conceptual two-level inverter. These sequences apply the pivot vector only once, but employ one of the other two vectors twice within the subcycle. These four switching sequences are termed as “ABCPWM sequences” for three-level inverter. These sequences exploit the flexibility available in the space vector approach to PWM to switch a phase more than once in a subcycle, which results in the application of an active vector twice within the subcycle. Influence of the proposed ABCPWM sequences on the line current ripple over a subcycle is studied. The various sequences are compared in terms of rms line current ripple over a subcycle. An analytical closed-form expression for rms line current ripple over a subcycle is derived in terms of reference magnitude, angle of reference voltage vector, and subcycle duration for each of the sequences. Further, closed-form expressions are also derived for the rms current ripple over a line cycle in terms of modulation index and subcycle duration, corresponding to the various sequences. The four proposed ABCPWM sequences for the NPC inverter can be grouped into two pairs of sequences. Each pair of sequences is shown to perform better than the individual sequences, if the two sequences are employed in appropriate spatial regions. Hence, with these two pairs of sequences, two hybrid PWM schemes are proposed. Finally, a hybrid PWM technique is proposed which employs all five sequences (conventional and proposed four sequences) in spatial regions where each performs the best. This is termed as “five-zone hybrid PWM”. The total harmonic distortion (THD) in the motor current, pertaining to all the proposed schemes, is studied theoretically over the entire range of linear modulation. The theoretical investigations are validated experimentally on a 2.2 kW, 415V, 4.9A, 50 Hz induction motor drive. The no-load current THD is measured over a range of fundamental frequency from 10 Hz to 50 Hz in steps of 2 Hz for the various PWM methods. Theoretical and experimental results bring out the reduction in current THD due to the proposed BCPWM schemes at fundamental frequencies of 45 Hz and above, compared to CSVPWM. The ABCPWM methods improve the performance at higher as well as lower modulation indices. Further improvement is achieved with the proposed five-zone hybrid PWM. At the rated frequency (50 Hz) of the drive, the improvement in line current distortion is around 36% with this hybrid PWM scheme over CSVPWM. The reduction in THD is also experimentally verified at different loads on the motor. The difference between the top and bottom capacitor voltages is measured at various operating conditions, corresponding to CSVPWM and the proposed schemes. No significant difference is observed in the dc neutral voltage shifts with the different proposed schemes and CSVPWM method. Thus, the proposed methods improve the THD at low and high speed ranges without appreciable worsening of the dc voltage unbalance.

La première thématique développée dans ce mémoire vise à développer de nouveaux algorithmes pour la commande des éoliennes reposant sur une machine asynchrone à double alimentation et des convertisseurs multi niveaux. Deux stratégies de contrôle direct du courant, basées sur l’Hystérésis à Zones Carrées et l’Hystérésis à Zones Circulaires (HZCi) ont été proposées. Celles-ci consistent à appliquer des vecteurs de tension appropriés pour contrôler les puissances actives et réactive générées et permettent également d’équilibrer les tensions du bus continu interne des convertisseurs. Des résultats de simulation et d’expérimentation montrent que la stratégie basée sur l’HZCi est meilleure en termes de forme d’onde et de contenu harmonique des tensions de sortie.La seconde concerne la supervision et la gestion des puissances active et réactive dans une ferme éolienne au vu de son intégration dans un réseau électrique. Cette supervision centralisée est assurée par un algorithme qui distribue les consignes de puissance aux éoliennes de la ferme de manière proportionnelle. Ces références sont fonction de la capacité maximale de production de l’éolienne. Pour cela, une analyse des transits de puissance dans le système éolien à base de la machine asynchrone à double alimentation a été effectuée. Elle a permis de déterminer la caractéristique (P, Q) du générateur et de calculer ses limites de compensation en termes de puissance réactive. Une gestion locale des puissances de chaque éolienne a été développée permettant ainsi une répartition des puissances entre le stator de la machine et le convertisseur coté réseau en considérant plusieurs modes de fonctionnement du système éolien / This research work deals with two topics conditioning the large scale development of wind turbines into electrical grids. The first is devoted to the development of new algorithms for the control of Doubly Fed Induction Machine (DFIM) based wind energy conversion systems. Two direct current control strategies have been proposed and are based on the hysteresis square areas (HZCA) and hysteresis circular areas (HZCI). Both strategies apply an appropriate voltage vector to control the active and reactive powers delivered to the grid, and also, to balance the voltages of the inner DC bus converter. Simulation and experimental results show that the HZCI strategy is better than HZCA in terms of output voltage waveforms and harmonic contain.The second topic is dedicated to the active and reactive powers supervision in a wind farm in order to supply prescribed power references from the grid operator. This supervision is ensured by a centralized algorithm that distributes power references between wind turbines in a proportional way. These references are calculated according to the maximum production capacity of wind turbines. An analysis of the power flow in the DFIM based wind energy system has been made to identify the (P, Q) characteristic and to calculate limits in terms of reactive power compensation. The local power management of each wind system has been developed allowing the powers distribution between the stator of the DFIM and the grid side converter by considering several operating modes of the wind generator

Modular Multilevel Converters (MMCs), over recent years, have gained popularity in high-voltage(HV) and medium-voltage (MV) applications due to their high reliability. Also, with the rapid growth of solar photovoltaics (PV) and energy storage systems, there is a high demand for efficient and reliable power converter solutions. Therefore, due to the seen merits behind MMCs, this thesis assesses their performance for low-voltage (LV) applications. This is accomplished by comparing basic MMC solutions with an equivalent flying capacitors based solution. Such comparison is based on the evaluation of the passive elements requirements, semi-conductor losses, area, voltage, and current stresses, and common-mode voltage. It is worth mentioning that the evaluation is based on utilizing LV MOSFETs. Furthermore, the thesis introduces a modulation scheme for the full-bridge submodule MMC, thus further exploring the different operating regions of the full-bridge based MMC.

The Modular Multilevel Converter (MMC) is one of the most commonly used active converters in the high-/medium-voltage sector due to its many advantages such as high scalability, high efficiency, modularity and low harmonic contents. However, in low-voltage and high-current applications, classical MMC designs are not very economical. Recently there has been interest in a new design of modular multilevel converter with interleaved submodules (ISM-MMC) capable of using lower cost, lower current switches. The aim of this study is to compare several different design configurations for a given ISM-MMC topology including classical MMC and to give the best design approach taking into account the efficiency and energy density of the system. The power loss of ISM-MMC influence the final efficiency. The loss studied in this thesis mainly consists of conduction losses and switching losses in the semiconductor devices and inductor losses. An analytical calculation method is summarized and validated by the simulation result. The simulation result is carried out in PLECS model with different system components. Power density is determined by the output power and the converter dimension. The volume of semiconductor devices and passive components determine the general dimension of the converter. This thesis discusses the selection of semiconductor devices, inductor and capacitor in the system, with semiconductor devices constraining interleaved leg current and submodule voltage, inductor constraining output current ripple and capacitor constraining capacitor voltage fluctuation. After the specific components are designed, their dimensions are evaluated, and thus the power density of different configurations can be compared. / Den modulära multinivåomvandlaren (modular multilevel converter, MMC) är en av de mest använda aktiva omvandlarna inom hög-/mellanspänningssektorn på grund av dess många fördelar som hög skalbarhet, hög verkningsgrad, modularitet och lågt övertonsinnehåll. Men i lågspännings- och högströmsapplikationer är konventionella MMC-konstruktioner inte särskilt ekonomiska. Nyligen har det funnits intresse för en ny design av modulär flernivåomvandlare med interfolierade submoduler (ISM-MMC) som kan uppnå lägre kostnad, och använda mindre halvledarelement. Syftet med denna studie är att jämföra flera olika designkonfigurationer för en given ISM-MMC-topologi inklusive konventionell MMC och att ge den bästa designmetoden med hänsyn till systemets verkningsgrad och energitäthet. Effektförlusten för ISM-MMC påverkar den slutliga verkningsgraden. Förluster som studeras i denna avhandling består huvudsakligen av ledningsförluster och kopplingsförluster i halvledarenheterna och induktorförluster. En analytisk beräkningsmetod sammanfattas och valideras av simuleringsresultatet. Simuleringsresultatet utförs men en PLECS-modell med olika systemkomponenter. Effekttätheten bestäms av uteffekten och omvandlardimensionen. Volymen av halvledarenheter och passiva komponenter bestämmer omvandlarens allmänna dimension. Denna avhandling diskuterar valet av halvledarenheter, induktor och kondensator i systemet, med halvledarenheter som begränsar interfolierad benström och submodulspänning, induktor som begränsar utströmsrippel och kondensatorbegränsande kondensatorspänningsfluktuationer. Efter att de specifika komponenterna har valts utvärderas deras storlek, och därmed kan effekttätheten för olika konfigurationer jämföras.

Les structures de conversion multiniveaux permettent de convertir en moyenne tension et forte puissance. Celles-ci sont construites à partir de cellules de commutations et permettent d’augmenter le courant et la tension en entrée ou en sortie. Ces structures sont appelées multiniveaux car les formes d’ondes des tensions en sortie permettent d’avoir plus de deux niveaux de tension différents. Les différentes structures peuvent être classées dans différentes catégories tel que la mise en série de pont en H, les convertisseurs multicellulaires série ou parallèle ou encore les structures utilisant le fractionnement du bus continu. Toutes ces structures ont des propriétés et applications différentes, même si certaines structures ont des propriétés communes. Il est aussi possible de créer de nouvelles structures en mixant les différentes structures de bases des différentes familles de convertisseurs multiniveaux ou en assemblant les structures de base de la conversion statique. Même si l’utilisation de structure de conversion multiniveaux permet de convertir à forte puissance, celle-ci n’est pas toujours aisée. En effet l’augmentation du nombre de niveaux ou de la tension d’entrée implique également une augmentation du nombre de composants semiconducteurs. Ceci peut être un frein à l’utilisation de convertisseur multiniveaux. Pour cela une nouvelle structure utilisant des composants partagés entre les différentes phases est proposée afin de limiter leur nombre. Un autre problème important lié aux convertisseurs multiniveaux est l’équilibrage des tensions des condensateurs du bus continu si celui-ci est composé de plus de deux condensateurs mis en série. Pour cela plusieurs solutions sont possibles : soit en utilisant une commande spécifique utilisant la modulation vectorielle, soit en utilisant des structures auxiliaires qui ont pour but d’équilibrer les différentes tensions des condensateurs. Dans une dernière partie ont été proposées de nouvelles structures qui permettent à la fois d’augmenter le courant de sortie et la tension en entrée en utilisant les principes des structures de base des convertisseurs multicellulaires série et parallèle. De plus, ces structures ont des propriétés intéressantes sur les formes d’ondes de sortie. De ces structures a été conçu un prototype permettant de valider les résultats de simulation. Une commande numérique implantée sur FPGA a été réalisée et a permis d’avoir des résultats expérimentaux intéressants. / This PhD Thesis deals with the study of new multilevel structures. At the beginning of this work, a new methodology to create new multilevel structures has been conceived. To evaluate the performances of these structures, there are many possibilities: number of output voltage levels, number of components, and the quality of the converters’ output waveforms. The list of criteria is not exhaustive. One technique to obtain an output multilevel waveform is to split the DC link in several capacitors. There is a limitation since putting more than two capacitors in serial connection leads to an unbalancing of these voltage capacitors. Several solutions are possible to balance these voltages. The first one uses the control of the structure in a three phase application, using a space vector modulation and minimizing the energy stored in the DC link. The second solution consists in using auxiliary circuits, which realize an energy transfer between one capacitor to another through an inductor. The drawback of this method is the high number of components. This problem can be reduced sharing some components between the three phases of the converter. The third part of this study is related to multicell converters, structures with very interesting good properties. New converter structures mix serial and parallel multicell converters, to obtain a hybrid converter with similar performances to the two basic converters. An experimental prototype was built to validate the results of the PhD. The digital control of this hybrid structure was made with a FPGA where two DSP processors were implemented.

Multilevel converters are finding increased attention in industry and academia as the preferred choice of electronic power conversion for high power applications. They have a wide application area in a variety of industries involving transportation and energy management, a significant portion of which comprises of multilevel inverter fed induction motor drives. Multilevel inverters are ideally suitable for high power drives, since the switching frequency of the devices is limited for high power applications. In low power drives, the switching frequency is often in the range of tens of kHz, so that switching frequency harmonics are pushed higher in the frequency spectrum thereby the size and cost of the filter are reduced. But higher switching frequency has its own drawbacks, in particular for high voltage, high power applications. They cause large dv/dt stress on the motor and the devices, increased EMI problems and higher switching losses. An engineering trade-o is thus needed to select the minimum switching frequency without compromising on the output voltage quality. The present work is an alternate approach in this direction. Here, new inverter topologies and PWM strategies are developed that can eliminate a set of harmonics in the phase voltage using 12-sided polygonal space vector diagrams, also called dodecagonal space vector diagrams. A dodecagonal space vector diagram has many advantages over a hexagonal one. Switching space vectors on a dodecagon will not produce any harmonics of the order 6n 1, (n=odd) in the phase voltage. The next set of harmonics thus reside at 12n 1, (n=integer). By increasing the number of samples in a sector, it is also possible to suppress the lower order harmonics and a nearly sinusoidal voltage can be obtained. This is possible to achieve at a low switching frequency of the inverters. At the same time, a dodecagon is closer to a circle than a hexagon; so the linear modulation range is extended by about 6.6% compared to the hexagonal case. For a 50 Hz rated frequency operation, under constant V/f ratio, the linear modulation can be achieved upto a frequency of 48.3 Hz. Also, the harmonics of the order 6n 1, (n=odd) are absent in the over-modulation region. Maximum fundamental voltage is obtained from this inverter at the end of over-modulation region, where the phase voltage becomes a 12-step waveform. The present work is developed on dodecagonal space vector diagrams. The entire work can be summarized and explained through Fig. 1. This figure shows the development of hexagonal and dodecagonal space vector diagrams. It is known that, 3-level and 5-level space vector diagrams have been developed as an improvement over 2-level ones. They Figure 1: Development of hexagonal and dodecagonal space vector diagrams have better harmonic performance, reduced dv/dt stress on the motor and devices, better electromagnetic compatibility and improvement of efficiency over 2-level space vector diagrams. This happens because the instantaneous error between the reference vector and the switching vectors reduces, as the space vector density increases in the diagram. This is shown at the top of the figure. In the bottom part, the development of the dodecagonal space vector diagram is shown, which is the contribution of this thesis work. This is explained in brief in the following lines. Initially, a space vector diagram is proposed which switches on hexagonal space vectors in lower-modulation region and dodecagonal space vectors in the higher modulation region. As the reference vector length increases, voltage vectors at the vertices of the outer dodecagon and the vertices from the outer most hexagon is used for PWM control. This results in highly suppressed 5th and 7th order harmonics thereby improving the harmonic profile of the motor current. This leads to the 12-step operation at rated voltage where all the 5th and 7th order harmonics are completely eliminated. At the same time, the linear range of modulation extends upto 96.6% of base speed. Because of this, and the high degree of suppression of lower order harmonics, smooth acceleration of the motor upto rated speed is possible. The presence of multilevel space vector structure also limits the switching frequency of the inverters. In the next work, the single dodecagonal space vector diagram is improved upon to form two concentric dodecagons spanning the space vector plane (Fig. 1). The radius of the outer dodecagon is double the inner one. It reduces the device rating and the dv/dt stress on the devices to half compared to existing 12-sided schemes. The entire space vector diagram is divided into smaller sized isosceles triangles. PWM switching on these smaller triangles reduces the inverter switching frequency without compromising on the output voltage quality. The space vector diagram is further refined to accommodate six concentric dodecagons in the space vector plane (Fig. 1). Here the space vector diagram is characterized by alternately placed dodecagons which become closer to each other at higher radii. As such the harmonics in the phase voltage are reduced, in particular at higher modulation indices. At the same time, because of the dodecagonal space vector structure, all the 6n ± 1, (n=odd) harmonics are eliminated from the phase voltage. A nearly sinusoidal phase voltage can be generated without resorting to high frequency switching of the inverters. The above space vector diagrams are developed using different inverter circuits. The first work is developed from cascaded combination of three 2-level inverters, while the second and third works use 3-level NPC inverters feeding an open end induction motor drive. The circuit topologies are explained in detail in the respective chapters. Apart from this, PWM switching schemes and detailed analysis on duty cycle calculations using the concept of volt-second balance are also presented. They show that with proper switching schemes, the proposed configurations can substantially reduce the overall loss of the inverter. Other operational issues like capacitor voltage balancing of 3-level NPC inverters and improvement of input current drawn from the grid are also covered. All the above propositions are first simulated by MATLAB and subsequently verified by an experimental laboratory prototype. Motor current waveforms both at steady state and transient conditions during motor acceleration show that the induction motor can be fed from nearly sinusoidal voltage at all operating conditions. Simplified comparative studies are also made with the proposed converters and higher level inverters in terms of output voltage quality and losses. These are some of the constituents for chapters 2, 3 and 4 in this thesis. Additionally, the first chapter also covers a brief survey on some of the recent progresses made in the field of multilevel inverter. The thesis concludes with some interesting ideas for further thought and exploration.

L’électricité prend une place de plus en plus importante dans les systèmes énergétiques embarqués. L’électricité est une forme d’énergie très malléable, facile à transporter et réglable ou transformable avec un très faible taux de pertes. L’énergie électrique, associée à des convertisseurs statiques, est plus facile à maîtriser que, par exemple, l’énergie hydraulique et/ou pneumatique, permettant un réglage plus fin et une réduction des coûts de maintenance. L’évolution de la puissance dans les modèles avioniques est marquante. Avec le nombre croissant de charges électroniques, un avion plus électrique avec un réseau à courant alternatif inclurait un grand nombre de redresseurs AC/DC qui devront respecter les normes de qualité secteur. Une solution pour la réduction de la masse serait de préférer un réseau HVDC (High Voltage DC Bus). Sur les futurs modèles avioniques plus électriques, les concepteurs envisageront des conversions HVDC/DC à partir de l’unité appelée BBCU (Buck Boost Converter Unit). Dans ce cas d’étude, un réseau de distribution en tension continue (±270Vdc) est connecté à un réseau de sécurité basse tension (28Vdc) avec un échange bidirectionnel de puissance pouvant atteindre 10kW. Le convertisseur statique assurant cette liaison représente de nouveaux défis pour l’électronique de puissance en termes de fiabilité, sûreté, détection de panne, rendement et réduction de masse et de coût. Le dimensionnement du convertisseur doit prendre en compte une conception optimale, en aéronautique ce critère est la masse. Dans le processus de dimensionnement et d’optimisation du convertisseur, il est donc impératif de prendre en compte trois facteurs principaux : 1) l’évolution des topologies de conversion, 2) l’évolution des composants actifs et passifs et 3) l’intégration de puissance. La réunion de ces trois facteurs permettra ainsi la miniaturisation des convertisseurs statiques. Dans un premier temps, nous préciserons la démarche adoptée pour le dimensionnement d’un convertisseur en prenant en compte : les topologies actives, les filtres différentiels et le système de refroidissement. Les différents éléments qui composent le convertisseur sont décrits dans un langage informatique orienté objet. Des facteurs de performances seront également introduits afin de faciliter le choix des semi-conducteurs, des condensateurs et du dissipateur pour un convertisseur statique. Dans un deuxième temps, nous présenterons le fonctionnement d’une topologie multicellulaire DC/DC, isolée pour l’application proposée. Nous présenterons les avantages du couplage de différentes phases de ce convertisseur. Nous introduirons les différentes associations des cellules et leurs avantages, possibles grâce à l’isolement, comme la mise en série et en parallèle. Puisque la caractérisation des pertes des semi-conducteurs est essentielle pour le dimensionnement du convertisseur statique, nous proposerons deux approches : un modèle de simulation relativement simple et paramétré à l’aide de seules notices constructeurs ; et une méthode de mesure des pertes dans les semi-conducteurs qui est à la fois précise et compatible avec les composants les plus rapides. En ce qui concerne les composants magnétiques, une surface de réponse des matériaux ferrites sera présentée. Nous allons décrire, par le biais analytique et de simulation, des modèles pour la détermination du champ magnétique à l’intérieur du noyau et des ondulations de courant engendrés. Finalement, en profitant des modèles et des résultats obtenus dans les sections précédentes, nous montrerons le dimensionnement et la réalisation de chaque partie du convertisseur BBCU 100kHz / 10kW. Une perspective d’un design idéal est également présentée. / The electricity is taking a more important place in the embedded systems. The electricity is a very moldable form of energy, easy to transport and adjustable or transformed with a very low losses. The electrical energy, associated with power converters, is easier to control than hydraulic and/or pneumatic energies for example, allowing a finer regulation and a cost cutting of maintenance. The installed power in the avionic models is growing fast. With the increasing number of electronic loads, a more electrical aircraft with an AC network would include a large number of rectifiers AC/DC which will have to respect the quality standards. A solution for the reduction of the mass would be to prefer a HVDC network (High Voltage DC BUS). On the future more electrical aircrafts, the designers will be facing a HVDC/DC power conversion. This is the role of the unit called BBCU (Buck Boost Converter Unit). In our case of study, a distribution network in DC voltage (± 270Vdc) is connected to a security low-voltage network (28Vdc) which includes a bidirectional power exchanges achieving 10kW. The power converter for this connection gives new challenges for the power electronics in terms of reliability, safety, failure detection, efficiency and reduction of mass and cost. The design of the power converter needs to take into account for an optimal design. It is thus imperative to take into account three main factors: 1) the evolution of the power topologies 2) the evolution of the active and passive devices and 3) the power integration. The meeting of these three factors will allow the miniaturization of the power converters. At first, the adopted approach for designing power converters, taking into account the power topology, the differential filters and the cooling system are presented. The various elements which compose the power converter are described in an Object-Oriented Programming. The performance factors will be introduced to facilitate the choice of semiconductors, capacitors and heat-sinks. Secondly, the operation phases of a multicellular isolated DC/DC topology for the proposed application are presented. A discussion of the advantages of the magnetic coupling is also introduced. Thanks to the isolation, different associations of switching cells, series or/and parallel connection, are possible. Knowing the losses of power semiconductors is an essential step to design a power converter, thus two approaches are proposed: 1) a simulation model using a relatively simple model with the datasheets information; and 2) a losses measurement method which is precise and compatible with the fastest devices. As regards the magnetic components, a response surface of ferrite materials will be presented. Some models for the determination of the magnetic field inside the core and the current ripple are also described. Finally, by taking advantage of models and results obtained in the previous sections, the design and the realization of each party of the BBCU power converter 100kHz / 10kW is showed. A perspective of an ideal design is also presented.

Cette thèse porte sur la commande de réseaux multi-terminaux à courant continu (MTDC) basés sur des convertisseurs multiniveaux modulaires (MMCs).Tout d’abord, notre attention se focalise sur l'énergie stockée en interne dans le MMC qui constitue un degré de liberté additionnel apporté par sa topologie complexe. Afin d’en tirer le meilleur parti, les limites de l’énergie interne sont formulées mathématiquement.Afin de maîtriser la dynamique de la tension DC, l’utilisation de ce nouveau degré de liberté s’avère d’une grande importance. Par conséquent, une nouvelle de stratégie de commande, nommée «Virtual Capacitor Control», est proposée. Cette nouvelle méthode de contrôle permet au MMC de se comporter comme s’il possédait un condensateur de taille réglable aux bornes, contribuant ainsi à l’atténuation des fluctuations de la tension DC.Enfin, la portée de l’étude est étendue au réseau MTDC. L'un des défis majeurs pour un tel système est de faire face à une perte soudaine d'une station de convertisseur qui peut entraîner une grande variation de la tension du système. A cet effet, la méthode de statisme de tension est la plus couramment utilisée. Cependant, l'analyse montre que l'action de contrôle souhaitée risque de ne pas être réalisée lorsque la marge disponible de réserve de puissance du convertisseur est insuffisante. Nous proposons donc une nouvelle structure de contrôle de la tension qui permet de fournir différentes actions en fonction du signe de l'écart de la tension suite à une perturbation, associée à un algorithme qui détermine les paramètres de statisme en tenant compte du point de fonctionnement et de la réserve disponible à chaque station. / The scope of this thesis includes control and management of the Modular Multilevel Converter (MMC)-based Multi-Terminal Direct Current (MTDC).At first, our focus is paid on the internally stored energy, which is the important additional degree of freedom brought by the complex topology of MMC. In order to draw out the utmost of this additional degree of freedom, an in-depth analysis of the limits of this internally stored energy is carried out, and they are mathematically formulated.Then, this degree of freedom of the MMC is used to provide a completely new solution to improve the DC voltage dynamics. A novel control strategy, named Virtual Capacitor Control, is proposed. Under this control, the MMC behaves as if there were a physical capacitor whose size is adjustable. Thus, it is possible to virtually increase the equivalent capacitance of the DC grid to mitigate the DC voltage fluctuations in MTDC systems.Finally, the scope is extended to MMC-based MTDC grid. One of the crucial challenges for such system is to cope with a sudden loss of a converter station which may lead to a great variation of the system voltage. The voltage droop method is commonly used for this purpose. The analysis shows that the desired control action may not be exerted when the available headroom of the converter stations are insufficient. We thus propose a novel voltage droop control structure which permits to provide different actions depending on the sign of DC voltage deviation caused by the disturbance of system voltage as well as an algorithm that determines the droop parameters taking into account the operating point and the available headroom of each station.

Modular multilevel converters (MMCs) are the preferred converter solution in flexible ac transmission systems (FACTS) and high-voltage direct current (HVDC) applications. This is due to the high quality of the voltage and current signals, lower overall losses, and fewer problems with switching-related EMI. However, without an efficient and fast data recording system, the sampled data from current and voltage measurement boards can cause long latencies in the control system and make it difficult to analyze the operation of MMCs. In this thesis, a filed programmable gate array (FPGA)-based closed-loop control, and a high-speed data recording system is developed for a low-power singlephase MMC prototype. In the prototype, a data-transmission scheme based on the RS485 (TIA/EIA- 485) standard exists. This protocol offers a robust solution for transmitting data over noisy environments. A direct memory access (DMA) scheme is utilized to transmit sampled data from the programmable logic (PL) to the processing subsystem (PS) in the Zynq-7000 SOC. Moreover, an asymmetric multiprocessing (AMP) mechanism was implemented on the two processor cores in the PS. The first processor controls the power transmission to and from the power grid, and the second processor runs the ethernet application to transmit sampled data to the computer using MATLAB. For the closed-loop control of this MMC prototype, a phase-locked loop (PLL), a proportional resonant (PR) current controller, and an energy control loop for capacitor voltage balancing and control are implemented. The results showed that the output power of this single-phase MMC prototype is under control and each sub-module capacitor voltage is balanced and charged to the desired value. The sampled data can be recorded from the computer through the implemented data recording system at 25.6Mbps. Moreover, a dynamic oscilloscope function is developed in MATLAB using this online data recording scheme. / Modulära multilevel-omvandlare (MMC) är den föredragna omvandlarlösningen i flexibla växelströmstransmissionssystem (FACTS) och applikationer med högspänningslikström (HVDC). Detta beror på den höga kvaliteten på spännings- och strömsignalerna, lägre totala förluster och färre problem med omkopplingsrelaterad EMI. Utan ett effektivt och snabbt dataregistreringssystem kan dock samplade data från ström- och spänningsmätkort orsaka långa latenser i styrsystemet och göra det svårt att analysera driften av MMC:er. I denna avhandling utvecklas en FPGA-baserad styrning med sluten slinga och ett höghastighetsdataregistreringssystem för en lågeffekts enfas MMCprototyp. I prototypen finns ett dataöverföringssystem baserat på standarden RS485 (TIA/EIA-485). Detta protokoll erbjuder en robust lösning för att överföra data över bullriga miljöer. Ett schema för direkt minnesåtkomst (DMA) används för att överföra samplade data från den programmerbara logiken (PL) till bearbetningsundersystemet (PS) i Zynq-7000 SOC. Dessutom implementerades en asymmetrisk multiprocessing (AMP)-mekanism på de två processorkärnorna i PS. Den första processorn styr kraftöverföringen till och från elnätet, och den andra processorn kör ethernetapplikationen för att överföra samplade data till datorn med MATLAB. För styrning med sluten slinga av denna MMC-prototyp implementeras en faslåst slinga (PLL), en proportionell resonansströmkontroller (PR) och en energikontrollslinga för balansering och kontroll av kondensatorspänning. Resultaten visade att uteffekten från denna enfasiga MMC-prototyp är under kontroll och varje undermoduls kondensatorspänning är balanserad och laddad till önskat värde. Samplade data kan spelas in från datorn genom det implementerade dataregistreringssystemet vid 25,6 Mbps. Dessutom utvecklas en dynamisk oscilloskopfunktion i MATLAB med hjälp av detta onlinedataregistreringsschema.