The nano-age has already begun, where typical feature dimensions are smaller than 100nm. The operating frequency is expected to increase up to 12 GHz, and a single chip will contain over 12 billion transistors in 2020, as given by the International Technology Roadmap for Semiconductors (ITRS) initiative. ITRS also predicts that the scaling of CMOS devices and process technology, as it is known today, will become much more difficult as the industry advances towards the 16nm technology node and further. This aggressive scaling of CMOS technology has pushed the devices to their physical limits. Design goals are governed by several factors other than power, performance and area such as process variations, radiation induced soft errors, and aging degradation mechanisms. These new design challenges have a strong impact on the parametric yield of nanometer digital circuits and also result in functional yield losses in variation-sensitive digital circuits such as Static Random Access Memory (SRAM) and flip-flops. Moreover, sub-threshold SRAM and flip-flops circuits, which are aggravated by the strong demand for lower power consumption, show larger sensitivity to these challenges which reduces their robustness and yield. Accordingly, it is not surprising that the ITRS considers variability and reliability as the most challenging obstacles for nanometer digital circuits robust design. Soft errors are considered one of the main reliability and robustness concerns in SRAM arrays in sub-100nm technologies due to low operating voltage, small node capacitance, and high packing density. The SRAM arrays soft errors immunity is also affected by process variations. We develop statistical design-oriented soft errors immunity variations models for super-threshold and sub-threshold SRAM cells accounting for die-to-die variations and within-die variations. This work provides new design insights and highlights the important design knobs that can be used to reduce the SRAM cells soft errors immunity variations. The developed models are scalable, bias dependent, and only require the knowledge of easily measurable parameters. This makes them useful in early design exploration, circuit optimization as well as technology prediction. The derived models are verified using Monte Carlo SPICE simulations, referring to an industrial hardware-calibrated 65nm CMOS technology. The demand for higher performance leads to very deep pipelining which means that hundreds of thousands of flip-flops are required to control the data flow under strict timing constraints. A violation of the timing constraints at a flip-flop can result in latching incorrect data causing the overall system to malfunction. In addition, the flip-flops power dissipation represents a considerable fraction of the total power dissipation. Sub-threshold flip-flops are considered the most energy efficient solution for low power applications in which, performance is of secondary importance. Accordingly, statistical gate sizing is conducted to different flip-flops topologies for timing yield improvement of super-threshold flip-flops and power yield improvement of sub-threshold flip-flops. Following that, a comparative analysis between these flip-flops topologies considering the required overhead for yield improvement is performed. This comparative analysis provides useful recommendations that help flip-flops designers on selecting the best flip-flops topology that satisfies their system specifications while taking the process variations impact and robustness requirements into account. Adaptive Body Bias (ABB) allows the tuning of the transistor threshold voltage, Vt, by controlling the transistor body voltage. A forward body bias reduces Vt, increasing the device speed at the expense of increased leakage power. Alternatively, a reverse body bias increases Vt, reducing the leakage power but slowing the device. Therefore, the impact of process variations is mitigated by speeding up slow and less leaky devices or slowing down devices that are fast and highly leaky. Practically, the implementation of the ABB is desirable to bias each device in a design independently, to mitigate within-die variations. However, supplying so many separate voltages inside a die results in a large area overhead. On the other hand, using the same body bias for all devices on the same die limits its capability to compensate for within-die variations. Thus, the granularity level of the ABB scheme is a trade-off between the within-die variations compensation capability and the associated area overhead. This work introduces new ABB circuits that exhibit lower area overhead by a factor of 143X than that of previous ABB circuits. In addition, these ABB circuits are resolution free since no digital-to-analog converters or analog-to-digital converters are required on their implementations. These ABB circuits are adopted to high performance critical paths, emulating a real microprocessor architecture, for process variations compensation and also adopted to SRAM arrays, for Negative Bias Temperature Instability (NBTI) aging and process variations compensation. The effectiveness of the new ABB circuits is verified by post layout simulation results and test chip measurements using triple-well 65nm CMOS technology. The highly capacitive nodes of wide fan-in dynamic circuits and SRAM bitlines limit the performance of these circuits. In addition, process variations mitigation by statistical gate sizing increases this capacitance further and fails in achieving the target yield improvement. We propose new negative capacitance circuits that reduce the overall parasitic capacitance of these highly capacitive nodes. These negative capacitance circuits are adopted to wide fan-in dynamic circuits for timing yield improvement up to 99.87% and to SRAM arrays for read access yield improvement up to 100%. The area and power overheads of these new negative capacitance circuits are amortized over the large die area of the microprocessor and the SRAM array. The effectiveness of the new negative capacitance circuits is verified by post layout simulation results and test chip measurements using 65nm CMOS technology.

<div>In this work, we investigate the trade-off between scalability and reliability for next generation logic-transistors i.e. Gate-All-Around (GAA)-FET, Multi-Bridge-Channel (MBC)-FET. First, we analyze the electronic properties (i.e. bandgap and</div><div>quantum conductance) of ultra-thin silicon (Si) channel i.e. nano-wire and nano-sheet based on first principle simulation. In addition, we study the influence of interface</div><div>states (or dangling bonds) at Si-SiO₂ interface. Second, we investigate the impact of bandgap change and interface states on GAA-FETs and MBC-FETs characteristics by</div><div>employing Non-equilibrium Green's Function based device simulation. In addition to that, we calculate the activation energy of Si-H bond dissociation at Si-SiO₂ interface for different Si nano-wire/sheet thickness and different oxide electric-field. Utilizing these thickness dependent activation energies for corresponding oxide electric-field, in conjunction with reaction-diffusion model, we compute the characteristics shift and analyze the negative bias temperature instability in GAA-FET and MBC-FET. Based on our analysis, we estimate the operational voltage of these transistors for a life-time of 10 years and the ON current of the device at iso-OFF-current condition. For example, for channel length of 5 nm and thickness < 5 nm the safe operating voltage needs to be < 0.55V. Furthermore, our analysis suggests that the benefit of Si thickness scaling can potentially be suppressed for obtaining a desired life-time of GAA-FET and MBC-FET.</div>

Afin de réaliser correctement leur fonction, certains blocs analogiques ou numériques comme les miroirs de courant ou les SRAM, nécessitent des paires de transistors MOS électriquement identiques. Cependant, les dispositifs sur silicium, même appariés, subissent des variations locales aléatoires ce qui fait varier leurs performances électriques. Ce phénomène est connu sous le nom désappariement. L'objectif de cette thèse est de comprendre les causes physiques de ce désappariement, de le quantifier et de proposer des solutions pour le réduire. Dans ce contexte, quatre thèmes principaux sont développés. Le premier thème se focalise sur l'optimisation des méthodologies de mesures des phénomènes de désappariement. Une nouvelle méthode de mesure du désappariement de Vt et de β ainsi qu'un nouveau modèle de désappariement de ID sont proposés, analysés et appliqués à des données mesurées sur des technologies 28nm Bulk et FD SOI. Le second thème se concentre sur la caractérisation des différentes configurations de transistor MOS afin de proposer l'architecture optimale en fonction des applications visées. Ainsi, la possibilité de remplacer le LDEMOS par une configuration cascode est analysée en détail. Le troisième thème se focalise sur l'analyse et la modélisation des phénomènes de désappariement des transistors MOS avancés. Trois aspects sont analysés : 1) l'introduction du Ge dans le canal P des technologies 28nm BULK, 2) la suppression de la contribution de la grille sur le désappariement de Vt en utilisant la technologie 20 nm métal-Gate-Last 3) un descriptif des principaux contributeurs au désappariement de Vt, β et ID dans les technologies 28 et 14nm FD SOI. Le dernier thème traite du comportement du désappariement des transistors MOS après vieillissement. Un vieillissement NBTI a été appliqué sur des PMOS de la technologie 28nm FD SOI. Des modèles de comportement de Vt et de β en fonction du nombre de charges fixes ou d'états d'interfaces induits à l'interface Si/SiO2 ou dans l'oxyde sont proposés et analysés. / For correct operation, certain analog and digital circuits, such as current mirrors or SRAM, require pairs of MOS transistors that are electrically identical. Real devices, however, suffer from random local variations in the electrical parameters, a problem referred to as mismatch. The aim of this thesis is to understand the physical causes of mismatch, to quantify this phenomenon, and to propose solutions that enable to reduce its effects. In this context, four major areas are treated. The first one focuses on the optimization of mismatch measurement methodologies. A new technique for the measurement of Vt and β mismatch and an ID mismatch model are proposed, analyzed and applied to experimental data for 28 nm Bulk and FD SOI technologies. The second area focuses on the characterization of different configurations of MOS transistors in order to propose design architectures that are optimized for certain applications. Specifically, the possibility of replacing LDEMOS with transistors in cascode configuration is analyzed. The third area focuses on the analysis and modeling of mismatch phenomena in advanced Bulk and SOI transistors. Three aspects are analyzed: 1) the impact of the introduction of germanium in P channel of 28nm BULK transistors; 2) the elimination of the metal gate contribution to Vt mismatch by using 20nm Gate-last Bulk technology; 3) a descriptive study of the principal contributions to Vt, β and ID mismatch in 28 and 14 nm FD SOI technologies. The last area treats the mismatch trends with transistor aging. NBTI stress tests were applied to PMOS 28nm FD SOI transistors. Models of the Vt and β mismatch trends as a function of the induced interface traps and fixed charges at the Si/SiO2 interface and in the oxide were developed and discussed.

La miniaturisation croissante des circuits intégrés entraîne une augmentation de la complexité des procédés de<br />fabrication où chaque nouvelle étape peut influer la fiabilité du composant. Les fabricants de semi-conducteurs<br />doivent garantir un niveau de fiabilité excellent pour garantir les performances à long terme du produit final.<br />Pour cela il est nécessaire de caractériser et modéliser les différents mécanismes de défaillance au niveau du<br />transistor MOSFET. Ce travail de thèse porte spécifiquement sur les mécanismes de dégradation de type «<br />Negative Bias Temperature Instability» communément appelé NBTI.<br />Basé sur la génération d'états d'interface, la génération de charges fixes et de piégeage de trous dans l'oxyde, le<br />modèle de dégradation proposé permet de prédire les accélérations en température et en champ électrique,<br />d'anticiper les phénomènes de relaxation, tout en restant cohérent avec les caractères intrinsèques de chaque<br />défauts et les modifications des matériaux utilisés.<br />Ce travail de thèse ouvre le champ à de nouvelles techniques d'analyse basées sur l'optimisation des méthodes<br />de tests et d'extraction de paramètres dans les oxydes ultra minces en évitant les phénomènes de relaxation qui<br />rendent caduques les techniques conventionnelles. Ainsi, une nouvelle technique dite « à la volée » a été<br />développée, et permet d'associer à la fois la mesure et le stress accéléré à l'aide de trains d'impulsions<br />appropriés.<br />Finalement, une nouvelle méthodologie est développée pour tenir compte des conditions réelles de<br />fonctionnement des transistors, et une approche novatrice de compensation du NBTI est proposée pour des<br />circuits numériques et analogiques.

Ce travail contribue à l'évaluation de la technique de génération de seconde harmonique induite par un champ électrique quasi statique, ou technique EFISHG, appliquée au domaine de la microélectronique. Une description du principe de la technique EFISHG, basé sur l'optique non linéaire, permet d'appréhender l'origine physique de cette méthode. Un état de l'art a permis d'identifier deux champs d'applications liés à la microélectronique : l'analyse de défaillance, via la mesure en temps réelle des variations de champs électriques internes dans les circuits intégrés, et la fiabilité par l'étude du piégeage de charges à l'interface Si/SiO2 et de la dégradation dite de " Negative Bias Temperature Instability " ou NBTI. Ce manuscrit présente les différentes étapes qui ont permis l'élaboration d'un banc de test en vue de l'évaluation de l'applicabilité de la technique EFISHG à ces problématiques. Les résultats expérimentaux obtenus avec ce montage ont permis de mettre en avant les possibilités qu'offre la technique EFISHG à caractériser et à accélérer le vieillissement NBTI.

Ce travail contribue à l’évaluation de la technique de génération de seconde harmonique induite par un champ électrique quasi statique, ou technique EFISHG, appliquée au domaine de la microélectronique. Une description du principe de la technique EFISHG, basé sur l’optique non linéaire, permet d’appréhender l’origine physique de cette méthode. Un état de l’art a permis d’identifier deux champs d’applications liés à la microélectronique : l’analyse de défaillance, via la mesure en temps de réelle des variations de champs électriques internes dans les circuits intégrés, et la fiabilité par l’étude du piégeage de charges à l’interface Si/SiO2 et de la dégradation dite de « Negative Bias Temperature Instability » ou NBTI. Ce manuscrit présente les différentes étapes qui ont permis l’élaboration d’un banc de test en vue de l’évaluation de l’applicabilité de la technique EFISHG à ces problématiques. Les résultats expérimentaux obtenus avec ce montage ont permis de mettre en avant les possibilités qu’offre la technique EFISHG à caractériser et à accélérer le vieillissement NBTI. / This work concerns the elaboration of an industrial method for Single Event Effect (SEE) sensitivity testing on integrated circuits. The concerned SEEs are those produced by heavy ions and are mainly Single Event Upset (SEU) and Single Event Latchup (SEL). The original test approach chosen in this study relies on the use of infrared laser pulses striking the backside of the tested device. Laser pulse and heavy ion interaction with semiconductor materials are described and a presentation of the particle accelerator test and some former laser test methods is also given. Advantages and drawbacks of those two techniques are discussed. The developed experimental setup uses a near infrared fiber coupled Neodyme/YAG pulsed laser. Its different elements are described. Using this tool to characterise the SEU sensitivity of several modern SRAMs has allowed to define a test methodology. Its efficiency is discussed and illustrated by different experimental results.