Η παρούσα διπλωματική εργασία πραγματεύεται τη μελέτη, το σχεδιασμό, την πρσοομοίωση και την κατασκευή κυκλώματος για την οδήγηση και τον έλεγχο στροφών κινητήρα τύπου DC Brushless.Η εργασία αυτή εκπονήθηκε στο εργαστήριο Ηλεκτρομηχανικής Μετατροπής Ενέργειας του τμήματος Ηλεκτρολόγων Μηχανικών και Τεχνολογίας Ηλεκτρονικών Υπολογιστών. Σκοπός της παρούσας εργασίας είναι η μελέτη και η κατασκευή κυκλώματος τριφασικού αντιστροφέα ισχύος για να επιτύχουμε οδήγηση και έλεγχο κινητήρα τύπου DC Brushless. Ο κινητήρας αυτού του τύπου είναι Σύγχρονος κινητήρας Μόνιμου Μαγνήτη. Για το λόγο αυτό το πρώτο πράγμα που μελετήθηκε στην παρούσα εργασία είναι κάποιες θεμελιώδεις ιδιότητες του μαγνητικού πεδίου, καθώς και τα χαρακτηριστικά των μαγνητικών υλικών που χρησιμοποιούνται σε τέτοιους τύπους κινητήρων. Στην συνέχεια αναλύονται οι κινητήρων Brushless DC ως προς την κατασκευή τους καθώς και τη λειτουργία τους. Παρατίθενται οι εξισώσεις που περιγράφουν τη λειτουργία τους και οι χαρακτηριστικές ροπής-ταχύτητας και επιπλέον γίνεται σύγκριση αυτών με κινητήρες άλλων τύπων. Ακολουθεί η περιγραφή της προσομοίωσης του συστήματος η οποία πραγματοποιήθηκε στο πρόγραμμα προσομοίωσης ηλεκτρικών κυκλωμάτων Simulink του Matlab. Αναλύεται η λογική στην οποία βασιστήκαμε για την προσομοίωση και παρατίθενται οι κυματομορφές της τάσης και του ρεύματος σε διάφορα σημεία του κυκλώματος. Έπειτα γίνεται μια θεωρητική ανάλυση του κυκλώματος του αντιστροφέα που κατασκευάστηκε καθώς και όλων των άλλων κυκλωμάτων και στοιχείων που απαιτήθηκαν για τη λειτουργία της διάταξης. Επιπλέον περιγράφεται η μέθοδος παλμοδότησης που χρησιμοποιήθηκε για την έναυση/σβέση των διακοπτικών στοιχείων ισχύος. Τέλος γίνεται αναλυτική παράθεση του τελικού κυκλώματος που κατασκευάστηκε. Προχωράμε με την περιγραφή των ιδιοτήτων και δυνατοτήτων του μικροελεγκτή που χρησιμοποιήθηκε στην πλακέτα μας, καθώς επίσης και με τη λογική που ακολουθήθηκε κατά τον προγραμματισμό του. Τέλος παραθέτονται τα αποτελέσματα των πειραμάτων και τα παλμογραφήματα που ελήφθησαν κατά τη διεξαγωγή τους. Γίνεται σχολιασμός των αποτελεσμάτων αυτών και αξιολόγηση της κατασκευής. / This thesis is focused in the study and development of a Drive System for a DC Brushless motor. This work was conducted in the Laboratory of Electromechanical Energy Conversion, at the department of Electrical and Computer Engineering, in the University of Patras, Greece. DC Brushless motors, have been used in the last years they are used in a number of applications. They combine all the benefits of a DC motor, such as their operation simplicity and their linear characteristics, avoiding the brushes and the necessary excitation of DC motors, making them a suitable choice for low and medium power applications. The main purpose of this project is the Study and Construction of a Three-Phase Voltage Source Inverter for the control of the performance of a DC Brushless Motor by the implementation of a Scalar control. This thesis began with the simulation of the motor, since it is necessary for the understanding of its dynamic behavior. Then an analysis on the design and construction of the required circuit boards is done. Finally the used microcontroller (dsPIC family) was studied thoroughly, before writing the necessary code(C & assembly) for open and closed loop control. Finally, measurements were taken for the open loop control system. Conclusions were made as far as the behavior of the motor and ways to optimize the control were discussed.

A measurement system is to be presented, which is used to obtain the I-V characteristics of a solar cell and to track its temperature during irra-diation before mounting it into a complete array/module. This project presents both the design and implementation of an Electronic load for testing the solar cell under field conditions of 10000 W/m^2, which is able to provide current versus voltage and power versus voltage charac-teristics of a solar cell using a software based model developed in Lab-VIEW. An efficient water cooling method which includes a heat pipe array system is also suggested. This thesis presents the maximum power tracking of a solar cell and the corresponding voltage and current values. In addition, the design of the clamp system provides an easy means of replacing the solar cell during testing.Keywords: Solar cell, Metal Oxide Semiconductor Field Effect Transistor (MOSFET), I-V characteristics, cooling system, solar cell clamp system, LabVIEW, Graphical User Interface (GUI).

The low dimensions of the state-of-the-art nanoscale transistors exhibit increasing quantum mechanical effects, which are no longer negligible. Gate tunneling current is one of such effects, that is responsible for high power consumption and high working temperature in microprocessors. This in turn put limits on further down scaling of devices. Therefore modeling and calculation of tunneling current is of a great interest. This work provides a review of existing models for the calculation of the gate tunneling current in MOSFETs. The quantum mechanical effects are studied with a model, based on a self-consistent solution of the Schrödinger and Poisson equations within the effective mass approximation. The calculation of the tunneling current is focused on models based on the calculation of carrier’s lifetime on quasi-bound states (QBSs). A new method for the determination of carrier’s lifetime is suggested and then the tunneling current is calculated for different samples and compared to measurements. The model is also applied to the extraction of the “tunneling effective mass” of electrons in ultrathin oxynitride gate dielectrics. Ultrathin gate dielectrics (tox<2 nm) consist of only few atomic layers. Therefore, atomic scale deformations at interfaces and within the dielectric could have great influences on the performance of the dielectric layer and consequently on the tunneling current. On the other hand the specific material parameters would be changed due to atomic level deformations at interfaces. A combination of DFT and NEGF formalisms has been applied to the tunneling problem in the second part of this work. Such atomic level ab initio models take atomic level distortions automatically into account. An atomic scale model interface for the Si/SiO2 interface has been constructed and the tunneling currents through Si/SiO2/Si stack structures are calculated. The influence of single and double oxygen vacancies on the tunneling current is investigated. Atomic level distortions caused by a tensile or compression strains on SiO2 layer as well as their influence on the tunneling current are also investigated. / Die vorliegende Arbeit beschäftigt sich mit der Berechnung von Tunnelströmen in MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors). Zu diesem Zweck wurde ein quantenmechanisches Modell, das auf der selbstkonsistenten Lösung der Schrödinger- und Poisson-Gleichungen basiert, entwickelt. Die Gleichungen sind im Rahmen der EMA gelöst worden. Die Lösung der Schrödinger-Gleichung unter offenen Randbedingungen führt zur Berechnung von Ladungsverteilung und Lebensdauer der Ladungsträger in den QBSs. Der Tunnelstrom wurde dann aus diesen Informationen ermittelt. Der Tunnelstrom wurde in verschiedenen Proben mit unterschiedlichen Oxynitrid Gatedielektrika berechnet und mit gemessenen Daten verglichen. Der Vergleich zeigte, dass die effektive Masse sich sowohl mit der Schichtdicke als auch mit dem Stickstoffgehalt ändert. Im zweiten Teil der vorliegenden Arbeit wurde ein atomistisches Modell zur Berechnung des Tunnelstroms verwendet, welche auf der DFT und NEGF basiert. Zuerst wurde ein atomistisches Modell für ein Si/SiO2-Schichtsystem konstruiert. Dann wurde der Tunnelstrom für verschiedene Si/SiO2/Si-Schichtsysteme berechnet. Das Modell ermöglicht die Untersuchung atom-skaliger Verzerrungen und ihren Einfluss auf den Tunnelstrom. Außerdem wurde der Einfluss einer einzelnen und zwei unterschiedlich positionierter neutraler Sauerstoffleerstellen auf den Tunnelstrom berechnet. Zug- und Druckspannungen auf SiO2 führen zur Deformationen in den chemischen Bindungen und ändern den Tunnelstrom. Auch solche Einflüsse sind anhand des atomistischen Modells berechnet worden.

In recent years, the use of first-principles based atomistic modeling technique has become extremely popular to gain better insights on the various locally modulated electronic properties of nano materials and structures. Atomistic modeling offers the benefit of predicting crystal structures, visualizing orbital distribution and electron density, as well as understanding material properties which are hard to access experimentally. The single layer MoS2 has emerged as a suitable choice for the next generation nano devices, owing to its distinctive electrical, optical and mechanical properties like, better electrostatics, increased photo luminescence, higher mechanical flexibility, etc. The realization of decananometer scale digital switches with the single layer MoS2 as the channel may provide many significant advantages such as, high On/Off current ratio, excellent electrostatic control of the gate, low leakage, etc. However, there are quite a few critical issues such as, forming low resistance source/drain contacts, achieving higher effective mobility, ensuring large scale controlled growth, etc. which need to be addressed for successful implementation of the atomically thin transistors in integrated circuits. Recent experimental demonstration showing the coexistence of metallic and semiconducting phases in the same monolayer MoS2, has attracted much attention for its use in ultra-low contact resistance-MoS2 transistors. Howbeit, the electronic structures of the metallic-to-semiconducting phase boundaries, which appear to dictate the carrier injection in such transistors, are not yet well understood. In this work, we first develop the geometrically optimized atomistic models of the 2H-1T′ hetero-phase structures with two distinct phase boundaries, β and γ. We then apply density functional theory to calculate the electronic structures for those optimized geometries. Furthermore, we employ non equilibrium Green’s function formalism to evaluate the transmission spectra and the local density of states in order to assess the Schottky barrier nature of the phase boundaries. Nonetheless, the symmetry of the source-channel and drain-channel junction, is a unique property of a metal-oxide semiconductor field effect transistor (MOSFET), which needs to be preserved while realizing sub-10 nm channel length devices using advanced technology. Employing experimental-findings-driven atomistic modeling technique, we demonstrate that such symmetry might not be preserved in an atomically thin phase-engineered MoS2- based MOSFET. It originates from the two distinct atomic patterns at phase boundaries (β and β*) when the semiconducting phase (channel) is sandwiched between the two metallic phases (source and drain). Next, using first principles based quantum transport calculations we demonstrate that due to the clusterization of “Mo” atoms in 1T′ MoS2, the transmission along the zigzag direction is significantly higher than that in the armchair direction. Moreover, to achieve excellent impedance matching with various metal contacts (such as, “Au”, “Pd”, etc.), we further develop the atomistic models of metal-1T′ MoS2 edge contact geometries and compute their resistance values. Other than the charge carrier transport, analysing the heat transport across the channel is also crucial in designing the ultra-thin next generation transistors. Hence, in this thesis work, we have investigated the electro-thermal transport properties of single layer MoS2, in quasi ballistic regime. Besides the perfect monolayer in its pristine form, we have also considered various line defects which have been experimentally observed in mechanically exfoliated MoS2 samples. Furthermore, a comprehensive study on the phonon thermal conductivity of a suspended monolayer MoS2, has been incorporated in this thesis. The studies presented in this thesis could be useful for understanding the carrier transport in atomically thin devices and designing the ultra-thin next generation transistors.

This work investigates the voltage scaling feasibility of several low voltage SiC MOSFET modules operated as a single series-connected switch using active gate control. Both multilevel and two-level topologies are capable of achieving higher blocking voltages in high-power converter applications. Compared to multilevel topologies, two-level switching topologies are of interest due to less complex circuitry, higher density, and simpler control techniques. In this work, to balance the voltage between series-connected MOSFETs, device turn-off speeds are dynamically controlled on active gate-drivers using active gate control. The implementation of the active gate control technique (specifically, turn-off dv/dt control) is described in this thesis. Experimental results of the voltage balancing behavior across eight 1.7 kV rated SiC MOSFET devices in series (6 kV total dc bus voltage) with the selected active dv/dt control scheme are demonstrated. Finally, the voltage balancing performance and switching behavior of series-connected SiC MOSFET devices are discussed. / Master of Science / According to ABB, 40% of the world's power demand is supplied by electrical energy. Specifically, in 2018, the world's electrical demand has grown by 4% since 2010. The growing need for electric energy makes it increasingly essential for systems that can efficiently and reliably convert and control energy levels for various end applications, such as electric motors, electric vehicles, data centers, and renewable energy systems. Power electronics are systems by which electrical energy is converted to different levels of power (voltage and current) depending on the end application. The use of power electronics systems is critical for controlling the flow of electrical energy in all applications of electric energy generation, transmission, and distribution. Advances in power electronics technologies, such as new control techniques and manufacturability of power semiconductor devices, are enabling improvements to the overall performance of electrical energy conversion systems. Power semiconductor devices, which are used as switches or rectifiers in various power electronic converters, are a critical building block of power electronic systems. In order to enable higher output power capability for converter systems, power semiconductor switches are required to sustain higher levels of voltage and current. Wide bandgap semiconductor devices are a particular new category of power semiconductors that have superior material properties compared to traditional devices such as Silicon (Si) Insulated-Gate Bipolar Junction Transistors (IGBTs). In particular, wide bandgap devices such as Silicon Carbide (SiC) Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) have better ruggedness and thermal capabilities. These properties provide wide bandgap semiconductor devices to operate at higher temperatures and switching frequencies, which is beneficial for maximizing the overall efficiency and volume of power electronic converters. This work investigates a method of scaling up voltage in particular for medium-voltage power conversion, which can be applied for a variety of application areas. SiC MOSFET devices are becoming more attractive for utilization in medium-voltage high-power converter systems due to the need to further improve the efficiency and density of these systems. Rather than using individual high voltage rated semiconductor devices, this thesis demonstrates the effectiveness of using several low voltage rated semiconductor devices connected in series in order to operate them as a single switch. Using low voltage devices as a single series-connected switch rather than a using single high voltage switch can lead to achieving a lower total on-state resistance, expectedly maximizing the overall efficiency of converter systems for which the series-connected semiconductor switches would be applied. In particular, this thesis focuses on the implementation of a newer approach of compensating for the natural unbalance in voltage between series-connected devices. An active gate control method is used for monitoring and regulating the switching speed of several devices operated in series in this work. The objective of this thesis is to investigate the feasibility of this method in order to achieve up to 6 kV total dc bus voltage using eight series-connected SiC MOSFET devices.

Les résonateurs électromécaniques (MEMS), de part leurs bonnes performances, leur petite taille, ou encore leurs possibilités d'intégration au plus proche des transistors, présentent un fort potentiel pour le remplacement des quartz dans les applications de référence de temps.<br />Dans ce contexte, nous proposons de développer des résonateurs électromécaniques en vue d'une intégration « front-end », pour la réalisation d'oscillateurs intégrés. Ainsi, nous avons fabriqué des démonstrateurs à partir des briques de base de la technologie CMOS Silicon On Nothing, en phase de R&D à STMicroelectronics. Du fait de la petite taille des composants, nous avons utilisé un transistor à grille résonante pour amplifier la détection de la résonance. Ainsi, des développements technologiques spécifiques ont permis de fabriquer les résonateurs et leur transistor de détection. La conception des dispositifs a été réalisée à partir du développement d'un modèle électromécanique des résonateurs. Ce modèle est compatible avec les outils de design et peut alors aider à la conception de l'oscillateur MEMS. Nous avons ensuite montré le bon fonctionnement des résonateurs fabriqués, ainsi que celui de l'amplification induite par la<br />détection MOS. Cette démonstration constitue une première, prouvant la fonctionnalité de la détection MOS pour un composant de petite taille, vibrant dans le plan du substrat. Enfin, nous avons validé le modèle électromécanique à partir d'autres modèles ainsi qu'avec les mesures des composants fabriqués.<br />En termes de perspectives, le recours à diverses améliorations permettrait d'obtenir des dispositifs<br />compatibles avec la réalisation d'un oscillateur performant et co-intégré.

La miniaturisation croissante des circuits intégrés entraîne une augmentation de la complexité des procédés de<br />fabrication où chaque nouvelle étape peut influer la fiabilité du composant. Les fabricants de semi-conducteurs<br />doivent garantir un niveau de fiabilité excellent pour garantir les performances à long terme du produit final.<br />Pour cela il est nécessaire de caractériser et modéliser les différents mécanismes de défaillance au niveau du<br />transistor MOSFET. Ce travail de thèse porte spécifiquement sur les mécanismes de dégradation de type «<br />Negative Bias Temperature Instability» communément appelé NBTI.<br />Basé sur la génération d'états d'interface, la génération de charges fixes et de piégeage de trous dans l'oxyde, le<br />modèle de dégradation proposé permet de prédire les accélérations en température et en champ électrique,<br />d'anticiper les phénomènes de relaxation, tout en restant cohérent avec les caractères intrinsèques de chaque<br />défauts et les modifications des matériaux utilisés.<br />Ce travail de thèse ouvre le champ à de nouvelles techniques d'analyse basées sur l'optimisation des méthodes<br />de tests et d'extraction de paramètres dans les oxydes ultra minces en évitant les phénomènes de relaxation qui<br />rendent caduques les techniques conventionnelles. Ainsi, une nouvelle technique dite « à la volée » a été<br />développée, et permet d'associer à la fois la mesure et le stress accéléré à l'aide de trains d'impulsions<br />appropriés.<br />Finalement, une nouvelle méthodologie est développée pour tenir compte des conditions réelles de<br />fonctionnement des transistors, et une approche novatrice de compensation du NBTI est proposée pour des<br />circuits numériques et analogiques.

Cette étude porte sur l'intégration hybride de transistors à un électron (single-electron transistor, SET) dans un noeud technologique CMOS. Les SETs présentent de forts potentiels, en particulier en termes d'économies d'énergies, mais ne peuvent complètement remplacer le CMOS dans les circuits électriques. Cependant, la combinaison des composants SETs et MOS permet de pallier à ce problème, ouvrant la voie à des circuits à très faible puissance dissipée, et à haute densité d'intégration. Cette thèse se propose d'employer pour la réalisation de SETs dans le back-end-of-line (BEOL), c'est-à-dire dans l'oxyde encapsulant les CMOS, le procédé de fabrication nanodamascène, mis au point par C. Dubuc.

La progressivité du claquage des oxydes de grille d'épaisseurs inférieures à 20 nm permet d'envisager une prolongation de la durée de vie des circuits. Cet enjeu majeur de la fiabilité contemporaine requiert des modèles adaptés afin de contrôler la variabilité des paramètres induites par le claquage. Après avoir étudié l'impact d'une fuite de courant sur une couche chargée, nous avons mis au point un modèle bas niveau de simulation par éléments finis, capable de reproduire la dérive des paramètres mesurée sur des dispositifs du nœud 45 nm. Des lois empiriques de ces dérives ont été injectées dans un modèle compact du transistor dégradé, simplifié par nos observations originales de la dépolarisation du canal et de la répartition des courants. Finalement nous avons simulé l'impact du claquage sur le fonctionnement de circuits simples et estimés la dérive de leurs paramètres tels que l'augmentation de la consommation due au claquage. / Breakdown (BD) progressivity for oxides thicker than 20nm may allow circuit lifetime extension; for design purpose and reliability questions, it is now very important to include soft BD failure in compact models in order to predict circuit's parameters variability. After studying the impact of current leakage on a charged layer, we set up a low level simulation model, able to reproduce parameters deviation measured on MOSFET from the 45nm node. Empirical laws of parameter's variability due to this degradation have been used to build up a compact model of damaged device. Our observations have allowed several improvements of BD understanding and led to major simplifications in BD compact modelling. Our simulations of small circuits show a good agreement with published measures and allow an estimation of BD impact on circuits, such as circuit's parameters deviation and power consumption increase estimation.

The low dimensions of the state-of-the-art nanoscale transistors exhibit increasing quantum mechanical effects, which are no longer negligible. Gate tunneling current is one of such effects, that is responsible for high power consumption and high working temperature in microprocessors. This in turn put limits on further down scaling of devices. Therefore modeling and calculation of tunneling current is of a great interest. This work provides a review of existing models for the calculation of the gate tunneling current in MOSFETs. The quantum mechanical effects are studied with a model, based on a self-consistent solution of the Schrödinger and Poisson equations within the effective mass approximation. The calculation of the tunneling current is focused on models based on the calculation of carrier’s lifetime on quasi-bound states (QBSs). A new method for the determination of carrier’s lifetime is suggested and then the tunneling current is calculated for different samples and compared to measurements. The model is also applied to the extraction of the “tunneling effective mass” of electrons in ultrathin oxynitride gate dielectrics. Ultrathin gate dielectrics (tox<2 nm) consist of only few atomic layers. Therefore, atomic scale deformations at interfaces and within the dielectric could have great influences on the performance of the dielectric layer and consequently on the tunneling current. On the other hand the specific material parameters would be changed due to atomic level deformations at interfaces. A combination of DFT and NEGF formalisms has been applied to the tunneling problem in the second part of this work. Such atomic level ab initio models take atomic level distortions automatically into account. An atomic scale model interface for the Si/SiO2 interface has been constructed and the tunneling currents through Si/SiO2/Si stack structures are calculated. The influence of single and double oxygen vacancies on the tunneling current is investigated. Atomic level distortions caused by a tensile or compression strains on SiO2 layer as well as their influence on the tunneling current are also investigated. / Die vorliegende Arbeit beschäftigt sich mit der Berechnung von Tunnelströmen in MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors). Zu diesem Zweck wurde ein quantenmechanisches Modell, das auf der selbstkonsistenten Lösung der Schrödinger- und Poisson-Gleichungen basiert, entwickelt. Die Gleichungen sind im Rahmen der EMA gelöst worden. Die Lösung der Schrödinger-Gleichung unter offenen Randbedingungen führt zur Berechnung von Ladungsverteilung und Lebensdauer der Ladungsträger in den QBSs. Der Tunnelstrom wurde dann aus diesen Informationen ermittelt. Der Tunnelstrom wurde in verschiedenen Proben mit unterschiedlichen Oxynitrid Gatedielektrika berechnet und mit gemessenen Daten verglichen. Der Vergleich zeigte, dass die effektive Masse sich sowohl mit der Schichtdicke als auch mit dem Stickstoffgehalt ändert. Im zweiten Teil der vorliegenden Arbeit wurde ein atomistisches Modell zur Berechnung des Tunnelstroms verwendet, welche auf der DFT und NEGF basiert. Zuerst wurde ein atomistisches Modell für ein Si/SiO2-Schichtsystem konstruiert. Dann wurde der Tunnelstrom für verschiedene Si/SiO2/Si-Schichtsysteme berechnet. Das Modell ermöglicht die Untersuchung atom-skaliger Verzerrungen und ihren Einfluss auf den Tunnelstrom. Außerdem wurde der Einfluss einer einzelnen und zwei unterschiedlich positionierter neutraler Sauerstoffleerstellen auf den Tunnelstrom berechnet. Zug- und Druckspannungen auf SiO2 führen zur Deformationen in den chemischen Bindungen und ändern den Tunnelstrom. Auch solche Einflüsse sind anhand des atomistischen Modells berechnet worden.