The iron ore mining industry makes use of various processes that result in the release of airborne dust into the surrounding atmosphere where workers are exposed, to produce a final product. The deposition in the lung and toxicological influences of airborne dust can be determined by their physical- and chemical characteristics. The Occupational Health and Safety Act (OHSA) regulations for hazardous chemical substances have no current system of how the physical- and chemical properties of particulates originating from specific areas will influence a worker‘s exposure and health, especially for ultrafine particles (UFP). It is therefore imperative to characterise airborne dust containing micrometer and UFP size particles originating from specific areas to determine if there are physical- and chemical characteristics that may or may not have an influence on the workers‘ health. Aim: This pilot study is aimed at the physical- and chemical characterisation of the airborne iron ore dust generated at the process areas of an opencast iron ore mine. Method: Sampled areas included the Primary-secondary crusher, Tertiary crusher, Quaternary crusher and Sifting house. Gravimetric sampling was conducted through the use of static inhalable- and respirable samplers in conjunction with optical- and condensation particle counters that were placed near airborne dust- emitting sources. Physical- and chemical characterisation was done with the use of scanning electron microscopy (SEM) and energy dispersive X-ray spectroscopy (EDS). Results: The results found in the study indicate high mass concentration levels of inhalable dust at all four process areas, as well as high levels of respirable dust found at the primary- secondary crusher area. Particle size distribution optical particle counter (OPC) results indicate that the majority of particles at all four process areas are in the region of 0.3 μm in size. Condensation particle counter (CPC) results integrated with OPC results indicate that at the primarysecondary and Tertiary crushers the majority of particles are found to be in the size fraction <0.3 μm. SEM analysis indicates that particle agglomeration largely occurs in the airborne iron ore dust. Particle splinters originating from larger particle collisions and breakages are present in the airborne dust. EDS analysis indicates that the elemental majority of the airborne iron ore dust consists of iron, oxygen, carbon, aluminium, silicon, potassium and calcium. The elemental percentages differ from each process area where an increase in iron and decrease in impurities can be seen as the ore moves through the beneficiation process from the Primary-secondary crusher to the Sifting house. Conclusion: The results obtained from the physical- and chemical properties of the airborne iron ore dust indicate high risk of over-exposure to the respiratory system, as well as possible ultrafine particle systemic exposure, that may overwhelm the physiological defense mechanisms of the human body and lead to reactive oxygen species (ROS) formation and the development of pathologies such as siderosis, silicasiderosis and lung cancer. / MSc (Occupational Hygiene), North-West University, Potchefstroom Campus, 2014

No description available.

Biosensors have a multitude of important applications in basic research, environmental monitoring, biodefense, and medicine. This research aims to show that Ionic Self-Assembled Multilayers (ISAMs) adsorbed on Long Period Gratings (LPGs) can serve as a highly sensitive, robust, inexpensive optical-based biosensor platform. The ISAM technique is a layer-by-layer deposition method that builds nanometer-thick films based on the principle of Coulomb attraction between oppositely charged polyelectrolyte solutions while LPGs cause strong attenuation bands that enable an optical fiber to be extremely sensitive to changes in the surrounding environment. LPGs have been shown to be highly sensitive to the adsorption of nanoscale self-assembled films on the optical fiber cladding surface. In this work, we utilize Turnaround Point (TAP) LPGs, which possess even greater sensitivity than standard LPGs. This thesis focuses on evaluation of approaches to increasing the sensitivity of the sensor platfom, implementation of a biosensor for detection of several biomolecules, and preliminary evaluation of the potential for pH sensing. For a thin-film coated TAP LPG, we have demonstrated that shifts in the transmitted light intensity at the resonant wavelength of the LPG can result from the variation in film thickness and/or refractive index. We have observed decreases in intensity as large a 7 dB for one bilayer of ISAM film (~1 nm), which corresponds to an 80% decrease in the transmitted light intensity at the resonant wavelength. We have also shown that the sensitivity of the TAP LPG sensor can be increased by implementing nm-thick ISAM films that have a refractive index greater than silica. Furthermore, it is shown that incorporation of silica nanoparticles into the ISAM films significantly increases sensitivity through increased surface area and thickness. The biotin-streptavidin system was used as a model for implementaion and optimization of the ISAM-coated TAP LPG biosensor platform. Through evaluation of various biotin derivatives to maximize the amount functionalized onto the ISAM film, optimization of the ISAM film properties, and use of LPGs designed for higher sensitivity, the minimum detectable concentration of streptavidin was decreased from 0.0125 mg/ml to 12.0 ng/ml. The biosensor platform was then tested on prostate specific antigen (PSA), which is used as a clinical marker for early diagnosis of potential prostate cancer. Using a direct crosslinking approach of the monoclonal antibody to PSA into the ISAM film, a sensitivity level of 11.64 ng/ml PSA was obtained through combined optimization of the ISAM film and antibody surface coverage. Finally, the potential of ISAM TAP LPGs as pH sensors was examined based on the pH dependent swelling of ISAM films. / Ph. D.

Biosensors have widespread applications in many areas. Currently the Surface Plasmon Resonance (SPR) biosensor is one of the most prevalent types of biosensor. However, it has several disadvantages such as being delicate, expensive, and non-portable. Ionic Self-Assembled Multilayers (ISAMs) adsorbed on Long Period Fiber Gratings (LPGs) provides an attractive platform for building optical sensors, which could potentially overcome the disadvantages of SPR biosensors. The ISAM technique is a type of layer-by-layer deposition technique for building nanoscale thin films. An LPG is a type of fiber device that is sensitive to physical property changes of the ambient environment. LPGs have been extensively investigated for use as optical sensors. We have carried out a study on combining these two techniques to build efficient biosensors. In this thesis, we demonstrate ultra-sensitive LPGs whose attenuation can be changed by 25 dB (~99.7%) over a 48-nm spectral band, with ambient-index changes of only 2.7E-4. The device schematic allows arbitrarily high index sensitivities to be achieved, which makes it an attractive platform for realizing sensors and modulators that respond to small index changes. For a thin-film coated LPG, we find theoretically that the resonant wavelength shift of the LPG can result from either the variation of the thickness of the film and/or the variation of its refractive index. Furthermore, results illustrate that the sensitivity of the sensor could be enhanced using a nm-thick thin-film (e.g. ISAM films) whose refractive index is greater than silica. Experimentally, we demonstrate the fabrication of nm-thick ISAM films deposited on LPGs, which induces dramatic shifts in the resonant wavelength. The refractive index and the thickness of the ISAM film was precisely controlled by altering the relative fraction of the anionic and cationic materials combined with layer-by-layer deposition. Finally, we demonstrate that ISAM-coated LPGs can function effectively as biosensors by using the biotin-streptavidin system. These demonstrations confirm that the ISAM-LPG scheme provides a thermally-stable, reusable, and robust platform for building efficient optical sensors. / Ph. D.

Delay variability poses a formidable challenge in both design and test of nanometer circuits. While process parameter variability is increasing with technology scaling, as circuits are becoming more complex, the dynamic or vector dependent variability is also increasing steadily. In this research, we develop solutions to incorporate the effect of delay variability in delay testing. We focus on two different applications of delay testing. In the first case, delay testing is used for testing the timing performance of a circuit using path based fault models. We show that if dynamic delay variability is not accounted for during the path selection phase, then it can result in targeting a wrong set of paths for test. We have developed efficient techniques to model the effect of two different dynamic effects namely multiple-input switching noise and coupling noise. The basic strategy to incorporate the effect of dynamic delay variability is to estimate the maximum vector delay of a path without being too pessimistic. In the second case, the objective was to increase the defect coverage of reliability defects in the presence of process variations. Such defects cause very small delay changes and hence can easily escape regular tests. We develop a circuit that facilitates accurate control over the capture edge and thus enable faster than at-speed testing. We further develop an efficient path selection algorithm that can select a path that detects the smallest detectable defect at any node in the presence of process variations. / text

ASICs estruturados com leiautes regulares representam uma das soluções para a perda de rendimento de fabricação de circuitos integrados em tecnologias nanométricas causada pela distorção de fotolitografia. Um método de projeto de circuitos integrados ainda mais restritivo resulta em ASICs estruturados configuráveis apenas pelas camadas de vias, que são compostos pela repetição do mesmo modelo de bloco em todas as camadas do leiaute, exceto as camadas de vias. A escolha do modelo de bloco tem grande influência nas características do circuito final, criando a demanda por novas ferramentas de CAD que possam avaliar e comparar tais modelos em seus diversos aspectos. Esta tese descreve um ambiente de CAD baseado em SAT, capaz de avaliar o aspecto de capacidade lógica em padrões de blocos configuráveis por vias. O ambiente proposto é genérico, podendo tratar quaisquer padrões de bloco definido pelo usuário, e se comporta de maneira eficiente quando aplicado aos principais padrões já publicados na literatura. / Structured ASICs with regular layouts comprise a design-based solution for IC manufacturing yield loss in nanometer technologies caused by photolithography distortions. Via-configurable structured ASICs is even a more restrictive digital IC design method, based on the repetition of a block template comprising all layout layers except the vias one. The choice of such a design strategy impacts greatly the final circuit characteristics, arising the need for specific CAD tools to allow template evaluation and comparison in different aspects. This work presents a SAT-based CAD environment for evaluating the logical capacity aspect of via-configurable block templates. The proposed environment is able to support any user-defined template, and behaves efficiently when applied to block templates presented in related literature.

The nano-age has already begun, where typical feature dimensions are smaller than 100nm. The operating frequency is expected to increase up to 12 GHz, and a single chip will contain over 12 billion transistors in 2020, as given by the International Technology Roadmap for Semiconductors (ITRS) initiative. ITRS also predicts that the scaling of CMOS devices and process technology, as it is known today, will become much more difficult as the industry advances towards the 16nm technology node and further. This aggressive scaling of CMOS technology has pushed the devices to their physical limits. Design goals are governed by several factors other than power, performance and area such as process variations, radiation induced soft errors, and aging degradation mechanisms. These new design challenges have a strong impact on the parametric yield of nanometer digital circuits and also result in functional yield losses in variation-sensitive digital circuits such as Static Random Access Memory (SRAM) and flip-flops. Moreover, sub-threshold SRAM and flip-flops circuits, which are aggravated by the strong demand for lower power consumption, show larger sensitivity to these challenges which reduces their robustness and yield. Accordingly, it is not surprising that the ITRS considers variability and reliability as the most challenging obstacles for nanometer digital circuits robust design. Soft errors are considered one of the main reliability and robustness concerns in SRAM arrays in sub-100nm technologies due to low operating voltage, small node capacitance, and high packing density. The SRAM arrays soft errors immunity is also affected by process variations. We develop statistical design-oriented soft errors immunity variations models for super-threshold and sub-threshold SRAM cells accounting for die-to-die variations and within-die variations. This work provides new design insights and highlights the important design knobs that can be used to reduce the SRAM cells soft errors immunity variations. The developed models are scalable, bias dependent, and only require the knowledge of easily measurable parameters. This makes them useful in early design exploration, circuit optimization as well as technology prediction. The derived models are verified using Monte Carlo SPICE simulations, referring to an industrial hardware-calibrated 65nm CMOS technology. The demand for higher performance leads to very deep pipelining which means that hundreds of thousands of flip-flops are required to control the data flow under strict timing constraints. A violation of the timing constraints at a flip-flop can result in latching incorrect data causing the overall system to malfunction. In addition, the flip-flops power dissipation represents a considerable fraction of the total power dissipation. Sub-threshold flip-flops are considered the most energy efficient solution for low power applications in which, performance is of secondary importance. Accordingly, statistical gate sizing is conducted to different flip-flops topologies for timing yield improvement of super-threshold flip-flops and power yield improvement of sub-threshold flip-flops. Following that, a comparative analysis between these flip-flops topologies considering the required overhead for yield improvement is performed. This comparative analysis provides useful recommendations that help flip-flops designers on selecting the best flip-flops topology that satisfies their system specifications while taking the process variations impact and robustness requirements into account. Adaptive Body Bias (ABB) allows the tuning of the transistor threshold voltage, Vt, by controlling the transistor body voltage. A forward body bias reduces Vt, increasing the device speed at the expense of increased leakage power. Alternatively, a reverse body bias increases Vt, reducing the leakage power but slowing the device. Therefore, the impact of process variations is mitigated by speeding up slow and less leaky devices or slowing down devices that are fast and highly leaky. Practically, the implementation of the ABB is desirable to bias each device in a design independently, to mitigate within-die variations. However, supplying so many separate voltages inside a die results in a large area overhead. On the other hand, using the same body bias for all devices on the same die limits its capability to compensate for within-die variations. Thus, the granularity level of the ABB scheme is a trade-off between the within-die variations compensation capability and the associated area overhead. This work introduces new ABB circuits that exhibit lower area overhead by a factor of 143X than that of previous ABB circuits. In addition, these ABB circuits are resolution free since no digital-to-analog converters or analog-to-digital converters are required on their implementations. These ABB circuits are adopted to high performance critical paths, emulating a real microprocessor architecture, for process variations compensation and also adopted to SRAM arrays, for Negative Bias Temperature Instability (NBTI) aging and process variations compensation. The effectiveness of the new ABB circuits is verified by post layout simulation results and test chip measurements using triple-well 65nm CMOS technology. The highly capacitive nodes of wide fan-in dynamic circuits and SRAM bitlines limit the performance of these circuits. In addition, process variations mitigation by statistical gate sizing increases this capacitance further and fails in achieving the target yield improvement. We propose new negative capacitance circuits that reduce the overall parasitic capacitance of these highly capacitive nodes. These negative capacitance circuits are adopted to wide fan-in dynamic circuits for timing yield improvement up to 99.87% and to SRAM arrays for read access yield improvement up to 100%. The area and power overheads of these new negative capacitance circuits are amortized over the large die area of the microprocessor and the SRAM array. The effectiveness of the new negative capacitance circuits is verified by post layout simulation results and test chip measurements using 65nm CMOS technology.

The nano-age has already begun, where typical feature dimensions are smaller than 100nm. The operating frequency is expected to increase up to 12 GHz, and a single chip will contain over 12 billion transistors in 2020, as given by the International Technology Roadmap for Semiconductors (ITRS) initiative. ITRS also predicts that the scaling of CMOS devices and process technology, as it is known today, will become much more difficult as the industry advances towards the 16nm technology node and further. This aggressive scaling of CMOS technology has pushed the devices to their physical limits. Design goals are governed by several factors other than power, performance and area such as process variations, radiation induced soft errors, and aging degradation mechanisms. These new design challenges have a strong impact on the parametric yield of nanometer digital circuits and also result in functional yield losses in variation-sensitive digital circuits such as Static Random Access Memory (SRAM) and flip-flops. Moreover, sub-threshold SRAM and flip-flops circuits, which are aggravated by the strong demand for lower power consumption, show larger sensitivity to these challenges which reduces their robustness and yield. Accordingly, it is not surprising that the ITRS considers variability and reliability as the most challenging obstacles for nanometer digital circuits robust design. Soft errors are considered one of the main reliability and robustness concerns in SRAM arrays in sub-100nm technologies due to low operating voltage, small node capacitance, and high packing density. The SRAM arrays soft errors immunity is also affected by process variations. We develop statistical design-oriented soft errors immunity variations models for super-threshold and sub-threshold SRAM cells accounting for die-to-die variations and within-die variations. This work provides new design insights and highlights the important design knobs that can be used to reduce the SRAM cells soft errors immunity variations. The developed models are scalable, bias dependent, and only require the knowledge of easily measurable parameters. This makes them useful in early design exploration, circuit optimization as well as technology prediction. The derived models are verified using Monte Carlo SPICE simulations, referring to an industrial hardware-calibrated 65nm CMOS technology. The demand for higher performance leads to very deep pipelining which means that hundreds of thousands of flip-flops are required to control the data flow under strict timing constraints. A violation of the timing constraints at a flip-flop can result in latching incorrect data causing the overall system to malfunction. In addition, the flip-flops power dissipation represents a considerable fraction of the total power dissipation. Sub-threshold flip-flops are considered the most energy efficient solution for low power applications in which, performance is of secondary importance. Accordingly, statistical gate sizing is conducted to different flip-flops topologies for timing yield improvement of super-threshold flip-flops and power yield improvement of sub-threshold flip-flops. Following that, a comparative analysis between these flip-flops topologies considering the required overhead for yield improvement is performed. This comparative analysis provides useful recommendations that help flip-flops designers on selecting the best flip-flops topology that satisfies their system specifications while taking the process variations impact and robustness requirements into account. Adaptive Body Bias (ABB) allows the tuning of the transistor threshold voltage, Vt, by controlling the transistor body voltage. A forward body bias reduces Vt, increasing the device speed at the expense of increased leakage power. Alternatively, a reverse body bias increases Vt, reducing the leakage power but slowing the device. Therefore, the impact of process variations is mitigated by speeding up slow and less leaky devices or slowing down devices that are fast and highly leaky. Practically, the implementation of the ABB is desirable to bias each device in a design independently, to mitigate within-die variations. However, supplying so many separate voltages inside a die results in a large area overhead. On the other hand, using the same body bias for all devices on the same die limits its capability to compensate for within-die variations. Thus, the granularity level of the ABB scheme is a trade-off between the within-die variations compensation capability and the associated area overhead. This work introduces new ABB circuits that exhibit lower area overhead by a factor of 143X than that of previous ABB circuits. In addition, these ABB circuits are resolution free since no digital-to-analog converters or analog-to-digital converters are required on their implementations. These ABB circuits are adopted to high performance critical paths, emulating a real microprocessor architecture, for process variations compensation and also adopted to SRAM arrays, for Negative Bias Temperature Instability (NBTI) aging and process variations compensation. The effectiveness of the new ABB circuits is verified by post layout simulation results and test chip measurements using triple-well 65nm CMOS technology. The highly capacitive nodes of wide fan-in dynamic circuits and SRAM bitlines limit the performance of these circuits. In addition, process variations mitigation by statistical gate sizing increases this capacitance further and fails in achieving the target yield improvement. We propose new negative capacitance circuits that reduce the overall parasitic capacitance of these highly capacitive nodes. These negative capacitance circuits are adopted to wide fan-in dynamic circuits for timing yield improvement up to 99.87% and to SRAM arrays for read access yield improvement up to 100%. The area and power overheads of these new negative capacitance circuits are amortized over the large die area of the microprocessor and the SRAM array. The effectiveness of the new negative capacitance circuits is verified by post layout simulation results and test chip measurements using 65nm CMOS technology.

ASICs estruturados com leiautes regulares representam uma das soluções para a perda de rendimento de fabricação de circuitos integrados em tecnologias nanométricas causada pela distorção de fotolitografia. Um método de projeto de circuitos integrados ainda mais restritivo resulta em ASICs estruturados configuráveis apenas pelas camadas de vias, que são compostos pela repetição do mesmo modelo de bloco em todas as camadas do leiaute, exceto as camadas de vias. A escolha do modelo de bloco tem grande influência nas características do circuito final, criando a demanda por novas ferramentas de CAD que possam avaliar e comparar tais modelos em seus diversos aspectos. Esta tese descreve um ambiente de CAD baseado em SAT, capaz de avaliar o aspecto de capacidade lógica em padrões de blocos configuráveis por vias. O ambiente proposto é genérico, podendo tratar quaisquer padrões de bloco definido pelo usuário, e se comporta de maneira eficiente quando aplicado aos principais padrões já publicados na literatura. / Structured ASICs with regular layouts comprise a design-based solution for IC manufacturing yield loss in nanometer technologies caused by photolithography distortions. Via-configurable structured ASICs is even a more restrictive digital IC design method, based on the repetition of a block template comprising all layout layers except the vias one. The choice of such a design strategy impacts greatly the final circuit characteristics, arising the need for specific CAD tools to allow template evaluation and comparison in different aspects. This work presents a SAT-based CAD environment for evaluating the logical capacity aspect of via-configurable block templates. The proposed environment is able to support any user-defined template, and behaves efficiently when applied to block templates presented in related literature.

Made available in DSpace on 2016-06-02T19:56:35Z (GMT). No. of bitstreams: 1 2373.pdf: 7764902 bytes, checksum: 711e8da93c1f36cc76df511c9897a671 (MD5) Previous issue date: 2009-03-12 / Universidade Federal de Sao Carlos / The interest of studies on the development of techniques for removal of particles in the nanosized scale was promoted by concern about air quality and human health, in addition to restrictions on the control of ultrafine particles, wich are more intransigent by environmental laws. Additionally, the increasing application of nanoparticles in various areas of science and technology has stimulated the development of studies on the subject. Amongst the several equipments capable to operate with efficiency on the particle removal, the fibrous filters are distinguished. Such filters are, in principle, capable to act in sub-micrometer scale, but there is little information about its performance in the nano-sized scale. In this work the performance of a polyester filter, of a HEPA cellulose filter, of a quartz microfiber filter and also of cylindrical filtering membrane, provided by Pam-Membranas Seletivas Ltda, were evaluated. The experimental system was able to simulate a contamination of nanometric particles in a stream of ultrapure air, with the aim of investigating the efficiency of filter media in the removal of nanoparticles. The test aerosol was constituted by NaCl polydisperse nanoparticles, ranging from 6.15 to 245.1 nm. The performance of the filter was evaluated through the analysis of the efficiency of removal of nanoparticles, for the counting of particles before and after to cross the filtering media, using the electric mobility technique. This procedure was performed using the TSI Scannig Mobility Particle Sizer (SMPS), model 3936, which provides the particles concentration, in size range. The results, in general, have showed that the filter media loses efficiency with the increasing filtration velocity and increasing particle size, in the ranged studied, indicating the typical behavior of difusional mechanism. The filtering membranes have showed better performance in the removal of particles unlike the others filters analysed there was no tendency to increase the penetration of particles with increasing the velocity of filtration or particle diameter. / O interesse de estudos acerca do desenvolvimento de técnicas de remoção de materiais particulados na escala nanométrica foi impulsionado pela preocupação com a qualidade do ar e da saúde humana, somada às restrições do controle de particulados ultrafinos, cada vez mais intolerantes pelas leis ambientais. Adicionalmente, a crescente aplicação de partículas nanométricas em diversas áreas da ciência e tecnologia estimulou o aprofundamento de estudos sobre o assunto. Dentre os vários equipamentos capazes de operar com eficiência na remoção de partículas ultrafinas, destacam-se os filtros fibrosos. Tais filtros são, em princípio, capazes de atuar em escala submicrométrica, mas as informações referentes ao seu desempenho em escala nanométrica ainda são pouco conhecidas. No presente trabalho avaliou-se o desempenho de filtros de poliéster, de celulose HEPA, de microfibras de quartzo e, também, de membranas filtrantes cilíndricas, fornecidas pela empresa Pam-Membranas Seletivas Ltda. O sistema experimental disponível era capaz de simular uma contaminação de partículas nanométricas em uma corrente de ar ultrapuro, a fim de que, posteriormente, fosse possível investigar a eficiência dos meios filtrantes na operação de remoção das mesmas. O aerossol de teste era constituído por nanopartículas polidispersas de NaCl, produzidas na faixa de diâmetros de 6,15 a 245,1 nm. O desempenho do filtro foi avaliado através da análise da eficiência de remoção das partículas nanométricas, pela contagem das partículas antes e após a passagem pelo meio filtrante, utilizando a técnica de mobilidade elétrica. Tal procedimento foi realizado por meio de um equipamento da TSI, o Scannig Mobility Particle Sizer (SMPS), modelo 3936, que fornece o número de partículas por faixa de tamanho. Os resultados, em geral, mostraram que a eficiência dos meios filtrantes diminui com o aumento da velocidade de filtração e com aumento do diâmetro, na faixa em estudo, indicando o comportamento típico do mecanismo difusional. As membranas apresentaram um melhor desempenho na remoção das partículas, visto que, diferentemente dos demais meios filtrantes analisados, não se observou tendência para o aumento da penetração de partículas, com o aumento da velocidade de filtração ou diâmetros das partículas, sendo que, em relação à faixa de tamanho, a penetração ocorreu de forma aleatória.