No description available.

Abstract The thesis comprises two different IC design projects, which are briefly introduced as follows. The first part is the NIC (Network Interface Controller) design. The NIC implements all of the Media Access Control (MAC) layer functions for transmission and reception of packets in accordance with the IEEE 802.3 standard. The design is compatible with CSMA/CD type Local Area Network, i.e, 100/10 Mbps Ethernet. The second part is a post-amplifier for a 16Mbps infrared transceiver module. We presents a design of the post-amplifier to convert the pre-amplifier output into digital pulses such that the baseband digital codec can further translate the pulses into the format of IrDA protocols. The design of the amplifier is aimed at the VFIR (very fast infrared) which is supposed to provide a 16 Mbps data transmission rate. The circuit design is carried out by TSMC 0.35 um 1P4M CMOS technology. The simulations results of the design meet the required specification of IrDA VFIR.

The thesis is composed of two different IC design projects, which are briefly introduced as follows. The first topic is an area-saving decoder structure for ROMs. In this part of work, we propose a novel 3-dimensional decoding method. The stages of address decoding are drastically shortened. Hence, the delay is reduced as well as the power consumption. The overall transistor count and the delay are thoroughly derived. A physical 256x8 ROM using the proposed decoder is fabricated by UMC 0.5 mm 2P2M CMOS technology. The second part is the NIC (Network Interface Controller) design. The NIC transfers data frames from and to transmitter and receiver buffers in the host memory, respectively. Meanwhile, the transferred data must also comply with the IEEE 802.3 standard. The design is compatible with CSMA/CD type Local Area Network, including 10/100 Mbps Ethernet.

No description available.

ITC/USA 2005 Conference Proceedings / The Forty-First Annual International Telemetering Conference and Technical Exhibition / October 24-27, 2005 / Riviera Hotel & Convention Center, Las Vegas, Nevada / As requirements for the amount of test data continues to increase, instrumentation engineers are under pressure to deploy data acquisition systems that reduce the amount of associated wiring and overall system complexity. Smart sensor buses have been long considered as one approach to address this issue by placing the appropriate signal conditioners close to their respective sensors and providing data back over a common bus. However, the inability to adequately synchronize the operation of the sensor bus to the system master, which is required to correlate analog data measurements, has precluded their use. The ongoing development and deployment of smart sensor buses has reached the phase in which integration into a larger data acquisition system environment must be considered. Smart sensor buses, such as IntelliBus™, have their own unique mode of operation based on a pre-determined sampling schedule, which however, is typically asynchronous to the operation of the (master or controller) data acquisition system and must be accounted for when attempting to synchronize the two systems. IRIG Chapter 4 type methods for inserting data into a format, as exemplified by the handling of MIL-STD-1553 data, could be employed, with the disadvantage of eliminating any knowledge as to when a particular measurement was sampled, unless it is time stamped (similar to the time stamping function that is provided to mark receipt of 1553 command words). This can result in excessive time data as each sensor bus can manage a large number of analog sensor inputs and multiple sensor buses must be accommodated by the data acquisition system. The paper provides an example, using the Boeing developed IntelliBus system and the L3 Communications - Telemetry East NetDAS system, of how correlated data can be acquired from a smart sensor bus as a major subsystem component of a larger integrated data acquisition system. The focus will be specifically on how the IntelliBus schedule can be synchronized to that of the NetDAS formatter. Sample formats will be provided along with a description of how a standalone NetDAS stack and an integrated NetDAS-IntelliBus system would be programmed to create the required output, taking into account the unique sampling characteristics of the sensor bus.

In this thesis, we characterize the proprietary active scanning algorithm of several wireless network interface cards. Our experiments are the first of its kind to observe the complete scanning process as the wireless network interface cards probe all the channels in the 2.4GHz spectrum. We discuss the: 1) correlation of channel popularity during active scanning and access point channel deployment popularity; 2) number of probe request frames statistics on each channel; 3) channel probe order; and 4) dwell time. The knowledge gained from characterizing wireless network interface cards is important for the following reasons: 1) it helps one understand how active scanning is implemented in different hardware and software; 2) it can be useful in identifying a wireless rogue host; 3) it can help implement Active Scanning in network simulators; and 4) it can radically influence research in the familiar fields like link-layer handovers and effective deployment of access points.

Containerization has gained popularity for deploying applications in a lightweight environment. Kubernetes and Docker have gained a lot of dominance for scalable deployments of applications in containers. Usually, kubernetes clusters are deployed within a single shared network. For high availability of the application, multiple kubernetes clusters are deployed in multiple regions, due to which the number of kubernetes clusters keeps on increasing over time. Maintaining and managing mul-tiple kubernetes clusters is a challenging and time-consuming process for system administrators or DevOps engineers. These issues can be addressed by deploying a kubernetes cluster in a multi-region environment. A multi-region kubernetes de-ployment reduces the hassle of handling multiple kubernetes masters by having onlyone master with worker nodes spread across multiple regions. In this thesis, we investigated a multi-region kubernetes cluster’s network performance by deploying a multi-region kubernetes cluster with worker nodes across multiple openstack regions and tunneled using wireguard(a VPN protocol). A literature review on the common factors that influence the network performance in a multi-region deployment is conducted for the network performance metrics. Then, we compared the request-response time of this multi-region kubernetes cluster with the regular kubernetes cluster to evaluate the performance of the deployed multi-region kubernetescluster. The results obtained show that a kubernetes cluster with worker nodes ina single shared network has an average request-response time of 2ms. In contrast, the kubernetes cluster with worker nodes in different openstack projects and regions has an average request-response time of 14.804 ms. This thesis aims to provide a performance comparison of the kubernetes cluster with and without wireguard, fac-tors affecting the performance, and an in-depth understanding of concepts related to kubernetes and wireguard.

This dissertation argues that admission control should be applied as early as possible within a system. To that end, this dissertation examines the benefits and trade-offs involved in applying admission control to a networked computer system at the level of the network interface hardware. Admission control has traditionally been applied in software, after significant resources have already been expended on processing a request. This design decision leads to systems whose algorithmic cost is a function of the load applied to the system, rather than the load admitted to the system. By performing admission control at the network interface, it is possible to develop systems whose algorithmic cost is a function of load admitted to the system, rather than load applied to the system. Such systems are able to deal with excessive applied loads without exhibiting performance degradation. This dissertation first examines existing admission control approaches, focussing on the cost of admission control within those systems. It then goes on to develop a model of system behaviour under overload, and the impact of admission control on that behaviour. A new class of admission control mechanisms which are able to perform load rejection using the network interface hardware are then described, along with a prototype implementation using commodity hardware. A prototype implementation in the FreeBSD operating system is evaluated for a variety of network protocols and performance is compared to the standard FreeBSD implementation. Performance and scalability under overload is significantly improved.

The most studies on ad hoc network mainly focus on TCP (Transmission Control Protocol) of transport layer, the routing of network layer, multi-hop of Data-link layer, and the integration of WWAN and WLAN to increase the load balancing, coverage, and power savings. Nevertheless, in this dissertation, the system performances of four schemes proposed are improved with respect to data-link and network layers. One purpose of the data link layer is to perform error correction or detection. The other is responsible for the way in which different users share the transmission medium. The Medium Access Control (MAC) sublayer is responsible for allowing frames to be sent over the shared media without undue interference with other users. This aspect is referred to as multi-access communications. In the first and third schemes, the FDMA (Frequently-division multiple access) is employed to improve system performance, while in the fourth scheme the CDMA (Code-division multiple access) is used to enhance performance. Network layer has several functions, first is to determine the routing information. A second function is to determine the quality of service. A third function is flow control to avoid network to become congested. In the third scheme, the data-link and network layers have been used to increase system performance. Furthermore, the second scheme mainly concentrates on power savings under wireless sensor network. In ad hoc wireless networks, most data delivery is accomplished through multi-hop routing (hop by hop). This approach may leads to long delay and routing overhead regardless of which routing protocol is used. To overcome this inherent characteristic, this work presents a novel idea adopting dual-card-mode and performing self-organization process with specific IP naming and channel assignment to form a hierarchical star-graph ad hoc network (HSG-ad hoc) which can not only expedite the data transmission but also eliminate the route discovery procedure during data transmission. Therefore, the overall network reliability and stability can be significantly improved. Simulation results show that the proposed approach achieves substantial improvements in terms of average end-to-end delay, throughput, and packet delivery ratio. In a large-scale wireless sensor network, a topology is needed to gather state-based data from sensor network and efficiently aggregate the data given the requirements of balanced load, minimal energy consumption and prolonged network lifetime. In this study, we proposed a ring-based hierarchical clustering scheme (RHC) consisting of four phases: pre-deployment, parent-child relationship building, deployment, and member join phases. Two node types are distributed throughout the network: cluster head nodes (type 1 node) and general sensor nodes (type 2 node). The type 1 node has better battery life, software capability and hardware features than the type 2 node does; therefore, the type 1 node is a better cluster head than type 2 node. Most routing protocols focus mainly on obtaining a workable route without considering network traffic conditions for a mobile ad hoc network. Consequently, real time and multimedia applications do not achieve adequate quality of service (QoS). To support QoS, this work proposes a QoS-aware routing protocol, i.e. QUality of service with Admission control RouTing (QUART), that incorporates an admission control scheme into route discovery and route setup procedures. One variant of QUART, called, QUART-DD, adopts a dual-card dual-signal mechanism to increase system performance. Simulation results indicate that QUART-DD can significantly improve packet delivery ratio and throughput, while having a lower average end-to-end delay than routing protocols without QoS support. The performance of ad hoc wireless network suffers from problems in multi-hop transmission. This study adopts code division to modulate the frame header and the frame payload separately. A common spreading code modulates the frame header, and a special spreading code is negotiated and to modulate the frame payload. A field in the frame header indicates the spreading code used to modulate the successive frame payload. The modulated frame is transparent for every node, enabling many frames to be transmitted simultaneously. To allow the special spreading code negotiation, the RTS/CTS command is modified as ERTS/ECTS, and a spreading code table (SCT) is maintained in every node. Due to the space reuse, the proposed scheme has superior performance in latency and bandwidth utilization, as revealed by the simulation results.

This dissertation argues that admission control should be applied as early as possible within a system. To that end, this dissertation examines the benefits and trade-offs involved in applying admission control to a networked computer system at the level of the network interface hardware. Admission control has traditionally been applied in software, after significant resources have already been expended on processing a request. This design decision leads to systems whose algorithmic cost is a function of the load applied to the system, rather than the load admitted to the system. By performing admission control at the network interface, it is possible to develop systems whose algorithmic cost is a function of load admitted to the system, rather than load applied to the system. Such systems are able to deal with excessive applied loads without exhibiting performance degradation. This dissertation first examines existing admission control approaches, focussing on the cost of admission control within those systems. It then goes on to develop a model of system behaviour under overload, and the impact of admission control on that behaviour. A new class of admission control mechanisms which are able to perform load rejection using the network interface hardware are then described, along with a prototype implementation using commodity hardware. A prototype implementation in the FreeBSD operating system is evaluated for a variety of network protocols and performance is compared to the standard FreeBSD implementation. Performance and scalability under overload is significantly improved.