The first topic of this thesis proposes a 10-bit, 30 Msample/s pipeline analog-to-digital converter (ADC) suitable for digital video broadcasting over handheld (DVB-H) systems. The ADC is based on the 1.5-bit-per-stage pipeline architecture. The proposed design is implement- ed by 0.18 um CMOS technology. The input range is 2 V peak-to-peak differential signals, and the post-layout simulation result shows that the spurious-free dynamic range (SFDR) is 57.85 dBc with a full-scale sinusoidal input at 700 KHz. The maximum power consumption is 37 mW given a 3.3 V power supply. The core area is 0.27 mm2. The second topic is to propose a fully mixed-voltage-tolerant I/O cell implemented using typical CMOS 2P4M 0.35 um process. Unlike traditional mixed-voltage-tolerant I/O cell, the proposed design can transmit and receive the digital signals with voltage levels of 5/3.3/1.8 V. By using stacked PMOS and stacked NMOS at the output stage and a voltage level converter providing appropriate control voltages for the gates of the stacked PMOS, the gate-oxide overstress and hot-carrier degradation are avoided. Moreover, gate-tracking and floating N-well circuits are used to remove the undesirable leakage current paths. The maximum transmitting speed of the proposed I/O cell is 103/120/84 Mbps for the supply voltage of I/O cell at 5/3.3/1.8 V, respectively, given the load of 20 pF.

Video decoders play a very important role in the TV receivers. This is especially true for NTSC-based TVs. The design and implementation of the video decoder with two-line delay comb filter are presented. Moreover, the works includes the low-power SRAM (static random access memory) in the comb filter for storing scanning line data and the low-power small-area I/O cells for transmitting digital data. A digital phase lock loop (PLL) in the proposed video decoder uses a ROM-less 4£c-based direct digital frequency synthesizer (DDFS)-based digital control oscillator to resolve the false locking problem. Two 20-tap transposed FIRs (finite-duration impulse response filter) are used to implement the low pass filters (LPF) in the chrominance demodulator. Besides, the unnecessary decimals of the coefficients of the LPF are truncated to reduce hardware cost. The proposed SRAM takes advantage of a negative word-line voltage controlling the access transistors of the memory cell to reduce the leakage current in the standby mode. Besides, a memory bank partition scheme and a clock gating scheme are also used to save more power. Finally, a fully different concept from current I/O designs is proposed. The novel I/O cell takes advantage of reducing output voltage swing as well as transistors with different threshold voltages such that the area and power consumption of overall chip can be drastically reduced.

This thesis includes two topics. The first topic is a data dispatcher design of a digital image processor for plasma display panels, which can be used in a 42-inch plasma display panel (PDP). The second one is a low-power small-area digital I/O cell design. The data dispatcher is applied to a 42-inch panel, which is produced by AUO corporation, as a test platform. It comprises FPGAs and RAMs to carry out data dispatching. The solution is verified to provide a better image quality, while the cost is also reduced. Regarding the low-power small-area digital I/O cell, we propose a totally different concept in contrast to traditional I/O cells. It is focused on low power consumption and small area. The proposed design is carried out by TSMC 1P5M 0.25 mm CMOS process at 2.5 V power supply. The power consumption is measured to be at least 51.4% less than prior works. The area is proven to be at least 44% more efficient.

The thesis comprises three parts: Part 1 is the design and implementation of a high speed pipelined carry lookahead adder (CLA) ; Part 2 introduces how to build 0.35£gm basic cell library in the Cadence 97¡¦s environment and execute the cell-based design flow by self-built basic cells; Part 3 is the design and implementation of a low-power discrete cosine transform (DCT) processor. Part 1 of this thesis is a 32-bit tree-structured pipelined carry lookahead adder (CLA) constructed by the modified all-N-transistor (ANT) design. Not only the CLA possesses few transistor count, but also occupies small chip size. Moreover, the post- layout simulation results given by TimeMill show that the clock used in the 32-bit CLA can run up to 1.25 GHz. The proposed architecture can be easily expanded for long data addition. Part 2 of this thesis is to describe the procedure of a self-built cell library in detail, and explain how to correctly proceed cell-based design flow by using the self-built basic cell library. Part 3 of this thesis is to implementation of a DCT processor. We carefully observed the operation behavior of Multiply Accumulator (MAC) and improved the power consumption

The thesis is composed of tow topics: a fully bidirectional mixed- voltage-tolerant I/O cell using a new output stage circuit and a sub-3¡ÑVDD wide range fully bidirectional mixed-voltage-tolerant I/O cell. The first topic discloses a mixed-voltage-tolerant I/O cell implemented using 2P4M 0.35 £gm CMOS process, which uses a low static power dynamic gate bias generator providing three different logic voltage levels to the output stage to avoid gate oxide reliability and leakage current. The design also reveals a new output stage circuit, which enhances the output current to resolve the poor driving capability caused by the slow mobility and body effect of the stacked PMOS. The second topic shows a sub-3¡ÑVDD wide range fully bidirectional mixed-voltage-tolerant I/O cell using 1P6M 0.18 £gm CMOS process, which employs a new dynamic gate bias generator and a PAD voltage detector to provide appropriate gate biases. The design includes a new gate tracking circuit and a floating N-well circuit to avoid gate oxide reliability and leakage current, which relaxes the body effect at the output PMOS.

An investigation into the load-settlement behavior of two drilled shafts, founded in shale, is presented. The motivation for this research is to advance the understanding on how drilled shafts react under loading in stiff clays and shales. The objectives of the study are to measure the strengths within the subsurface material at the test site, estimate the unit side shear and unit end bearing of the shale-shaft interaction by running two axial load tests, and compare the results to the current design methods that are used to predict the axial capacity of drilled shafts. A comprehensive field investigation, performed by Fugro Consultants, provided strength profiles of the subsurface material at the test site. Through the cooperation of the Texas Department of Transportation (TxDOT), the Association of Drilled Shaft Contractors, and McKinney Drilling Company, two drilled shafts were installed at a highway construction site in Austin, Texas. The load tests were performed by Loadtest, Inc.; using the patented Osterberg-Cell™ loading technique to axially displace the shafts. Ensoft, Inc. installed strain gauges at multiple levels within the shafts, making it possible to analyze the shaft mobilization during loading. Ultimate end bearing values of about 100- and 120-ksf were measured for Test Shafts #1 and #2, respectively. The current methods for estimating unit end bearing, developed by TxDOT and the Federal Highway Administration, provide fairly accurate predictions when compared to the measured information. The ultimate side resistance obtained near the O-Cell™ in each test was about 20-ksf, however, the measured ultimate side resistance steadily decreased nearing the tip of the shaft. For the zones where the side resistance was believed to be fully mobilized, the TxDOT design method accurately predicts the side resistance. A limited amount of information is currently available for load tests performed in soils with TCP values harder than 2-in per 100 blows. Additional load test information should allow for a stronger correlation between TCP tests and unit resistances for very hard clay-shales, as well as, allowing for further evaluation of the shale-shaft interaction near the shaft tip. The results presented herein demonstrate the effectiveness of the current design methods for drilled shafts and the non-uniformity of side resistance within one- to two-diameters of the shaft tip. / text

Greenhouse gas emissions are one of the critical factors that affect climate change, increasing flooding risk and threatening human life. The use of traditional construction materials is responsible for a higher percentage of global greenhouse gas emissions when compared to the use of sustainable materials in the construction industry. The substitution of current building materials with sustainable materials is essential to reduce greenhouse gas emissions and positively influence climate change when the current construction demand in the world is considered. Wood is one of the primary environmentally friendly construction materials in regard to high carbon storage and low carbon emissions. Cross-laminated timber (CLT) is prefabricated and this type of composite wood material is convenient for constructing middle to high rise buildings because materials are able to be cut to specific specifications which lowers onsite labor time. This research observed the hygrothermal behavior of partially submerged CLT wall panels during the wetting and drying period and simulated the flooding of the panels with a software tool, Wärme Und Feuchte Instationär (WUFI). The higher number of CLT layers caused a slower water penetration rate throughout the layers with a lower water absorption rate corresponding to the first layer than the other layers, so the water was primarily retained in the first layer. Also, water penetration through axial direction significantly decreased due to gravity impact when the height of CLT panels was increased. The visual assessment showed that the 3-day-wetted CLT panel configurations did not show any type of fungi growth through the wetting and drying period. However, both untreated and treated CLT panels with the envelope system did have fungi growth on the drywall after a 20-day-wetting period.