Digital subscriber line (DSL) technology is used to provide high speed Internet access and, more recently, video services over twisted pair lines. Telephone lines have impairments that hinder DSL transmission, and some examples are coils and bridge taps that were introduced to aid voice telephony. Other faults are caused by physical damage that results in open circuits, short circuits or water in the line. Telephone companies have to locate and repair these faults to enable high-speed data services. It is also useful to qualify lines for future DSL service so that a new customer can be promptly informed whether high-speed service can be supplied. <p>This thesis proposes a novel technique called Wideband frequency domain reflectometry (W-FDR) to accurately locate impairments in telephone lines and estimate the reflection magnitude caused by faults. The measurement produces a result similar to the well-known time domain reflectometer (TDR), however, digital signal processing techniques are now applied to provide enhanced resolution and range. In addition to magnitude, the new technique is able to measure reflection angle which can help to determine the nature of the fault (wire in the cable, broken wires, etc). <p>The measurement technique consists of energizing the line with a sinusoid that increases from 50 kHz to 1300 kHz in discrete frequency steps after coherent detection. The amplitude of the reflected signal is recorded as a function of frequency for 2500 equally spaced frequencies. The Fourier transform and some signal processing are then used to estimate the complex reflection coefficient location of the faults in the telephone line. Lines with up to 4 reflection points have been accurately analyzed. <p>Results show distance measurement accuracy better than 1% and phase measurement accuracy better than 10 degrees for line lengths up to 5 km. These measurements exceed the performance of currently available TDR instruments.

Digital subscriber line (DSL) technology is used to provide high speed Internet access and, more recently, video services over twisted pair lines. Telephone lines have impairments that hinder DSL transmission, and some examples are coils and bridge taps that were introduced to aid voice telephony. Other faults are caused by physical damage that results in open circuits, short circuits or water in the line. Telephone companies have to locate and repair these faults to enable high-speed data services. It is also useful to qualify lines for future DSL service so that a new customer can be promptly informed whether high-speed service can be supplied. <p>This thesis proposes a novel technique called Wideband frequency domain reflectometry (W-FDR) to accurately locate impairments in telephone lines and estimate the reflection magnitude caused by faults. The measurement produces a result similar to the well-known time domain reflectometer (TDR), however, digital signal processing techniques are now applied to provide enhanced resolution and range. In addition to magnitude, the new technique is able to measure reflection angle which can help to determine the nature of the fault (wire in the cable, broken wires, etc). <p>The measurement technique consists of energizing the line with a sinusoid that increases from 50 kHz to 1300 kHz in discrete frequency steps after coherent detection. The amplitude of the reflected signal is recorded as a function of frequency for 2500 equally spaced frequencies. The Fourier transform and some signal processing are then used to estimate the complex reflection coefficient location of the faults in the telephone line. Lines with up to 4 reflection points have been accurately analyzed. <p>Results show distance measurement accuracy better than 1% and phase measurement accuracy better than 10 degrees for line lengths up to 5 km. These measurements exceed the performance of currently available TDR instruments.

The emergence of networks-on-chip (NoC) as the communication infrastructure solution for complex multi-core SoCs presents communication synthesis challenges. This dissertation addresses the design and run-time management aspects of communication synthesis. Design reuse and the infeasibility of Intellectual Property (IP) core interface redesign, requires the development of a Core-Network Interface (CNI) which allows them to communicate over the on-chip network. The absence of intelligence amongst the NoC components, entails the introduction of a CNI capable of not only providing basic packetization and depacketization, but also other essential services such as reliability, power management, reconguration and test support. A generic CNI architecture providing these services for NoCs is proposed and evaluated in this dissertation. Rising on-chip communication power costs and reliability concerns due to these, motivate the development of a peak power management technique that is both scalable to dierent NoCs and adaptable to varying trac congurations. A scalable and adaptable peak power management technique - SAPP - is proposed and demonstrated. Latency and throughput improvements observed with SAPP demonstrate its superiority over existing techniques. Increasing design complexity make prediction of design lifetimes dicult. Post SoC deployment, an on-line health monitoring scheme, is essential to maintain con- dence in the correct operation of on-chip cores. The rising design complexity and IP core test costs makes non-concurrent testing of the IP cores infeasible. An on-line scheme capable of managing IP core test in the presence of executing applications is essential. Such a scheme ensures application performance and system power budgets are eciently managed. This dissertation proposes Concurrent On-Line Test (COLT) for NoC-based systems and demonstrates how a robust implementation of COLT using a Test Infrastructure-IP (TI-IP) can be used to maintain condence in the correct operation of the SoC.

The emergence of networks-on-chip (NoC) as the communication infrastructure solution for complex multi-core SoCs presents communication synthesis challenges. This dissertation addresses the design and run-time management aspects of communication synthesis. Design reuse and the infeasibility of Intellectual Property (IP) core interface redesign, requires the development of a Core-Network Interface (CNI) which allows them to communicate over the on-chip network. The absence of intelligence amongst the NoC components, entails the introduction of a CNI capable of not only providing basic packetization and depacketization, but also other essential services such as reliability, power management, reconguration and test support. A generic CNI architecture providing these services for NoCs is proposed and evaluated in this dissertation. Rising on-chip communication power costs and reliability concerns due to these, motivate the development of a peak power management technique that is both scalable to dierent NoCs and adaptable to varying trac congurations. A scalable and adaptable peak power management technique - SAPP - is proposed and demonstrated. Latency and throughput improvements observed with SAPP demonstrate its superiority over existing techniques. Increasing design complexity make prediction of design lifetimes dicult. Post SoC deployment, an on-line health monitoring scheme, is essential to maintain con- dence in the correct operation of on-chip cores. The rising design complexity and IP core test costs makes non-concurrent testing of the IP cores infeasible. An on-line scheme capable of managing IP core test in the presence of executing applications is essential. Such a scheme ensures application performance and system power budgets are eciently managed. This dissertation proposes Concurrent On-Line Test (COLT) for NoC-based systems and demonstrates how a robust implementation of COLT using a Test Infrastructure-IP (TI-IP) can be used to maintain condence in the correct operation of the SoC.

Sistemas embarcados baseados em processadores têm sido largamente aplicados em áreas críticas no que diz respeito à segurança de seres humanos e do meio ambiente. Em tais aplicações, que compreendem desde o controle de freio de carros a missões espaciais, pode ser necessária a execução confiável de todas as funcionalidades do sistema durante longos períodos e em ambientes desconhecidos, hostis ou instáveis. Mesmo em aplicações não críticas, nas quais a confiabilidade do sistema não é um requisito primordial, o usuário final deseja que seu produto apresente comportamento estável e livre de erros. Daí vem a importância de se considerar o auto-teste on-line no projeto dos sistemas embarcados atuais. Entretanto, a crescente complexidade de tais sistemas somada às fortes restrições a que eles estão sujeitos torna o projeto do auto-teste um problema cada vez mais desafiador. Em aplicações de tempo-real a dificuldade é ainda maior, uma vez que, além dos cuidados com as restrições do sistema alvo, deve-se levar em conta o atendimento dos requisitos temporais da aplicação. Entre as técnicas de auto-teste on-line atualmente pesquisadas, uma tem se destacado pela eficácia obtida a um baixo custo de projeto e sem grande impacto no atendimento dos requisitos e restrições do sistema: o auto-teste baseado em software (SBST – Software-Based Self-Test). Neste trabalho, é proposta uma metodologia para o projeto e aplicação de auto-teste on-line para processadores embarcados, considerando-se também aplicações de temporeal. Tal metodologia, denominada STEP (Self-Test for Embedded Processors), tem como base a técnica SBST e prevê o planejamento, a geração e a seleção de rotinas de teste para o processador alvo. O método proposto garante a execução periódica do autoteste, com o menor período permitido pela aplicação de tempo-real, e assegura o atendimento de todas as restrições do sistema embarcado. Além disso, a solução fornecida pelo método alcança uma boa qualidade de teste enquanto auxilia a redução de custos do sistema final. Como estudo de caso, a metodologia proposta é aplicada a diferentes arquiteturas de processadores Java e os resultados obtidos comprovam a eficiência da mesma. Por fim, é apresentada uma ferramenta que implementa a metodologia STEP, automatizando, assim, o projeto e a aplicação de auto-teste on-line para os processadores estudados. / Processor-based embedded systems have been widely used in safety-critical applications. In such applications, which include from cars break control to spatial missions, the whole system operation must be reliable during long periods even within unknown, hostile and unstable environments. In non-critical applications, system reliability is not a prime requirement, but the final user requires an error free product, with stable behavior. Hence, one can realize the importance of on-line self-testing in current embedded systems. Self-testing is becoming an important challenge due to the increasing complexity of the systems allied to their strong constraints. In real-time applications this problem becomes even more complex, since, besides meeting systems constraints, one must take into consideration the application timing requirements. Among all on-line self-testing techniques studied, Software-Based Self-Test (SBST) has been distinguished by its effectiveness, low-cost and small impact on system constraints and requirements. This work proposes a methodology for the design and implementation of on-line self-test in embedded processors, considering real-time applications. Such a methodology, called STEP (Self-Test for Embedded Processors), is based on SBST technique and encloses planning, generation and selection of test routines for the target processor. The proposed method guarantees periodical self-test execution, at the smallest period allowed by the real-time application, and ensures that all embedded system constraints are met. Furthermore, provided solution achieves high test quality while helping in the optimization of the costs of the final system. The proposed methodology is applied to different architectures of Java processors to demonstrate its efficiency. Finally, this work presents a tool that automates the design and implementation of on-line self-test in the studied processors by implementing the STEP methodology.

Sistemas embarcados baseados em processadores têm sido largamente aplicados em áreas críticas no que diz respeito à segurança de seres humanos e do meio ambiente. Em tais aplicações, que compreendem desde o controle de freio de carros a missões espaciais, pode ser necessária a execução confiável de todas as funcionalidades do sistema durante longos períodos e em ambientes desconhecidos, hostis ou instáveis. Mesmo em aplicações não críticas, nas quais a confiabilidade do sistema não é um requisito primordial, o usuário final deseja que seu produto apresente comportamento estável e livre de erros. Daí vem a importância de se considerar o auto-teste on-line no projeto dos sistemas embarcados atuais. Entretanto, a crescente complexidade de tais sistemas somada às fortes restrições a que eles estão sujeitos torna o projeto do auto-teste um problema cada vez mais desafiador. Em aplicações de tempo-real a dificuldade é ainda maior, uma vez que, além dos cuidados com as restrições do sistema alvo, deve-se levar em conta o atendimento dos requisitos temporais da aplicação. Entre as técnicas de auto-teste on-line atualmente pesquisadas, uma tem se destacado pela eficácia obtida a um baixo custo de projeto e sem grande impacto no atendimento dos requisitos e restrições do sistema: o auto-teste baseado em software (SBST – Software-Based Self-Test). Neste trabalho, é proposta uma metodologia para o projeto e aplicação de auto-teste on-line para processadores embarcados, considerando-se também aplicações de temporeal. Tal metodologia, denominada STEP (Self-Test for Embedded Processors), tem como base a técnica SBST e prevê o planejamento, a geração e a seleção de rotinas de teste para o processador alvo. O método proposto garante a execução periódica do autoteste, com o menor período permitido pela aplicação de tempo-real, e assegura o atendimento de todas as restrições do sistema embarcado. Além disso, a solução fornecida pelo método alcança uma boa qualidade de teste enquanto auxilia a redução de custos do sistema final. Como estudo de caso, a metodologia proposta é aplicada a diferentes arquiteturas de processadores Java e os resultados obtidos comprovam a eficiência da mesma. Por fim, é apresentada uma ferramenta que implementa a metodologia STEP, automatizando, assim, o projeto e a aplicação de auto-teste on-line para os processadores estudados. / Processor-based embedded systems have been widely used in safety-critical applications. In such applications, which include from cars break control to spatial missions, the whole system operation must be reliable during long periods even within unknown, hostile and unstable environments. In non-critical applications, system reliability is not a prime requirement, but the final user requires an error free product, with stable behavior. Hence, one can realize the importance of on-line self-testing in current embedded systems. Self-testing is becoming an important challenge due to the increasing complexity of the systems allied to their strong constraints. In real-time applications this problem becomes even more complex, since, besides meeting systems constraints, one must take into consideration the application timing requirements. Among all on-line self-testing techniques studied, Software-Based Self-Test (SBST) has been distinguished by its effectiveness, low-cost and small impact on system constraints and requirements. This work proposes a methodology for the design and implementation of on-line self-test in embedded processors, considering real-time applications. Such a methodology, called STEP (Self-Test for Embedded Processors), is based on SBST technique and encloses planning, generation and selection of test routines for the target processor. The proposed method guarantees periodical self-test execution, at the smallest period allowed by the real-time application, and ensures that all embedded system constraints are met. Furthermore, provided solution achieves high test quality while helping in the optimization of the costs of the final system. The proposed methodology is applied to different architectures of Java processors to demonstrate its efficiency. Finally, this work presents a tool that automates the design and implementation of on-line self-test in the studied processors by implementing the STEP methodology.

Sistemas embarcados baseados em processadores têm sido largamente aplicados em áreas críticas no que diz respeito à segurança de seres humanos e do meio ambiente. Em tais aplicações, que compreendem desde o controle de freio de carros a missões espaciais, pode ser necessária a execução confiável de todas as funcionalidades do sistema durante longos períodos e em ambientes desconhecidos, hostis ou instáveis. Mesmo em aplicações não críticas, nas quais a confiabilidade do sistema não é um requisito primordial, o usuário final deseja que seu produto apresente comportamento estável e livre de erros. Daí vem a importância de se considerar o auto-teste on-line no projeto dos sistemas embarcados atuais. Entretanto, a crescente complexidade de tais sistemas somada às fortes restrições a que eles estão sujeitos torna o projeto do auto-teste um problema cada vez mais desafiador. Em aplicações de tempo-real a dificuldade é ainda maior, uma vez que, além dos cuidados com as restrições do sistema alvo, deve-se levar em conta o atendimento dos requisitos temporais da aplicação. Entre as técnicas de auto-teste on-line atualmente pesquisadas, uma tem se destacado pela eficácia obtida a um baixo custo de projeto e sem grande impacto no atendimento dos requisitos e restrições do sistema: o auto-teste baseado em software (SBST – Software-Based Self-Test). Neste trabalho, é proposta uma metodologia para o projeto e aplicação de auto-teste on-line para processadores embarcados, considerando-se também aplicações de temporeal. Tal metodologia, denominada STEP (Self-Test for Embedded Processors), tem como base a técnica SBST e prevê o planejamento, a geração e a seleção de rotinas de teste para o processador alvo. O método proposto garante a execução periódica do autoteste, com o menor período permitido pela aplicação de tempo-real, e assegura o atendimento de todas as restrições do sistema embarcado. Além disso, a solução fornecida pelo método alcança uma boa qualidade de teste enquanto auxilia a redução de custos do sistema final. Como estudo de caso, a metodologia proposta é aplicada a diferentes arquiteturas de processadores Java e os resultados obtidos comprovam a eficiência da mesma. Por fim, é apresentada uma ferramenta que implementa a metodologia STEP, automatizando, assim, o projeto e a aplicação de auto-teste on-line para os processadores estudados. / Processor-based embedded systems have been widely used in safety-critical applications. In such applications, which include from cars break control to spatial missions, the whole system operation must be reliable during long periods even within unknown, hostile and unstable environments. In non-critical applications, system reliability is not a prime requirement, but the final user requires an error free product, with stable behavior. Hence, one can realize the importance of on-line self-testing in current embedded systems. Self-testing is becoming an important challenge due to the increasing complexity of the systems allied to their strong constraints. In real-time applications this problem becomes even more complex, since, besides meeting systems constraints, one must take into consideration the application timing requirements. Among all on-line self-testing techniques studied, Software-Based Self-Test (SBST) has been distinguished by its effectiveness, low-cost and small impact on system constraints and requirements. This work proposes a methodology for the design and implementation of on-line self-test in embedded processors, considering real-time applications. Such a methodology, called STEP (Self-Test for Embedded Processors), is based on SBST technique and encloses planning, generation and selection of test routines for the target processor. The proposed method guarantees periodical self-test execution, at the smallest period allowed by the real-time application, and ensures that all embedded system constraints are met. Furthermore, provided solution achieves high test quality while helping in the optimization of the costs of the final system. The proposed methodology is applied to different architectures of Java processors to demonstrate its efficiency. Finally, this work presents a tool that automates the design and implementation of on-line self-test in the studied processors by implementing the STEP methodology.

Les systèmes RFID – pour RadioFrequency Identification – sont capables d’identifier des objets ou des personnes sans contact ni vision direct. Ainsi, leur utilisation grandit de manière exponentielle dans différents secteurs : nucléaire, aviation, ferroviaire, médical, traçabilité, contrôle d’accès… Mais ce sont surtout des systèmes fortement hétérogènes, composés de matériel analogique ou digital, et de systèmes informatique : le tag, attaché à l’objet à identifier, contenant l’identifiant de ce dernier ; le lecteur, appareil capable de venir lire les informations contenus dans les tags ; et le système informatique gérant l’ensemble des données générées par le système. Ces systèmes sont de plus en plus utilisés dans des domaines critiques ou dans des environnements difficiles, alors qu’ils sont basés uniquement sur des équipements bas coût et peu performant – les tags – ne permettant alors pas de garantir des communications robustes. Tous ces points font que le test en ligne des systèmes RFID est une tâche complexe.Cette thèse s’intéresse donc à la sûreté de fonctionnement des systèmes RFID : comment être certains que le système fonctionne comme il faut au moment où on en à besoin ? En premier, les défaillances et leurs causes ont été étudiées à l’aide d’une méthode classique : AMDE – Analyse des modes de défaillances et de leurs effets. Cette étude a permis d’identifier les points faibles des systèmes RFID. Après cela et grâce à cette analyse, il nous a été possible de définir et d’implémenter un simulateur de systèmes RFID appelé SERFID, pour Simulation et Evaluation des systèmes RFID. Ce simulateur est capable de simuler différents systèmes RFID multi-équipements (HF ou UHF, normes actuellement implémentées : ISO15693 et EPC Classe 1 Génération 2), du tag au lecteur, en passant par le canal de communication permettant aux tags et aux lecteurs de communiquer. SERFID permet aussi de connecter les lecteurs simulés à des middlewares existants ou nouveau afin des les évaluer. Pour permettre l’évaluation de la sûreté de fonctionnement des systèmes RFID, SERFID permet l’injection de fautes dynamiquement au sein des tags, lecteurs ou du canal de communication permettant de simuler différentes défaillances pouvant apparaître : diminution de la qualité de la communication ou de l’alimentation du tag, erreurs au sein de la mémoire du tag, bruit… SERFID a été notamment utilisé pour simuler et observer le comportement de systèmes RFID HF et UHF face à du bruit et des perturbations dans le canal de communication entre le tag et le lecteur. Finalement, cette thèse propose une nouvelle méthode pour détecter les tags fautifs ou vieillissants dans les applications de logistiques. Cette méthode, non intrusive et en ligne, est basée sur l’observation des performances du système au cours de son fonctionnement : le logiciel de gestion analyse les résultats des différentes identifications. A partir du taux d’erreur de lecture par tag, et en le comparant aux taux de lecture par tag précédemment observés, cette méthode est capable de déterminer quel groupe de tags est fautif ou non. Cette méthode a été évaluée par expérimentation et par simulation grâce à SERFID. Cette évaluation a permis de mettre en évidence les points forts et les faiblesses de la méthode. / RFID systems – for RadioFrequency Identification – are able to identify object or person without any contact or direct vision. For this reason, their use grows exponentially in many different fields: nuclear, avionics, railways, medical, warehouse inventories, access control… However they are complex heterogeneous systems, consisting of analog and digital hardware components and software components: the tag, closed on the object to identified, which contains its identifier; the reader which able to read identifiers on tags; and finally the IT infrastructure to manage data. RFID technologies are often used into critical domains or within harsh environments. But as RFID systems are only based on low cost and low-performance equipments, they do not always ensure robust communications. All these points make the on-line testing of RFID systems a very complex task.This thesis focuses on dependability of RFID systems: how to be sure that this system works correctly when we need to use it? Firstly, failures and their causes have been studied using a common method called FMEA – Failure Modes and Effects Analysis – This study allows to identify weakness aspects of RFID systems. After that and thanks to this analysis, a new simulator was designed and implemented. This simulator, called SERFID for Simulation and Evaluation of RFID systems, is able to simulate various RFID systems with many devices (HF or UHF, actually implemented standards: ISO15693 or EPC Class 1 Generation 2), from tag to reader, together with the RF channel between them and the physic aspect which permit to tags and readers to communicate. SERFID also permits to connect an existing or new middleware to simulated reader to evaluate new software approach. To analyze dependability of RFID systems, SERFID allows us to inject fault in tag, channel or readers dynamically, to simulate different failures which can be appear: decrease of quality of communication or tag supply, memory errors in tag, noises… SERFID was in particular use to simulate HF and UHF RFID systems to observe their reaction according noises and disturbances in communication between tag and reader. Finally, a new method to detect faulty or aging tags or readers in traceability application was proposed. This non-intrusive on-line method is based on performance observation of the system during operation: the managing software analyzes results of an identification round. According read error rate per tag of an inventory, and comparing it with previous obtained read error rates per tag, this method is able to determine which group of tags is faulty or not. This method has been analyzed with to method: by experimentations and by simulation using SERFID. This analyze brings out weakness and strength of this method.

隨著電子化學習(E-Learning)環境技術的普及，線上學習與線上測驗已成為資訊教育的重要議題。但是因為填充題及問答題等測驗類型在線上測驗系統上實施有許多問題需克服，當線上測驗系統提供填充題及問答題等題型測驗時，將會產生嚴重的測驗評分等化(Equation)問題。目前線上測驗系統大多仍以是非題、單選題及複選題等題型為主，雖有少數線上測驗系統提供填充題及其他開放式填答的測驗類型，但仍未針對受測者填答之答案進行的語意自動評分。 / 另外，現有線上測驗系統未提供教師設定個人化的評分風格，對於多位教師共用測驗系統平台時所產生的評分規則認知衝突，系統也未提供支援與解決，為了解決上述問題，並使線上測驗能具備與傳統測驗相同的評量效力，本研究使用模糊理論、相似語意詞庫及人工智慧概念等，發展一個線上測驗及智慧評分子系統，此系統除了包括一般測驗系統所提供的是非、單選、複選等題型外，也包含採用智慧評分機制來評分的填充題，完成雛形系統的建置後，本研究再針對傳統紙筆測驗、一般型評分機制、及本研究的智慧型評分機制進行評分效力比較的實證研究。 / 此部分的實證研究結果顯示，在包含填充題型的測驗中，不同的評分機制在測驗成績的評分結果上會有顯著差異，而智慧型評分機制運作初期雖然可以減少與紙筆評分間的差異，並改善一般型評分機制的評分效力，但仍無法在統計上獲得具有相同評分效力的結果。但是智慧評分機制在擴充詞彙語意後，「已擴充語意後的智慧評分機制」與「紙筆評分」的評分結果並無顯著差異，其顯示出若在包括填充題型的線上測驗系統中加入具有擴充詞彙語意關係知識的功能，並提供多功能的智慧型模糊評分機制，允許教師輸入代表個人評分風格習慣的評分規則參數，則線上評分系統將有可能具有與紙筆評分相同的評分效力來處理具有填充題題型的測驗工作。 / 然而線上測驗並不只是在測驗後給予受測者一個分數而已，而應該讓學習者了解自己在知識向度及認知向度的學習結果，因此測驗系統的試題若能包含Bloom教育目標分類資訊，將促使測驗活動能給予學習者更大的幫助。為了降低教師製作試題的負擔，本研究也以本體論、詞彙網路、Bloom分類理論、中文語意庫、人工智慧為基礎，提出一個輔助教師產製題庫的系統架構，並使電腦所產製的試題能涵蓋新版Bloom認知領域教育目標分類中的知識向度及認知向度概念。本研究在電腦輔助教師產製題庫的成果上，不僅能減少教師人工出題的負擔，系統產製的試題也能評量事實、概念及程序等三種知識及記憶、了解、應用、分析及評鑑等五種認知向度能力。受限於線上測驗系統能自動評分的四種題型，本研究尚無法產製屬於創造認知層次的試題，但是卻已能產製出包含基本知識概念的試題，並能提供具有Bloom概念的測驗題庫來評量學習成效。此外，本研究亦針對電子化學習環境，提出適用於線上測驗系統的試題品質及評分等化能力評估概念模式，強調Bloom理論在線上測驗系統環境中的使用範圍與限制。此模式也透過測驗等化觀念，針對教育領域測驗理論在評估試題品質概念上提出新的觀點。 / Since the rapid E-learning development, the online learning and testing have been important topics of information education. Currently teachers still need to spend much time on creating and maintaining on-line testing item banks. Some researches have applied the new Bloom's taxonomy to design meaningful learning assessments. This research has applied ontology, Bloom's taxonomy, Chinese semantic database, artificial intelligence, semantic web, to design an on-line course learning system to assist teachers in creating test items. / Most of present on-line testing only has multiple choice items and true-false items. Though some provide fill-in-blank items, they can only recognize the answers either all right or all wrong through the simple computer binary pattern matching. In order to have the same evaluation effects as the traditional paper-and-pencil testing, this research will adopt the concepts of fuzzy theory, thesaurus, set, and artificial intelligence to develop the fuzzy scoring mechanism. The proposed on-line testing system will have true-false, multiple-choice, and fil-in-blank items. The latter will be graded through fuzzy judgment that is naturally endowed by the human teachers. / In addition, the past research indicated that e-learning students would learn more if provided appropriate feedback messages. In this research will add feedback messages to the proposed system according to different situations. The proposed on-line testing system will not only grade the test items, but also explain the answers and provide related materials to the testers. / The result of study are: (1) we could design the test items that would need a particular cognitive process to a particular type of knowledge, though we still could not have items to test “creative” level of cognitive process; (2) the test items could be used to assess the learning level meaningfully; (3) the computer would assist teachers to create a large number items, and save time of making item; (4) that different scoring mechanisms have a significant effect on test scores; (5) at the beginning, though our fuzzy on-line testing system is significantly better than the usual on-line testing system, it could not achieve the same effect as the paper-and-pencil testing; (6) after expanding semantic vocabularies from feedbacks, our fuzzy scoring mechanism is equivalent to paper-and-pencil.

Si on veut assurer de fawn efficace les tests de conception, de fabrication, de maintenance et le test accompli au cours de l'application pour les systemes electroniques, on est amend a integrer le test hors-ligne et le test en-ligne dans des circuits. Ensuite, pour que les systemes complexes tirent profit des deux types de tests, une telle unification doit etre &endue du niveau circuit aux niveaux carte et module. D'autre part, bien que rintegration des techniques de test hors-ligne et en-ligne fait qu'il est possible de concevoir des systemes pour toute application securitaire, le materiel ajoute pour assurer une haute siirete de fonctionnement fait que la fiabilite de ces systemes est reduite, car la probabilite d'occurrence de fautes augmente. Confront& a ces deux aspects antagoniques, cette these se fixe l'objectif de trouver un compromis entre la securite et la fiabilite de systemes electroniques complexes. Ainsi, dans un premier temps, on propose une solution aux problemes de test hors-ligne et de diagnostic qui se posent dans les &apes intermediaires de revolution vers les cartes 100% compatibles avec le standard IEEE 1149.1 pour le test "boundary scan". Une approche pour le BIST ("Built-In Self-Test") des circuits et connexions "boundary scan" illustre ensuite retape ultime du test hors-ligne de cartes. Puis, le schema UBIST ("Unified BIST") - integrant les techniques BIST et "self-checking" pour le test en-ligne de circuits, est combine au standard IEEE 1149.1, afin d'obtenir une strategie de conception en vue du test unifie de connexions et circuits montes sur des cartes et modules. Enfin, on propose un schema tolerant les fautes et base sur la duplication de ces modules securitaires qui assure la competitivite du systeme resultant du point de vue de la fiabilite, tout en gardant sa silrete inherente. / On one hand, if the goal is to ensure that the design validation, the manufacturing and the maintenance testing, along with the concurrent error detection are efficiently performed in electronic systems, one is led to integrate the off-line and the on-line testing into circuits. Then, for complex systems to make profit of these two types of tests, such unification must be extended from the circuit to the board and module levels. On the other hand, although the unification of off-line and on-line testing techniques makes possible the design of systems suiting any safety application, the hardware added for increasing the application safety also decreases the system reliability, since the probability of occurrence of faults increases. Faced to these two antagonist aspects, this thesis aims at finding a compromise between the safety and the reliability of complex electronic systems. Thus, firstly we propose a solution to the off-line test and diagnosis problems found in the intermediate steps in the evolution towards boards which are 100% compliant with the IEEE standard 1149.1 for boundary scan testing. An approach for the BIST (Built-In Self-Test) of boundary scan circuits and interconnects then illustrates the ultimate step in the board off-line testing. Next, the UBIST (Unified BIST) scheme - merging BIST and self-checking capabilities for circuit on-line testing, is combined with the IEEE standard 1149.1, in order to obtain a design strategy for unifying the tests of interconnects and circuits populating boards and modules. Finally, we propose a fault-tolerant scheme based on the duplication of these kind of modules which ensures the competitivity of the resulting system in terms of reliability at the same time as preserving the inherent module safety.