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Thesis (Ph.D.)--University of Delaware, 2009. / Principal faculty advisor: Keith W. Goossen, Dept. of Electrical & Computer Engineering. Includes bibliographical references.

Thesis (Ph. D.)--University of Texas at Austin, 2004. / Supervisor: Ray T. Chen. Vita. Includes bibliographical references.

The influx of new data-intensive applications, such as machine learning and artificial intelligence, in high performance computing (HPC) and data centers (DC), has driven the design of efficient interconnection networks to meet the requisite bandwidth of the growing traffic demand. While the exponentially-growing traffic demand is expected to continue into the future, the free scaling of CMOS-based electrical interconnection networks will eventually taper off due to Moore’s Law. These trends suggest that building all-electrical interconnects to meet the increased demand for low latency, high throughput networking will become increasingly impractical going forward. Integrating optical interconnects capable of supporting high bandwidth links and dynamic network topology reconfiguration offer a potential solution to scaling current networks. However, the insertion of photonic interconnection networks offers a massive design space in terms of network topology and control plane that is currently under-explored. The work in this dissertation is centered around the study and development of control plane challenges to aid in the eventual adoption of optically-enabled reconfigurable networks. We begin by exploring Flexspander, a novel reconfigurable network topology that combines the flexible random expander networks construction with topological-reconfigurability using optical circuit switching (OCS). By incorporating random expander graph construction, as opposed to other more symmetric reconfigurable topologies, Flexspander can be built with a broader range of electrical packet switch (EPS) radix, while retaining high throughput and low latency when coupled with multi-path routing. In addition, we propose a topology-routing co-optimization scheme to improve network robustness under traffic uncertainties. Our proposed scheme employs a two-step strategy: First, we optimize the topology and routing strategy by maximizing throughput and average packet hop count for the expected traffic patterns based on historical traffic patterns. Second, we employ a desensitization step on top of the topology and routing solution to lower performance degradation due to traffic variations. We demonstrate the effectiveness of our approach using production traces from Facebook's Altoona data center, and show that even with infrequent reconfigurations, our solution can attain performances within 15\% of an offline optimal oracle. Next, we study the problem of routing scheme design in reconfigurable networks, which is a more under-studied problem compared to routing design for static networks. We first perform theoretical analyses to first identify the key properties an effective routing protocol for reconfigurable networks should possess. Using findings from these theoretical analyses, we propose a lightweight but effective routing scheme that yields high performance for practical HPC and DC workloads when employed with reconfigurable networks. Finally, we explore two fundamental design problems in the optical reconfigurable network design. First, it investigates how different OCS placement in the physical network topology lead to different tradeoffs in terms of power consumption/cost, network performance, and scalability. Second, we investigate how network performance is affected by different reconfiguration periods to understand how frequency of topology reconfiguration affects application performance. Taken together, the work in this dissertation tackles several key challenges related to efficient control plane for reconfigurable network designs, with the goal of facilitating the eventual adoption of optically-enable reconfigurable networks in high performance systems.

No description available.

VLSI miniaturization has created the need for high-density, low-cost, monolithically-integrated optical interconnects. High output power photodetectors are needed to directly drive load circuitry, which improves the noise performance and dynamic range of optical communications links by eliminating a post amplifier stage. Elimination of the post amplifier also reduces circuit cost and complexity. A new Si-Ge PIN waveguide photodiode with 31GHz bandwidth and 93% quantum efficiency at 1550nm has been developed by Yin et al., which was fabricated using standard CMOS processes on a Silicon substrate. This thesis demonstrates a method for improving the RF power extraction from these photodiodes by increasing the impedance of the load. An RF output power improvement of 5.5dB is obtained by increasing the load resistance from 50 ohms to 177 ohms with 15MHz modulation. The maximum obtainable RF power of all devices tested using 50 ohm and 100 ohm loads at 15MHz is 15.73dBm and 17.83dBm, respectively. The maximum obtainable RF power using a 177 ohm load for all devices tested is 17.67dBm, which is slightly smaller than that obtained with a 100 ohm load. A measurement procedure for RF power extraction at microwave frequencies is also described. Quarter-wavelength 70.71 ohm thin film coplanar waveguides are designed to transform 50 ohms to a higher impedance of 100 ohms for measurements of improved RF power extraction at 3GHz and 7GHz.

The use of optical input/output (I/O) interconnects, in addition to electrical I/Os, is a promising approach for achieving high-bandwidth, chip-to-board communications required for future high-performance gigascale chip-based systems. While numerous efforts are underway to investigate the integration of optoelectronics and silicon microelectronics, virtually no work has been reported relating to testing of such chips. The objective of this research is to explore methods that enable wafer-level testing of gigascale chips having electrical and optical I/O interconnects. A major challenge in achieving this is to develop probe modules which would allow high-precision, temporary interconnection of a multitude of electrical and optical I/Os, in a chip-size area, to automated test equipment. A probe module would need to do this in a rapid, step-and-repeat manner across all the chips on the wafer. In this work, two candidate probe modules were devised, batch-fabricated on Si using microfabrication techniques, and successfully demonstrated. The first probe module consists of compliant electrical probes (10^3 probes/cm^2) fabricated alongside grating-in-waveguide optical probes. The second module consists of micro-opto-electro-mechanical-systems (MOEMS)-based microsocket probes (10^4 probes/cm^2) to interface a chip with polymer pillar-based electrical and optical I/Os. High-density through-wafer interconnects are an essential attribute in both probe substrates for transferring electrical and optical signals to the substrate back-side. Fabrication and characterization of metal-clad, metal-filled, and polymer-filled through-wafer interconnects as well as process integration with probe substrate fabrication are described and numerous possible redistribution schemes are explicated. Chips with optical and electrical I/Os are an emerging technology, and one that test engineers are likely to encounter in the near future. The contributions of this thesis are to help understand and address the issues relating to joint electrical and optical testing during manufacturing.

Today's information and communication industry is confronted with a serious bottleneck due to the prohibitive energy consumption and limited transmission bandwidth of electrical interconnects. Silicon photonics offers an alternative by transferring data optically and thereby eliminating the restriction of electrical interconnects over distance and bandwidth. Due to the inherent advantage of using the same material as that used for the electronic circuitry, silicon photonics also promises high volume and low cost production plus the possibility of integration with electronics. In this thesis, I introduce an all-silicon optical interconnect architecture that promises very high integration density along with very low energy consumption. The basic building block of this architecture is a vertically coupled photonic crystal cavity-waveguide system. This vertically coupled system acts as a highly wavelength selective filter. By suitably designing the waveguide and the cavity, at resonance wavelength of the cavity, large drop in transmission can be achieved. By locally modulating the material index of the cavity electrically, the resonance wavelength of the cavity can be tuned to achieve modulation in the transmission of the waveguide. The detection scheme also utilizes the same vertically coupled system. By creating crystal defects in silicon in the cavity region, wavelength selective photodetection can be achieved. This unique vertical coupling scheme also allows us to cascade multiple modulators and detectors coupled to a single waveguide, thus offering huge channel scalability and design and fabrication simplicity. During this project, I have implemented this vertical coupling scheme to demonstrate modulation with extremely low operating energy (0.6 fJ/bit). Furthermore, I have demonstrated cascadeability and multichannel operation by using a comb laser as the source that simultaneously drives five channels. For photodetection, I have realized one of the smallest wavelength selective detector with responsivity of 0.108 A/W at 10 V reverse bias with a dark current of 9.4 nA. By cascading such detectors I have also demonstrated a two-channel demultiplexer.

The increasing integration of digital information with our daily lives has led to the rise of big data, cloud computing, and the internet of things. The growth in these categories will lead to an exponential increase in the required capacity for data centers and high performance computation. Meanwhile, due to bottlenecks in data access caused by the limited energy and bandwidth scalability of electrical interconnects, computational speedup can no longer scale with demand. A better solution is necessary in order to increase computational performance and reduce the carbon footprint of our digital future. People have long thought of photonic interconnects, which can offer higher bandwidth, greater energy efficiency, and orders-of-magnitude distance scalability compared to electrical interconnects, as a solution to the data access bottleneck in chip, board, and datacenter scale networks. Over the past three decades we have seen impressive growth of photonic technology from theoretical predictions to high-performance commercially available devices. However, the dream of an all-optical interconnection network for use in CPU, Memory, and rack-to-rack datacenter interconnects is not yet realized. Many challenges and obstacles still have to be addressed. This work investigates these challenges and describe some of the ways to overcome them. First we will first examine the pattern sensitivity of microring modulators, which are likely to be found as the first element in an optical interconnect. My work will illustrate the advantage of using depletion mode modulators compared to injection mode modulators as the number of consecutive symbols in the data pattern increases. Next we will look at the problem of thermal initialization for microring demultiplexers near the output of the optical interconnect. My work demonstrates the fastest achieved initialization speed to-date for a microring based demultiplexer. I will also explore an thermal initialization and control method for microrings based on temperature measurement using a pn-junction. Finally, we will look at how to control and initialize microring and MZI based optical switch fabrics, which is the second element found in a optical interconnect. Work here will show the possibility of switching high-speed WDM datastreams through microring based switches, as well as methods to deal with the complexities inherent in control and initialization of high-radix switch topologies. Through these demonstrations I hope to show that the challenges facing optical interconnects, although very real, are surmountable using reasonable engineering efforts.

ORMOCERR®s are organic-inorganic hybrid polymers. Since their material properties can be tailored precisely during synthesis, they are suitable for a wide range of applications in dielectric and optical microelectronics. This thesis reports on process development of ORMOCERR®s for Sequentially Build-Up (SBU) test vehicles, suitable for both electrical and optical interconnect. Furthermore, this work includes materials characterization, such as refractive index studies (system B59:V32), optical loss measurements (systems B59:V32 and B59:B66), and surface characterization through contact angle measurement and surface energy estimation (systems B59:V32 and B59:B66). Process development for a high-frequency test vehicle was performed applying a newly developed dielectric material of the ORMOCER® class. Dielectric layers in a total thickness of 80 μm were build-up on a common FR4 substrate, applying photolithographic processes and moderate process temperatures of below 433 K. The loss tangent and the permittivity of the material were measured to be 0.024 (loss tangent) and 3.05 (permittivity) over the entire frequency range 10 GHz to 40 GHz. The compatibility of the material to standard processes of the PCB industry was proven. Furthermore, a possibility for cost reduction in high-frequency MCM applications was shown, through the possibility of using low-cost substrates. The concept of a “flexible manufacture approach” for large-area panel optical backplane interconnects was introduced. Here, a 101.6 mm x 101.6 mm photolithographic mask is to be stepped-out over a large-area panel substrate (up to 609.6 mm x 609.6 mm). The goal is to be able to create a large amount of continuous and unique waveguide patterns over the whole area with a small portfolio of masks, thus being able to minimize excess costs. In practice continuous waveguide patterns were created over an area of 204.8 mm x 204.8 mm on a large-are panel (609.6 mm x 609.6 mm), using a large-are mask aligner and a 101.6 mm x 101.6 mm waveguide mask. The optical loss of the waveguides was measured to be 0.6 dB/cm (B59:V32 material system, λ =850 nm). In connection to the large-area panel project a re-evaluation on the optical power budget needed for high bit rate optical interconnects was performed. This work was mainly based on literature surveys of optical waveguide materials, planar optical amplifiers, light coupling structures, and planar light-routing structures. It was shown that optical amplification is necessary at certain places on realistically routed optical backplanes to boost the optical signal. Therefore, the concept of a flip-chip mountable optical amplifier (FOWA) device, based on planar optical waveguide amplifiers and Semiconductor Optical Amplifiers, was developed. The device’s design allows an independent manufacturing to the rest of the board and a mounting at key-positions using standard pick and place technology. Additionally, it was observed that most of the amplifier research is focused on the wavelength of 1310 nm and 1550 nm, whereas optical backplane applications are targeting the 830 nm range. During SBU processing of waveguide structures was discovered a de-wetting phenomenon of B59 resin on a cured B59:B66 and B59:V32 surface, respectively. Good wetting behavior could be achieved by adding small amounts of B66 or V32, respectively, to the B59. Surface tension estimations on various compositions of the systems B59:B66 and B59:V32 could not directly be correlated to the de-wetting phenomenon. Furthermore, the optical loss properties of B59 were only affected to a minor degree by adding B66 or V32. The process route proposed is an efficient alternative to processes including surface activations steps, thus opening possibilities for large-area processing in PCB industry, where surface activation steps, such as plasma activation or silanization, are not available. The process development, materials characterization, and reviews presented provide a basis for further research on processes for high-performance electro/optical backplane interconnects with focus on Large-Area Panel processing.