Silicon photonics is the study and application of photonic systems, which use silicon as an optical medium. Data is transferred in the systems by optical rays. This technology is seen as the substitutions of electric computer chips in the future and the means to keep tack on the Moore’s law. Cavity optomechanics is a rising field of silicon photonics. It focuses on the interaction between light and mechanical objects. Although it is currently at its early stage of growth, this field has attracted rising attention. Here, we present highly sensitive optical detection of acceleration using an optomechanical accelerometer. The core part of this accelerometer is a slot-type photonic crystal cavity with strong optomechanical interactions. We first discuss theoretically the optomechanical coupling in the air-slot mode-gap photonic crystal cavity. The dispersive coupling gom is numerically calculated. Dynamical parametric oscillations for both cooling and amplification, in the resolved and unresolved sideband limit, are examined numerically, along with the displacement spectral density and cooling rates for the various operating parameters. Experimental results also demonstrated that the cavity has a large optomechanical coupling rate. The optically induced spring effect, damping and amplification of the mechanical modes are observed with measurements both in air and in vacuum. Then, we propose and demonstrate our optomechanical accelerometer. It can operate with a resolution of 730 ng/Hz¹/² (or equivalently 40.1 aN/Hz¹/²) and with a transduction bandwidth of ≈ 85 kHz. We also demonstrate an integrated photonics device, an on-chip spectroscopy, in the last part of this thesis. This new type of on-chip microspectrometer is based on the Vernier effect of two cascaded micro-ring cavities. It can measure optical spectrum with a bandwidth of 74nm and a resolution of 0.22 nm in a small footprint of 1.5 mm².

The extraordinary growth of parallelism in high-performance computing requires efficient data communication for scaling compute performance. High-performance computing systems have been using photonic links for communication of large bandwidth-distance product during the last decade. Photonic interconnection networks, however, should not be a wire-for-wire replacement based on conventional electrical counterparts. Features of photonics beyond high bandwidth, such as transparent bandwidth steering, can implement important functionalities needed by applications. In another aspect, application characteristics can be exploited to design better photonic interconnects. Therefore, this thesis explores codesign opportunities at the intersection between photonic interconnect architectures and high-performance computing applications. The key accomplishments of this thesis, ranging from system level to node level, are as follows. Chapter 2 presents a system-level architecture that leverages photonic switching to enable a reconfigurable interconnect. The architecture, called Flexfly, reconfigures the inter-group level of the widely-used Dragonfly topology using information about the application’s communication pattern. It can steal additional direct bandwidth for communication-intensive group pairs. Simulations with applications such as GTC, Nekbone and LULESH show up to 1.8x speedup over Dragonfly paired with UGAL routing, along with halved hop count and latency for cross-group messages. To demonstrate the effectiveness of our approach, we built a 32-node Flexfly prototype using a silicon photonic switch connecting four groups and demonstrated 820 ns interconnect reconfiguration time. This is the first demonstration of silicon photonic switching and bandwidth steering in a high-performance computing cluster. Chapter 3 extends photonic switching to the node level and presents a reconfigurable silicon photonic memory interconnect for many-core architectures. The interconnect targets at important memory access issues, such as network-on-chip hot-spots and non-uniform memory access. Integrated with the processor through 2.5D/3D stacking, a fast-tunable silicon photonic memory tunnel can transparently direct traffic from any off-chip memory to any on-chip interface – thus alleviating the hot-spot and non-uniform access effects. We demonstrated the operation of our proposed architecture using a tunable laser, a 4-port silicon photonic switch (four wavelength-routed memory channels) and a 4x4 mesh network-on-chip synthesized by FPGA. The emulated system achieves a 15-ns channel switching time. Simulations based on a 12-core 4-memory model show that for such switching speeds the interconnect system can realize a 2x speedup for the STREAM benchmark in the hot-spot scenario and a reduction of execution time for data-intensive applications such as 3D stencil and K-means clustering by 23% and 17%, respectively. Chapters 4 explores application-level characteristics that can be exploited to hide photonic path setup delays. In view of the frequent reuse of optical circuits by many applications, we proposed a circuit-cached scheme that amortizes the setup overhead by maximizing circuit reuses. In order to improve circuit “hit” rates, we developed a reuse-distance based replacement policy called “Farthest Next Use”. We further investigated the tradeoffs between the realized hit rate and energy consumption. Finally, we experimentally demonstrated the feasibility of the proposed concept using silicon photonic devices in an FPGA-controlled network testbed. Chapter 5 proceeds to develop an application-guided circuit-prefetch scheme. By learning temporal locality and communication patterns from upper-layer applications, the scheme not only caches a set of circuits for reuses, but also proactively prefetches circuits based on predictions. We applied this technique to communication patterns from a spectrum of science and engineering applications. The results show that setup delays via circuit misses are significantly reduced, showing how the proposed technique can improve circuit switching in photonic interconnects.

The market for higher data rate communication is driving the semiconductor industry to develop new techniques of writing at smaller scales, while continuing to scale bandwidth at low power consumption. The question arises of how to continue to sustain this trend. Silicon photonic (SiPh) devices offer a potential solution to the electronic interconnect bandwidth bottleneck. SiPh leverages the technology commensurate of decades of fabrication development with the unique functionality of next-generation optical interconnects. Finer fabrication techniques have allowed for manufacturing physical characteristics of waveguide structures that can support multiple modes in a single waveguide. By refining modal characteristics in photonic waveguide structures, through mode multiplexing with the asymmetric y-junction and microring resonator, higher aggregate data bandwidth is demonstrated via various combinations of spatial multiplexing, broadening applications supported by the integrated platform. The main contributions of this dissertation are summarized as follows. Experimental demonstrations of new forms of spatial multiplexing combined together exhibit feasibility of data transmission through mode-division multiplexing (MDM), mode-division and wavelength-division multiplexing (MDM-WDM), and mode-division and polarization-division multiplexing (MDM-PDM) through a C-band, Si photonic platform. Error-free operation through mode multiplexers and demultiplexers show how data can be viably scaled on multiple modes and with existing spatial domains simultaneously. This work opens up new avenues for scaling bandwidth capacity through leveraging orthogonal domains available on-chip, beyond what had previously been employed like WDM and time-division multiplexing (TDM). Furthermore, we explore expanding device channel support from two to three arms. Finding that a slight mismatch in the third arm can increase crosstalk contributions considerably, especially when increasing data rate, we explore a methodical way to design the asymmetric y-junction device by considering its angles and multiplexer/demultiplexer arm width. By taking into consideration device fabrication variations, we turn towards optimizing device performance post-fabrication. Through ModePROP simulations, optimizing device performance dynamically post-fabrication is analyzed, through either electro-optical or thermo-optical means. By biasing the arm introducing the slight spectral offset, we can quantifiably improve device performance. Scaling bandwidth is experimentally demonstrated through the device at 3 modes, 2 wavelengths, and 40 Gb/s data rate for 240 Gb/s aggregate bandwidth, with the potential to reduce power penalty per the device optimization process we described. A main motivation for this on-chip spatial multiplexing is the need to reduce costs. As the laser source serves as the greatest power consumer in an optical system, mode-division multiplexing and other forms of spatial multiplexing can be implemented to push its potentially prohibitive cost metrics down. While the device introduces loss, through imperfect mode isolation, as device fabrication improves, tolerance can increase as well. Meanwhile, the rate that laser power consumption increases as supported wavelengths scales is shown to be much faster than the loss introduced by scaling on-chip bandwidth multi-modally. Future generations of ultra-high capacity devices through spatial multiplexing is explored. Already various systems can be implemented multimodally, with the design features serving as useful for other components. Central to photonic network-on-chips, a multimodal switch fabric, composed of microring resonators, is demonstrated to have error-free operation of 1x2 switching of 10 Gb/s data. These contributions aim to scale bandwidth to ultra-high capacity, while ameliorating any imperfect design, through multiple routes conjoined with on-chip spatial multiplexing, and they constitute the bulk of this dissertation. For the latter part, we turn to the issue of integrating a photonic device for dynamic power reallocation in a system. Specifically, we utilize a 4x4 nonblocking switch fabric composed of Mach-Zehnder interferometers that switch both electro-optically and thermo-optically at ns and μs rates respectively. In order to demonstrate an intelligent platform capable of dynamically multicasting data and reallocating power as needed by the system, we must first initialize the switch fabric to control with an electronic interface. A dithering mechanism, whereby exact cross, bar, and sub-percentage states are enforced through the device, is described here. Such a method could be employed for actuating the device table of bias values to states automatically. We then employ a dynamic power reallocation algorithm through a data acquisition unit, showing real-time channel recovery for channels experiencing power loss by diverting power from paths that could tolerate it. The data that is being multicast through the system is experimentally shown to be error-free at 40 Gb/s data rate, when transmitting from one to three clients and going from automatic bar/cross states to equalized power distribution. For the last portion of this topic, the switch fabric was inserted into a high-performance computing system. In order to run benchmarks at 10 Gb/s data ontop of the switch fabric, a newer model of the control plane was implemented to toggle states according to the command issued by the server. Such a programmable mechanism will prove necessary in future implementations of optical subsystems embedded inside larger systems, like data centers. Beyond the specific control plane demonstrated, the idea of an intelligent photonic layer can be applied to alleviate many kinds of optical channel abnormalities or accommodate for switching based on different patterns in data transmission. Besides spatial-multiplexing, expanding on-chip bandwidth can be accomplished by extension of the wavelength detection regime to a longer regime. Experimental demonstration of photodetection at 1.9 μm is shown with Si+-doped Si photodetectors at 1 Gb/s data operation featuring responsivities of .03 AW−1 at 5 V bias. The same way of processing these Si ribbed waveguide photodetectors can garner even longer wavelength operation at 2.2 μm wavelength. Finally, the experimental demonstration of a coherent perfect absorption Si modulator is exhibited, showing a viable extinction ratio of 24.5 dB. Using this coherent perfect absorption mechanism to demodulate signals, there is the added benefit of differential reception. Currently, an automated process for data collection is employed at a faster time scale than instabilities present in fibers in the setup with future implementations eliminating the off-chip phase modulator for greater signal stability. The field of SiPh has developed to a stage where specific application domains can take off and compete according to industrial-level standards. The work in this dissertation contributes to experimental demonstration of a newly developing area of mode-division multiplexing for substantially increasing bandwidth on-chip. While implementing the discussed photonic devices in dynamic systems, various attributes of integrated photonics are leveraged with existing electronic technologies. Future generations of computing systems should then be designed by implementing both system and device level considerations.

The combination of silicon photonics and advanced heterogeneous integration is promising for next-generation disaggregated data centers that demand large scale, high throughput, and low power. In this dissertation, we discuss the design and theory of power-efficient optical transceivers with System-in-Package (SiP) 2.5D integration. Combining prior arts and proposed circuit techniques, a receiver chip and a transmitter chip including two 10 Gb/s data channels and one 2.5 GHz clocking channel are designed and implemented in 28 nm CMOS technology. An innovative transimpedance amplifier (TIA) and a single-ended to differential (S2D) converter are proposed and analyzed for a low-voltage high-sensitivity receiver; a four-to-one serializer, programmable output drivers, AC coupling units, and custom pads are implemented in a low-power transmitter; an improved quadrature locked loop (QLL) is employed to generate accurate quadrature clocks. In addition, we present an analysis for inverter-based shunt-feedback TIA to explicitly depict the trade-off among sensitivity, data rate, and power consumption. At last, the research on CDR-based​ clocking schemes for optical links is also discussed. We introduce prior arts and propose a power-efficient clocking scheme based on an injection-locked phase rotator. Next, we analyze injection-locked ring oscillators (ILROs) that have been widely used for quadrature clock generators (QCGs) in multi-lane optical or wireline transceivers due to their low power, low area, and technology scalability. The asymmetrical or partial injection locking from 2 phases to 4 phases results in imbalances in amplitude and phase. We propose a modified frequency-domain analysis to provide intuitive insight into the performance design trade-offs. The analysis is validated by comparing analytical predictions with simulations for an ILRO-based QCG in 28 nm CMOS technology. This dissertation also discusses the design of high-linearity wireless wideband receivers. An out-of-band (OB) IM3 cancellation technique is proposed and analyzed. By exploiting a baseband auxiliary path (AP) with a high-pass feature, the in-band (IB) desired signal and out-of-band interferers are split. OB third-order intermodulation products (IM3) are reconstructed in the AP and cancelled in the baseband (BB). A 0.5-2.5 GHz frequency-translational noise-cancelling (FTNC) receiver is implemented in 65nm CMOS to demonstrate the proposed approach. It consumes 36 mW without cancellation at 1 GHz LO frequency and 1.2 V supply, and it achieves 8.8 MHz baseband bandwidth, 40dB gain, 3.3dB NF, 5dBm OB IIP3, and −6.5dBm OB B1dB. After IM3 cancellation, the effective OB-IIP3 increases to 32.5 dBm with an extra 34 mW for narrow-band interferers (two tones). For wideband interferers, 18.8 dB cancellation is demonstrated over 10 MHz with two −15 dBm modulated interferers. The local oscillator (LO) leakage is −92 dBm and −88 dB at 1 GHz and 2 GHz LO respectively. In summary, this technique achieves both high OB linearity and good LO isolation.

Silicon photonics is leading the advent of very-large-scale photonic integrated circuits (PICs) in which lasers, modulators, photodetectors, and multiplexers are integrated on a single chip and synchronized to enable faster data transfer both between and within highly integrated chips. Silicon photonics now extends beyond communication applications, paving new paths for many emerging applications and holding great potential in creating a compact beam projector. Compact beam steering in the visible and near-infrared spectral range is required for emerging applications such as augmented reality (AR) and virtual reality (VR) displays, optical traps for quantum information processing, biosensing, light detection and ranging (LiDAR), and free-space optical communications (FSO). Here we discuss two novel integrated beam steering platforms in the visible and near-infrared wavelengths, optical phased array (OPA) and focal plane switch array (FPSA), that can shape and steer a light beam. Previous OPA demonstrations have been mainly limited to the near-infrared spectral range due to the fabrication and material challenges imposed by the smaller wavelengths. Here we present the first active blue light phased array at the wavelength of 488 nm, leveraging a high confinement silicon nitride (Si₃N₄) platform. We randomly and sparsely place the emitters to remove grating lobes, alleviate fabrication constraints at this short wavelength and achieve a wide-angle 1D beam steering over a 50° field of view (FoV) with a full width at half maximum (FWHM) beam size of 0.17°. This demonstration is a crucial first step in realizing a non-mechanical fully-integrated beam steering device for many emerging applications. Unlike 1D steering OPA, designing 2D OPA impose a different challenge. Numerous issues arise, including complicated waveguide routing and optical crosstalk between channels. Also, creating a highly directional beam without ghost images is required to deploy visible OPAs in emerging applications. However, current demonstrations of visible OPAs, including our first demonstration, suffer from the issue of low directionality due to the presence of grating lobes, high background noise and a low percentage of power in the main beam. We demonstrate an integrated OPA that generates a highly directional beam at blue wavelengths (488 nm) by leveraging a disordered hyperuniform distribution of emitters. This exotic distribution is found in birds’ cone photoreceptor arrangements, the most uniform sampling given intrinsic packing constraints. Such unique distribution allows us to mitigate fabrication and waveguide routing constraints and achieve a beam with low background noise, high percentage of power and no grating lobes. Large-scale integration of the platform enables fully reconfigurable high-efficiency light projection across the entire visible spectrum. The novel platform offers a viable platform for next-generation applications in visible-spectrum addressing, imaging, and scanning displays. Although OPA is an invaluable device for creating a highly directional beam on a chip-scale, OPA has an inherent power consumption issue. Its architecture requires simultaneous control of all the phase shifters in the system for operation. We propose a novel silicon photonics FPSA system for beam steering with orders of magnitude lower electrical power consumption than other state-of-the-art platforms. The demonstrated system operates in the near-infrared wavelength regime; however, this can be extended into different wavelengths. Our demonstration enables low-size, weight, and power (SWaP) LiDAR for precision and autonomous robotics and optical scanners for mobile devices.

The increasing integration of digital information with our daily lives has led to the rise of big data, cloud computing, and the internet of things. The growth in these categories will lead to an exponential increase in the required capacity for data centers and high performance computation. Meanwhile, due to bottlenecks in data access caused by the limited energy and bandwidth scalability of electrical interconnects, computational speedup can no longer scale with demand. A better solution is necessary in order to increase computational performance and reduce the carbon footprint of our digital future. People have long thought of photonic interconnects, which can offer higher bandwidth, greater energy efficiency, and orders-of-magnitude distance scalability compared to electrical interconnects, as a solution to the data access bottleneck in chip, board, and datacenter scale networks. Over the past three decades we have seen impressive growth of photonic technology from theoretical predictions to high-performance commercially available devices. However, the dream of an all-optical interconnection network for use in CPU, Memory, and rack-to-rack datacenter interconnects is not yet realized. Many challenges and obstacles still have to be addressed. This work investigates these challenges and describe some of the ways to overcome them. First we will first examine the pattern sensitivity of microring modulators, which are likely to be found as the first element in an optical interconnect. My work will illustrate the advantage of using depletion mode modulators compared to injection mode modulators as the number of consecutive symbols in the data pattern increases. Next we will look at the problem of thermal initialization for microring demultiplexers near the output of the optical interconnect. My work demonstrates the fastest achieved initialization speed to-date for a microring based demultiplexer. I will also explore an thermal initialization and control method for microrings based on temperature measurement using a pn-junction. Finally, we will look at how to control and initialize microring and MZI based optical switch fabrics, which is the second element found in a optical interconnect. Work here will show the possibility of switching high-speed WDM datastreams through microring based switches, as well as methods to deal with the complexities inherent in control and initialization of high-radix switch topologies. Through these demonstrations I hope to show that the challenges facing optical interconnects, although very real, are surmountable using reasonable engineering efforts.

Advances in data-driven applications, particularly artificial intelligence and deep learning, are driving the explosive growth of computation and communication in today’s data centers and high-performance computing (HPC) systems. Increasingly, system performance is not constrained by the compute speed at individual nodes, but by the data movement between them. This calls for innovative architectures, smart connectivity, and extreme bandwidth densities in interconnect designs. Silicon photonics technology leverages mature complementary metal-oxide-semiconductor (CMOS) manufacturing infrastructure and is promising for low cost, high-bandwidth, and reconfigurable interconnects. Flexible and high-performance photonic switched architectures are capable of improving the system performance. The work in this dissertation explores various photonic interconnected systems and the associated optical switching functionalities, hardware platforms, and novel architectures. It demonstrates the capabilities of silicon photonics to enable efficient deep learning training. We first present field programmable gate array (FPGA) based open-loop and closed-loop control for optical spectral-and-spatial switching of silicon photonic cascaded micro-ring resonator (MRR) switches. Our control achieves wavelength locking at the user-defined resonance of the MRR for optical unicast, multicast, and multiwavelength-select functionalities. Digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) are necessary for the control of the switch. We experimentally demonstrate the optical switching functionalities using an FPGA-based switch controller through both traditional multi-bit DAC/ADC and novel single-wired DAC/ADC circuits. For system-level integration, interfaces to the switch controller in a network control plane are developed. The successful control and the switching functionalitiesachieved are essential for system-level architectural innovations as presented in the following sections. Next, this thesis presents two novel photonic switched architectures using the MRR-based switches. First, a photonic switched memory system architecture was designed to address memory challenges in deep learning. The reconfigurable photonic interconnects provide scalable solutions and enable efficient use of disaggregated memory resources for deep learning training. An experimental testbed was built with a processing system and two remote memory nodes using silicon photonic switch fabrics and system performance improvements were demonstrated. The collective results and existing high-bandwidth optical I/Os show the potential of integrating the photonic switched memory to state-of-the-art processing systems. Second, the scaling trends of deep learning models and distributed training workloads are challenging network capacities in today’s data centers and HPCs. A system architecture that leverages SiP switch-enabled server regrouping is proposed to tackle the challenges and accelerate distributed deep learning training. An experimental testbed with a SiP switch-enabled reconfigurable fat tree topology was built to evaluate the network performance of distributed ring all-reduce and parameter server workloads. We also present system-scale simulations. Server regrouping and bandwidth steering were performed on a large-scale tapered fat tree with 1024 compute nodes to show the benefits of using photonic switched architectures in systems at scale. Finally, this dissertation explores high-bandwidth photonic interconnect designs for disaggregated systems. We first introduce and discuss two disaggregated architectures leveraging extreme high bandwidth interconnects with optically interconnected computing resources. We present the concept of rack-scale graphics processing unit (GPU) disaggregation with optical circuit switches and electrical aggregator switches. The architecture can leverage the flexibility of high bandwidth optical switches to increase hardware utilization and reduce application runtimes. A testbed was built to demonstrate resource disaggregation and defragmentation. In addition, we also present an extreme high-bandwidth optical interconnect accelerated low-latency communication architecture for deep learning training. The disaggregated architecture utilizes comb laser sources and MRR-based cross-bar switching fabrics to enable an all-to-all high bandwidth communication with a constant latency cost for distributed deep learning training. We discuss emerging technologies in the silicon photonics platform, including light source, transceivers, and switch architectures, to accommodate extreme high bandwidth requirements in HPC and data center environments. A prototype hardware innovation - Optical Network Interface Cards (comprised of FPGA, photonic integrated circuits (PIC), electronic integrated circuits (EIC), interposer, and high-speed printed circuit board (PCB)) is presented to show the path toward fast lanes for expedited execution at 10 terabits. Taken together, the work in this dissertation demonstrates the capabilities of high-bandwidth silicon photonic interconnects and innovative architectural designs to accelerate deep learning training in optically connected data center and HPC systems.