In recent years, there has been growing interests on II-VI semiconductor nanostructures, which are suitable for applications in electronics and optoelectronic devices such as solar cells, UV lasers, sensors, light emitting diodes and field emission displays. II-VI semiconductor nanostructures with different morphologies such as wires, belts, rods, tubes, needles, springs, tetrapods, plates, hierarchical structures and so on, have been widely grown by vapor transport methods. However the process conditions used for the growth of nanostructures still remains incompatible for device fabrication. The realization of practical nanoscale devices using nanostructured film depends mainly on the availability of low cost and lower processing temperatures to manufacture high purity nanostructures on a variety of substrates including glass and polymer. In this thesis work, studies have been made on the growth and characterization of II-VI semiconductor nanostructures prepared at room temperature, under high vacuum, without employing catalysts or templates. (i) ZnO nanostructured films with different morphology such as flowers, needles and shrubs were deposited at room temperature on glass and polymer substrates by plasma assisted reactive process. (ii) Zn/ZnO core/shell nanowires were grown on Si substrates under optimized oxygen partial pressure. Annealing of this core shell nanowire in high vacuum resulted in the formation of ZnO nanocanals. (iii) ZnS and ZnSe nano and microstructures were grown on Si substrates under high vacuum by thermal evaporation. The morphology, structural, optical properties and composition of these nano and microstructures were investigated by XRD, SEM, TEM, Raman, PL and XPS. The growth mechanism behind the formation of the different nanostructures has been explained on the basis of vapour-solid (VS) mechanism.

Current electrical systems are faced with the limitation in performance by the electrical interconnect technology determining overall processing speed. In addition, the electrical interconnects containing many long distance interconnects require high power to drive. One of the best ways to overcome these bottlenecks is through the use of optical interconnect to limit interconnect latency and power. This research explores new computer-aided design algorithms for developing optoelectronic systems. These algorithms focus on place and route problems using optical interconnections covering system-on-a-chip design as well as system-on-a-package design. In order to design optoelectronic systems, optical interconnection models are developed at first. The CAD algorithms include optical interconnection models and solve place and route problems for optoelectronic systems. The MCNC and GSRC benchmark circuits are used to evaluate these algorithms.