In an ideal world, unwanted or undesirable effects in a system could and would be completely ignored. In fact, this was the case in mid-80s' PC design when an 80286 microprocessor running at a "blazing" 12 MHz was considered leading-edge technology. As technology continued to push the envelope and ever-faster designs were realized, more demanding software packages were developed and utilized efficiently. These increasingly sophisticated software packages in turn allowed designers of all disciplines to test systems of escalating complexity. These more complex models placed a heavier burden on the hardware, prompting a push for better and faster hardware designs. The cycle repeats to this day. As such, we are now in an environment where a 1 GHz microprocessor is considered somewhat dated. More importantly, whereas a small 1 nH (1 billionth of a Henry) inductance in a power delivery path was considered inconsequential a decade ago, it is now a barrier to implementing a design. Similarly, the equivalent series inductance (ESL) of a capacitor plays an increasing (and detrimental) role in the behavior and design of today's VRM (Voltage Regulator Module) design. In fact, it is the ESL of the capacitor that hinders proper voltage regulation at high frequencies by increasing the output impedance beyond a desired level. This dilemma has been recognized and several topologies have been proposed to overcome this problem. One category is improved passive devices, with the latest involving array capacitors to achieve near-zero ESL. As passive devices are almost always preferable to active solutions due to their lower losses, these technologies hold great promise, though they are inherently limited in small-footprint applications. A second category is the addition of active devices, which involves the use of some filtering technique to inject or absorb current during a fast transient by the use of semiconductor switches connected to a power source. These switching-state topologies have been shown to be prone to unstable oscillations, often caused by over-reactions or over-corrections of one transient prompting the opposite switch to engage its power source. The research goal is to develop a methodology to use active filters to more-seamlessly extend the control bandwidth of today's VRM technology. A hybrid active power filter is developed which uses bipolar junction transistors (BJT) in the forward-active region to connect a power supply source to the microprocessor. In this way, the switches are used in a way analogous to a dimmer switch (vs. simply 'on' or 'off'). By proper design of the compensator in the feedback loop, the active power filter can be used to suppress transients in any desired frequency range, limited only by the amplifier's current rating and bandwidth. The compensator design's derivation shows the relationship to the output impedance of the active filter. In essence, we are 'designing' a capacitor with a very low ESL, having more desirable output impedance vs. frequency relationship than either a capacitor, or a more complicated VRM with an extended bandwidth. Using this design, however, at very high frequencies (i.e., approaching 1 GHz, or one trillion cycles per second) requires state-of-the-art packaging designs to limit unwanted impedances, and also an ultra-wide GHz bandwidth, high-current operational amplifier. Both of these barriers are outside the scope of this research. As is often the case in research efforts, we have not '˜solved' the problem, but have shifted it to a frequency range where the effect isn't problematic. Experimental results show the use of a hybrid power filter with a VRM with Adaptive Voltage Positioning (AVP) can significantly suppress voltage undershoot during fast transient load current changes. In addition, the design is modified to reduce and possibly eliminate bulk output capacitors. This provides a promising alternative to a Voltage Regulator Module with a very high control bandwidth. Lastly, simulations give an estimate of the required IC design to use an APF to augment packaging capacitors. / Master of Science

No description available.

With lower output voltage (lower than 1V) and higher output current (more than 160A) required in the near future, the voltage regulators for the microprocessors, a kind of special power supplies are facing more and more critical challenges to achieve high efficiency and high power density. 90% plus efficiency for CPU VRs is expected from industry not only for the thermal management, but also for saving on electricity costs, especially for the large data-center systems. At the same time, high power density VRs are also desired due to the increasing power consumption of microprocessors as well as the precious space on CPU motherboard. Current multi-phase Buck VR has its limitation to achieve 90% plus efficiency. With the state of art devices, the single-stage 12V/1.2V 600kHz Buck VR achieves 85% to 86% efficiency at full load condition. In addition, for the future lower output voltage application, the Buck efficiency will drop another 3~4% due to the extreme small duty cycle. From the power density point of view, due to the switching frequency limitation (normally, from 300 kHz to 600 kHz for typical CPU VRs) for acceptable efficiency performance, the multi-phase Buck VR is unable to ensure a small size since it needs bulky output capacitors to meet the challenging transient requirement as well as the output impedance requirement with relatively low bandwidth design. To attain high efficiency and high power density at the same time, in-series two-stage power architecture was proposed. By cutting the single stage into two and utilizing the low voltage devices, the in-series two stages can achieve around 87% efficiency which is similar as single stage with second-stage operating at 1 MHz for less cost. Compared with the in-series one, the other two-stage power architecture is called "Sigma" architecture which is composed by an unregulated converter (DCX) and a regulated buck converter, with a special connection where the inputs are in series while outputs are paralleled. Through this topology, unlike the in-series two-stage where both two stages deliver the full load power, the power will be distributed between unregulated DCX and regulated Buck. If the unregulated DCX can achieve high efficiency, let most power be handled by it and just small power from buck, the Sigma architecture can achieve high efficiency performance based on this concept. The design consideration and process had been investigated by CPES previous graduates. By the designed 1.2V/120A Sigma VR circuit, approaching 90% efficiency was achieved which is around 3~4% efficiency higher than state of the art multi-phase Buck VR. However, it is not the optimal design for best efficiency performance, the improvement methods for higher efficiency is deeply considered and the efficiency potential benefit of this special structure will be clarified in this thesis. Besides the efficiency interest, transient performance of Sigma VR is also a challenging issue needed to be addressed. The state of the art Buck VR needs a bunch of output bulk capacitors to meet the stringent output impedance requirement from Intel and those output bulk capacitors occupy too much space in the motherboard. For Sigma architecture, through the help of the low impedance DCX which can achieve faster current dynamic response, some low voltage bulk capacitors could be replaced by smaller input high voltage capacitors. It is still not clear for us to identify how input capacitor impacts the DCX dynamic current response and how to best choose this impact factor. This thesis will investigate the faster DCX dynamic current performance of Sigma VR, and explain the dynamic impacts from input capacitors, from control design and from DCX impedance Lout. The high voltage capacitors could provide energy through low impedance DCX to deal with the transient load with smaller capacitance, resulting less total cost and footprint with conventional Buck solution. Low impedance DCX is also a desire for achieving fast current response for providing a "non-obstacle" path when energy transferring from input capacitors. The control also has the impact to the DCX current response when the bandwidth is higher than certain frequency. The transient benefit will also be discussed from impedance perspective. In order to improve the efficiency and power density of Sigma VR, several methods are proposed. As a critical component of DCX, the transformer design determines the performance of Sigma VR both to efficiency and power density. By optimizing the transformer design to achieve lower winding loss and smaller leakage inductance, the higher efficiency and faster transient DCX can be obtained. Changing the output capacitors to ceramic ones is helpful when control bandwidth is greater than 100 kHz for both lower cost and smaller footprint. Continually pushing bandwidth can reduce the required output ceramic capacitor number further. In addition, from the study of the loss breakdown, by adjusting the energy ratio of DCX and Buck can achieve higher efficiency based on current device level. What is more, with the same simple concept of adjusting power ratio of DCX and Buck, with the development of devices in the future as well as higher efficiency DCX, Sigma architecture will be more attractive for future's lower output voltage VR application. And it will also be more efficient considering higher than 12V input bus voltage by letting high efficiency DCX handle more power. Utilizing this characteristic, changing the power system delivery architecture from AC input to the microprocessors, the end to end efficiency could be improved. / Master of Science

Low voltage, low power amplifiers are proposed. One of the operational amplifiers is an Operational Transconductance Amplifier (OTA) with wide input and output swing and constant gm. The second and third amplifiers are high-performance Current Operational amplifiers (COAs). All amplifiers have power supply as low as one threshold voltage plus two overdrive voltage. In this thesis, the supply voltage is 1V. Simulation results show that the OTA has the maximum linear range over 0.7V. The transconductance can be 147£gA/V, the power consumption is 0.133mW. There are two designs of the COA. Simulation results show COA(1) with a current gain of 143. The input impedance is 110£[, the output impedance is 240K£[ and the power consumption is 0.15mW. In the simulation results of the COA(2), the current gain is 110. The DC power dissipation is 0.07mW. The input and output impedance are 95£[ and 500K£[, respectively. All the proposed amplifiers are implemented on a TSMC 0.35£gm 2p4m CMOS process technology and analyzed using HSPICE.

It is well known that real op-amps do not share most of the desirable characteristics of an ideal one, particularly those of gain and output impedance. When presented with a capacitive load, such as a MOSFET or ADC, feedback in an op-amp circuit can quickly become unstable. This thesis studies and characterizes an op-amp’s output impedance and how its interaction with this type of load creates a parasitic pole which leads to instability. Applying ideas from feedback control theory, a model for studying the problem is developed from which a generalized method for compensating the undesirable circumstance is formulated. Even in a zero-input state, many real op-amps driving capacitive loads can experience unforced oscillations. A case study is performed with three commonly used devices. First, the output impedance is determined by its dependence on the unity-gain bandwidth, load capacitance, and oscillation frequency. It is fitted into a second-order feedback control model that allows for an analytical study of the problem. It is then shown that a carefully designed passive network can be introduced between the load and op-amp to obtain a properly damped system free of oscillation and well-behaved. Using a shunt resistor is a known and commonly used method for lowering an op-amp’s output impedance to gain stability. This work considers the converse addition of a series capacitor to instead lower the load capacitance seen by the op-amp, a seemingly complementary method that achieves the same goal. A generalized, composite compensation method is developed that uses both the shunt resistor and series capacitor– a strategy not yet found in literature. Relevant formulas for damping ratio and natural frequency are derived that allow the design of a passive compensation network. Furthermore, tradeoffs between compensation, voltage swing, current consumption, and power usage are considered. An emphasis is placed on comparing simulated versus real circuits to highlight the fact that any problem is much worse in real-life than in a simulation. SPICE models and programs aim to de-idealize certain device characteristics, but often cannot account for environmental conditions and manufacturing variance. Thus, an importance is placed on experimental verification guided by simulations.

Bandgap reference circuits are used in a host of analog, digital, and mixed-signal systems to establish an accurate voltage standard for the entire IC. The accuracy of the bandgap reference voltage under steady-state (dc) and transient (ac) conditions is critical to obtain high system performance. In this work, the impact of process, power-supply, load, and temperature variations and package stresses on the dc and ac accuracy of bandgap reference circuits has been analyzed. Based on this analysis, the a bandgap reference that 1. has high dc accuracy despite process and temperature variations and package stresses, without resorting to expensive trimming or noisy switching schemes, 2. has high dc and ac accuracy despite power-supply variations, without using large off-chip capacitors that increase bill-of-material costs, 3. has high dc and ac accuracy despite load variations, without resorting to error-inducing buffers, 4. is capable of producing a sub-bandgap reference voltage with a low power-supply, to enable it to operate in modern, battery-operated portable applications, 5. utilizes a standard CMOS process, to lower manufacturing costs, and 6. is integrated, to consume less board space has been proposed. The functionality of critical components of the system has been verified through prototypes after which the performance of the complete system has been evaluated by integrating all the individual components on an IC. The proposed CMOS bandgap reference can withstand 5mA of load variations while generating a reference voltage of 890mV that is accurate with respect to temperature to the first order. It exhibits a trimless, dc 3-sigma accuracy performance of 0.84% over a temperature range of -40°C to 125°C and has a worst case ac power-supply ripple rejection (PSRR) performance of 30dB up to 50MHz using 60pF of on-chip capacitance. All the proposed techniques lead to the development of a CMOS bandgap reference that meets the low-cost, high-accuracy demands of state-of-the-art System-on-Chip environments.

This diploma work deals with active circuit elements and proposals of methods for measuring of some parameters of these elements. In the opening part the work deals with general classification of elements used in electronic circuits, ideal and real current sources and power supplies. Further there are stated basic parameters and characteristics presented by producers in a catalogue sheet for active elements MAX435, OPA660, AD844 and MAA741 element which already belongs to the history of IC. Main attention is paid to active circuit elements with current sources driven by CCCS (Current Controlled Current Source) and AD844 (high speed monolithic operational amplifier). In the work there is described a method for determining of selected parameters of active elements with CCCS. Examined parameters were frequency characteristics of current transfer, input impedance and output impedance. The proposed method was verified by a computer simulation on above mentioned active elements by means of PSpice software. Findings along with the description are summarized at the end of the work. In the closing part of the work there is undertaken a real measure of AD844 element based on the proposed method and the findings are compared with particular simulations. However, at first a flat connection board was made by means of EAGLE software and then the measure was performed on it.