Digital imaging systems for medical applications use amorphous silicon thin-film transistor (TFT) technology due to its ability to be manufactured over large areas, making it useful for X-ray imaging, which requires imagers to be the size of the subject, unlike optical imaging. TFT technology is used to make imaging arrays coated with an X-ray detector called amorphous selenium (a-Se), which can be grown easily over large areas by being evaporated on a substrate. However, TFT technology is far inferior to crystalline silicon CMOS technology in terms of the speed, stability, noise susceptibility, and feature size. Where CMOS technology falls short is its inability to be manufactured in large wafers at a competitive cost, allowing TFT technology to continue to be dominant in the medical imaging field, unlike the optical imaging industry. This work investigates the feasibility of integrating an imaging array fabricated in CMOS technology with an a-Se detector. The design of a CMOS passive pixel sensor (PPS) array is presented, in addition to how it is integrated with the amorphous selenium detector. Results show that the integrated Selenium-CMOS PPS array has good responsivity to optical light and X-rays, leaving the door open for further research on implementing CMOS imaging architectures going forward. Demonstrating that the PPS chips using CMOS technology can use a-Se as a detector is thus the first step in a promising path of research which should yield substantial and exciting results for the field. Though area may still prove challenging, larger CMOS wafers can be manufactured and tiled to allow for a large enough size for certain diagnostic imaging applications and potentially even large area applications like digital mammography.

Medical X-ray imaging is an important tool in diagnostic radiology. The ionising-radiation dose to the patient is justified by the clinical benefit of the examination. Nonetheless, detectors that operate at even lower doses and provide more information to the radiologist are desired. A hybrid pixel detector has the potential to provide a leap in detector technology as it incorporates a more advanced signal-processing capability than currently used detectors. The DIXI digital detector is a hybrid pixel detector developed for X-ray imaging. It consists of a readout chip and a semiconductor sensor. The division in two parts makes it possible to optimise each part individually. The detector is divided into square pixels with a size of 270 x 270 μm2. DIXI has the ability to count single photons and every readout pixel has two embedded counters to allow the acquisition of two images close in time. A discriminator enables the selection of photons with energies above a preset threshold level. The readout chip Angie has been developed and its performance has been evaluated in terms of noise, threshold variation and capability to perform energy weighted counting. Silicon sensors have been fabricated, and a control system for DIXI has been designed and built. An electroless process for deposition of Ni/Au bumps on the chip and sensor has been optimised as a preparation for the assembly of a complete detector, which is being assembled by flip-chip bonding using anisotropic conductive film. A simulation library for the DIXI detector has been set up and results on the image quality are reported for different exposures and working conditions. A theoretical model for hybrid pixel detectors based on the cascaded linear system theory has been developed. The model can be used to investigate and optimise the detector for different detector configurations and operating conditions.

An integrated circuit for evaluation of APS technology has been implemented in a 0.35 um process. The APS features snapshot operation and the readout circuitry can carry out: CDS, DS, and analog summing all in one circuit that is fully programmable. The output from the chip is a differential analog signal, intended to be connected to a high-speed ADC on an evaluation board. The sensor is fully compatible with current IVP camera systems, hence, the evaluation board should be easy to design. Several small code snippets that illustrate different modes of readout have been outlined, to aid the evaluation of the chip. It should be fairly straightforward to convert these code snippetsinto actual camera code. Furthermore, some code to illustrate a possible application and a faster mode of CDS have been indicated. Six types of APs have been implemented. They differ regarding diode type and implementation of the sampling capacitor. Design instructions and models for hand calculation have been described. The models have in most cases been validated by simulations and it has been shown that a readout speed of 8 MHz is possible to obtain, even for a larger sensor than this test chip. The desired resolution of 8 bits cannot be obtained for high levels of illumination. However, for low levels of illumination a resolution as high as 10 bits is possible. The chip layout has been validated to a large extent and should result in a fully functional chip, if manufactured. However, in the eventuality that IVP decides to manufacture this chip it is recommended to use the newer CAD tools, not available to the author at the time of implementation, to check the chip design for DRC and LVS errors.

Digital imaging systems for medical applications use amorphous silicon thin-film transistor (TFT) technology due to its ability to be manufactured over large areas, making it useful for X-ray imaging, which requires imagers to be the size of the subject, unlike optical imaging. TFT technology is used to make imaging arrays coated with an X-ray detector called amorphous selenium (a-Se), which can be grown easily over large areas by being evaporated on a substrate. However, TFT technology is far inferior to crystalline silicon CMOS technology in terms of the speed, stability, noise susceptibility, and feature size. Where CMOS technology falls short is its inability to be manufactured in large wafers at a competitive cost, allowing TFT technology to continue to be dominant in the medical imaging field, unlike the optical imaging industry. This work investigates the feasibility of integrating an imaging array fabricated in CMOS technology with an a-Se detector. The design of a CMOS passive pixel sensor (PPS) array is presented, in addition to how it is integrated with the amorphous selenium detector. Results show that the integrated Selenium-CMOS PPS array has good responsivity to optical light and X-rays, leaving the door open for further research on implementing CMOS imaging architectures going forward. Demonstrating that the PPS chips using CMOS technology can use a-Se as a detector is thus the first step in a promising path of research which should yield substantial and exciting results for the field. Though area may still prove challenging, larger CMOS wafers can be manufactured and tiled to allow for a large enough size for certain diagnostic imaging applications and potentially even large area applications like digital mammography.

The goal of this work is to extend the state-of-the-art in digital medical X-ray imaging as it pertains to real-time, low-noise imaging and multi-mode imager functionality. One focus of this research in digital flat-panel imagers is to increase the detective quantum efficiency, particularly at low X-ray exposures, in order to enable low-noise imaging applications such as fluoroscopy or tomographic mammography. Another focus of this research is in the creation of a multi-mode imager, such as a combined radiographic and fluoroscopic (R&F) imager, which will reduce hospital costs, both in terms of equipment acquisition and storage space. To that end, we propose a novel three-transistor multi-mode digital flat-panel imager with a dynamic range capable for use in R&F applications, with a particular focus on noise optimization for low-noise real-time digital flat-panel X-ray fluoroscopy. This work involves the derivation and optimization of the total input referred noise of an active pixel sensor (APS) in terms of the on-pixel thin-film transistor device dimensions. It is determined that in order to minimize noise, all non-transistor capacitances at the pixel sense node needed to be minimized. This leads to a design where the on-pixel storage capacitance is eliminated; and instead the gate capacitance of the sense-node transistor is used to store the incoming X-ray converted charge. This work allows researchers to gain insight into the fundamental noise operation of active pixels used in medical imaging, and to appropriately choose device dimensions. Due to the inherent large feature sizes of thin-film transistors, active pixel flat-panel X-ray medical imagers offer lower resolution than their film-screen counterparts. By demonstrating the desirability of smaller device dimensions for reduced noise and the elimination of a storage capacitor, this research frees some of the area constraints that exist in active pixel flat-panel imagers, allowing for smaller pixels, and thus higher resolution medical imagers. The noise analysis and optimization as a function of pixel TFT device dimensions in this work is applicable to any amorphous silicon (a-Si) based charge-sensitive pixel, and is easily extended to other device technologies such as polysilicon (poly-Si). iv In addition, experimental results of a 64x64 pixel four-transistor APS imaging array fabricated in a-Si technology and mated with an a-Se photoconductor for use in medical X-ray imaging is presented. MTF results and transient response in the presence of X-rays (image lag) for the APS array are poor, which is ascribed to high charge trapping at the silicon nitride/a-Se interface. Improvements to the silicon nitride passivation layer and pixel layout are suggested to reduce this charge trapping. The prototype imager is compared directly with a state-of-the-art a-Si PPS imaging array and demonstrates good SNR performance for X-ray exposures down to 1.5μR. Pixel design and fabrication process improvements are suggested for low-exposure APS testing and improved low-noise performance.

Polymer electrochromism on PEDOT coated fibres was successfully achieved. The electrochromic property of the PEDOT polymer is an excellent property. This feature gives way to many more research works at present and in the future also. The electrochromic property of the PEDOT polymer is utilized in this thesis work to design an electrochromic display pixel. The polymer coating over the fibres were obtained by using In-situ polymerization technique. The coated-fibres were used to design a display-pixel. Electrochemistry is performed successfully on the designed pixel to study electrochromism over the pixels. An electrochemical fibre transistor is designed successfully using the polymer coated fibres. / Polymer Electrochromism on PEDOT coated fibres

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<p>Polymer electrochromism on PEDOT coated fibres was successfully achieved. The electrochromic property of the PEDOT polymer is an excellent property. This feature gives way to many more research works at present and in the future also. The electrochromic property of the PEDOT polymer is utilized in this thesis work to design an electrochromic display pixel.</p><p> </p><p>The polymer coating over the fibres were obtained by using In-situ polymerization technique. The coated-fibres were used to design a display-pixel. Electrochemistry is performed successfully on the designed pixel to study electrochromism over the pixels. An electrochemical fibre transistor is designed successfully using the polymer coated fibres.</p> / Polymer Electrochromism on PEDOT coated fibres

Le développement des technologies sub-microniques a permis un regain d'intérêt pour les capteurs d'images CMOS, qui inondent aujourd'hui le marché des capteurs. Les approches conventionnelles pour la conception de machines de vision sont en général basées sur des architectures connectées à une caméra. L'approche proposée dans ce travail consiste à associer, dans un même circuit – une rétine CMOS -, les photocapteurs et des fonctions de pré-traitement de l'image, permettant ainsi de répartir et d'optimiser le traitement. Ces rétines ont des performances en vitesse, en intégration et en consommation meilleures que les solutions classiques (capteurs puis traitements logiciels et/ou matériels). Cette thèse porte plus précisément sur l'intégration d'un algorithme d'estimation du mouvement en transposant le calcul numérique fortement itératif en une structure de calcul électronique. Après avoir réalisé un circuit permettant d'acquérir des connaissances dans le domaine des capteurs d'images CMOS, nous avons conçu un circuit de vision estimant le mouvement. Cette estimation de mouvement est basée sur une méthode robuste de mise en correspondance de blocs de pixels, comprenant une phase de pré-codage des pixels suivi<br />d'une recherche de ce codage dans une fenêtre de destination potentielle. Cette approche est novatrice car elle propose une rétine CMOS pouvant traiter (électroniquement) des scènes fortement texturées, et à luminosité changeante, en s'appuyant sur une méthode jusqu'alors réservée aux approches numériques (FPGA, DSP) ou logicielles.

The goal of this work is to extend the state-of-the-art in digital medical X-ray imaging as it pertains to real-time, low-noise imaging and multi-mode imager functionality. One focus of this research in digital flat-panel imagers is to increase the detective quantum efficiency, particularly at low X-ray exposures, in order to enable low-noise imaging applications such as fluoroscopy or tomographic mammography. Another focus of this research is in the creation of a multi-mode imager, such as a combined radiographic and fluoroscopic (R&F) imager, which will reduce hospital costs, both in terms of equipment acquisition and storage space. To that end, we propose a novel three-transistor multi-mode digital flat-panel imager with a dynamic range capable for use in R&F applications, with a particular focus on noise optimization for low-noise real-time digital flat-panel X-ray fluoroscopy. This work involves the derivation and optimization of the total input referred noise of an active pixel sensor (APS) in terms of the on-pixel thin-film transistor device dimensions. It is determined that in order to minimize noise, all non-transistor capacitances at the pixel sense node needed to be minimized. This leads to a design where the on-pixel storage capacitance is eliminated; and instead the gate capacitance of the sense-node transistor is used to store the incoming X-ray converted charge. This work allows researchers to gain insight into the fundamental noise operation of active pixels used in medical imaging, and to appropriately choose device dimensions. Due to the inherent large feature sizes of thin-film transistors, active pixel flat-panel X-ray medical imagers offer lower resolution than their film-screen counterparts. By demonstrating the desirability of smaller device dimensions for reduced noise and the elimination of a storage capacitor, this research frees some of the area constraints that exist in active pixel flat-panel imagers, allowing for smaller pixels, and thus higher resolution medical imagers. The noise analysis and optimization as a function of pixel TFT device dimensions in this work is applicable to any amorphous silicon (a-Si) based charge-sensitive pixel, and is easily extended to other device technologies such as polysilicon (poly-Si). iv In addition, experimental results of a 64x64 pixel four-transistor APS imaging array fabricated in a-Si technology and mated with an a-Se photoconductor for use in medical X-ray imaging is presented. MTF results and transient response in the presence of X-rays (image lag) for the APS array are poor, which is ascribed to high charge trapping at the silicon nitride/a-Se interface. Improvements to the silicon nitride passivation layer and pixel layout are suggested to reduce this charge trapping. The prototype imager is compared directly with a state-of-the-art a-Si PPS imaging array and demonstrates good SNR performance for X-ray exposures down to 1.5μR. Pixel design and fabrication process improvements are suggested for low-exposure APS testing and improved low-noise performance.