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abstract: Pb-free solders are used as interconnects in various levels of micro-electronic packaging. Reliability of these interconnects is very critical for the performance of the package. One of the main factors affecting the reliability of solder joints is the presence of porosity which is introduced during processing of the joints. In this thesis, the effect of such porosity on the deformation behavior and eventual failure of the joints is studied using Finite Element (FE) modeling technique. A 3D model obtained by reconstruction of x-ray tomographic image data is used as input for FE analysis to simulate shear deformation and eventual failure of the joint using ductile damage model. The modeling was done in ABAQUS (v 6.10). The FE model predictions are validated with experimental results by comparing the deformation of the pores and the crack path as predicted by the model with the experimentally observed deformation and failure pattern. To understand the influence of size, shape, and distribution of pores on the mechanical behavior of the joint four different solder joints with varying degrees of porosity are modeled using the validated FE model. The validation technique mentioned above enables comparison of the simulated and actual deformation only. A more robust way of validating the FE model would be to compare the strain distribution in the joint as predicted by the model and as observed experimentally. In this study, to enable visualization of the experimental strain for the 3D microstructure obtained from tomography, a three dimensional digital image correlation (3D DIC) code has been implemented in MATLAB (MathWorks Inc). This developed 3D DIC code can be used as another tool to verify the numerical model predictions. The capability of the developed code in measuring local displacement and strain is demonstrated by considering a test case. / Dissertation/Thesis / M.S. Mechanical Engineering 2011

The constitutive mechanical behaviour with a focus on creep of Sn-Pb and various Sn-Ag-Cu based Pb-free solders in the 25-150°C temperature range has been studied using nanoindentation and various new meso-scale tests. All alloys have been studied as bulk wave soldering bars, as-received solder balls and solder joints. Ball Grid Array (BGA) solder joints in a typical electronic configuration were manufactured in-house using both Cu and Pd-Ag metallizations. Microstructural characterisation of all configurations used various types of optical and electron microscopy and showed that the solder pad metallization type played a major role in intermetallic compound (IMC) formation. There were comparatively fine and coarse-grained microstructures in both as-received solder balls and BGA solder joints depending on ball diameter. Nanoindentation creep measurements in the stress range 20-500MPa showed that grain boundary sliding occurred together with dislocation glide and dislocation climb in the low temperature (25-50°C) and high temperature (100-150°C) regimes respectively. Smaller grain sizes (<20µm) encouraged grain boundary sliding that enhanced creep. New elevated temperature mechanical tests were developed using the nanoindentation platform to enable testing of entire solder joints in shear and compression, with stresses in the 1E-2 - 3MPa range, more relevant to in-service conditions than those in nanoindentation. Meso-scale spherical indentation creep behaviour in compression on as-reflowed solder balls showed good agreement with that obtained by conventional nanoindentation. However, when BGAs were tested in shear, the solder microstructure had relatively little influence on the creep response, which was significantly less creep resistant than individual phases in the ball obtained by nanoindentation or the ball itself obtained by meso-scale spherical indentation. In shear, the creep conformed to diffusion controlled behaviour and interfacial microstructure was suggested to now control creep response, with the microstructure of the majority of the solder joint playing only a minor role.

For years, the alloy of choice for electroplating electronic components has been tin-lead (Sn-Pb) alloy. However, the legislation established in Europe on July 1, 2006, required significant lead (Pb) content reductions from electronic hardware due to its toxic nature. A popular alternative for coating electronic components is pure tin (Sn). However, pure tin has the tendency to spontaneously grow electrically conductive Sn whisker during storage. Sn whisker is usually a pure single crystal tin with filament or hair-like structures grown directly from the electroplated surfaces. Sn whisker is highly conductive, and can cause short circuits in electronic components, which is a very significant reliability problem. The damages caused by Sn whisker growth are reported in very critical applications such as aircraft, spacecraft, satellites, and military weapons systems. They are also naturally very strong and are believed to grow from compressive stresses developed in the Sn coating during deposition or over time. The new directive, even though environmentally friendly, has placed all lead-free electronic devices at risk because of whisker growth in pure tin. Additionally, interest has occurred about studying the nature of other metal whiskers such as zinc (Zn) whiskers and comparing their behavior to that of Sn whiskers. Zn whiskers can be found in flooring of data centers which can get inside electronic systems during equipment reorganization and movement and can also cause systems failure.Even though the topic of metal whiskers as reliability failure has been around for several decades to date, there is no successful method that can eliminate their growth. This thesis will give further insights towards the nature and behavior of Sn and Zn whiskers growth, and recommend a novel manufacturing technique that has potential to mitigate metal whiskers growth and extend life of many electronic devices.

In past years, legislative pressures (particularly in Japan and Europe) had forced the electronics industry to eliminate Pb from their end products and manufacturing processes. With respect to factors such as ease of converting existing tin-lead plating systems, ease of manufacture and compatibility with existing assembly methods, pure tin plating is seen by many in the industry as a potentially simple and cost effective alternative to SnPb-based systems. The problem of spontaneous tin whisker formation, a characteristic of pure tin, still needs to be addressed, as it can lead to device failure by shorting two terminals on electronic devices. This possibility gives rise to major reliability concerns. The study relates to an electronic component with pure tin deposit layer on the part for electric connection, wherein pure tin deposit layer is a fine grained tin deposit layer composed of grains with smaller size in the direction perpendicular to the deposit surface than in the direction parallel to the deposit surface. It is called irregular tin grain structure. It applies a process for plating an electronic component, so as to form a pure tin deposit layer on the part for electric connection, comprising the steps of: adjusting the composition of tin plating solution in which starter additive and brighter additive are included; moving the electronic component through the tin plating solution, so as to form a fine grained tin deposit layer on the part for electric connection. We performed a DoE by depositing different tin grain structures with variant thickness. After whisker test in high temperature/high humidity and room condition, we confirmed corrosion mechanism, intermetallic morphology, and different behaviour of tin atoms. To summarize the studies, as compared with the prior arts, irregular grain structure can validly inhibit the whisker growth.

The effects of intermetallic compound (IMC) formation on reliability of Pb-free Sn-based solders for flip chip and three-dimensional (3D) interconnects were studied. The dissertation is organized into four parts. In the first part, the effect of Sn grain orientation on electromigration (EM) reliability of Pb-free Sn-based flip chip solder joints was studied. The Sn grain microstructure in flip chip solder joints was characterized using the electron backscatter diffraction (EBSD) technique, and wa found to be closely related to the EM failure mechanims. The approach to grain structure optimization for improved EM reliability was also explored. In addition to the experimental work, a kinetic analysis was formulated to investigate the early EM degradation mechanism in Sn-based solder joints with Ni under-bump metallization (UMB). The aforementioned kinetic analysis, the intrinsic diffusion coefficients were not readily available in the literature. In the second part of the work, a Monte Carlo method known as simulated annealing was applied to estimate the unknown diffusion coefficients using a multi-parameter optimization method by fitting to experimental measurements. The intrinsic diffusion coefficients of Ni and Sn in Ni₃Sn₄ between 150 and 200°C, and those of Cu and Sn in Cu₃Sn and Cu₆Sn₅ between 120 and 200°C were estimatd. The activation energies for these diffusion coefficients were also determined. Together, this provides the diffusivity parameters to predict the intermetallic growth as a function of temperature. The third objective focused on the EM reliability of Sn-based microbump joints in 3D interconnects with through-silicon vias (TSVs). No EM-induced bump failure was observed, showing a robust EM reliability in microbumps. High temperature thermal annealing test was also performed on microbumps with three different metallizations in an effort to explore structural and process optimization. Finally, interfacial reaction induced stress in IMC microbumps was investigated. A numerial analysis was formulated to study the concurrent diffusion, phase transformation, and deformation in the process of IMC formation. Stress generation due to unbalanced diffusion rates and volumetric change upon phase transformation was considered. The coupled analysis was applied to investigate Ni₃Sn₄ growth in the Ni-Sn microbumping system. A simulation approach based on finite difference method with moving boundaries was employed to numerically solve stress evolution in Ni₃Sn₄. The equilibrium stress was also investigated using a modified model with a finite thickness of solder. Simulation predictions were found to be in good qualitative agreement with experimental observations. / text

Pb-free piezoelectric materials have grown in importance through increased environmental concern related to the presence of Pb and the subsequent legislation that has arisen including directives such as Waste Electrical and Electronic Equipment (WEEE) and the Restriction of Hazardous Substances Directive (RoHS). While much progress has been made on producing Pb-free bulk materials, the need to integrate these next generation Pb-free piezoelectric materials with substrates to form functional micro devices has received less attention and raises a number of challenges. With respect to the high temperature mixed oxide synthesis method, a simple, cost effective and robust low temperature molten hydroxide synthesis (MHS) method derived from the molten salt synthesis (MSS) method, has been developed to produce K0.5Na0.5NbO3 (KNN) small grain powders and is a method that lends itself easily to industrial scale up. A powder/sol gel composite ink film forming technique has been used to produce KNN thick films on silicon substrates. Characterisation of the produced films has shown the films to exhibit piezoelectric coefficients for un-doped material in the region of 30pC/N. The work will report on the Na ion favouring mechanism of the MSS and the related mechanism of the MHS. The work will also report on the dielectric and piezoelectric characteristics of initial KNN thick films produced and an investigation into use of dopants and process modification to improve the KNN thick film’s characteristics.

abstract: The mechanical behavior of Pb-free solder alloys is important, since they must maintain mechanical integrity under thermomechanical fatigue, creep, and mechanical shock conditions. Mechanical shock, in particular, has become an increasing concern in the electronics industry, since electronic packages can be subjected to mechanical shock by mishandling during manufacture or by accidental dropping. In this study, the mechanical shock behavior of Sn and Sn-Ag-Cu alloys was systematically analyzed over the strain rate range 10-3 - 30 s-1 in bulk samples, and over 10-3 - 12 s-1 on the single solder joint level. More importantly, the influences of solder microstructure and intermetallic compounds (IMC) on mechanical shock resistance were quantified. A thorough microstructural characterization of Sn-rich alloys was conducted using synchrotron x-ray computed tomography. The three-dimensional morphology and distribution of contiguous phases and precipitates was analyzed. A multiscale approach was utilized to characterize Sn-rich phases on the microscale with x-ray tomography and focused ion beam tomography to characterize nanoscale precipitates. A high strain rate servohydraulic test system was developed in conjunction with a modified tensile specimen geometry and a high speed camera for quantifying deformation. The effect of microstructure and applied strain rate on the local strain and strain rate distributions were quantified using digital image correlation. Necking behavior was analyzed using a novel mirror fixture, and the triaxial stresses associated with necking were corrected using a self-consistent method to obtain the true stress-true strain constitutive behavior. Fracture mechanisms were quantified as a function of strain rate. Finally, the relationship between solder microstructure and intermetallic compound layer thickness with the mechanical shock resistance of Sn-3.8Ag-0.7Cu solder joints was characterized. It was found that at low strain rates the dynamic solder joint strength was controlled by the solder microstructure, while at high strain rates it was controlled by the IMC layer. The influences of solder microstructure and IMC layer thickness were then isolated using extended reflow or isothermal aging treatments. It was found that at large IMC layer thicknesses the trend described above does not hold true. The fracture mechanisms associated with the dynamic solder joint strength regimes were analyzed. / Dissertation/Thesis / Ph.D. Materials Science and Engineering 2012

abstract: Microelectronic industry is continuously moving in a trend requiring smaller and smaller devices and reduced form factors with time, resulting in new challenges. Reduction in device and interconnect solder bump sizes has led to increased current density in these small solders. Higher level of electromigration occurring due to increased current density is of great concern affecting the reliability of the entire microelectronics systems. This paper reviews electromigration in Pb- free solders, focusing specifically on Sn0.7wt.% Cu solder joints. Effect of texture, grain orientation, and grain-boundary misorientation angle on electromigration and intermetallic compound (IMC) formation is studied through EBSD analysis performed on actual C4 bumps. / Dissertation/Thesis / M.S. English 2013

L’assemblage et le conditionnement en électronique représentent un enjeu de création de nouveaux systèmes électroniques hybrides rassemblant sur un même substrat des éléments électroniques, optiques, mécaniques… La technologie Flip-chip , introduite par IBM et baptisée C4 (Control Collapse Chip Connection), garantit une plus grande densité d’intégration tout en gardant les mêmes dimensions de puce. Au coeur de cette technologie, le « Bumping » est un procédé qui consiste en l’introduction d’une microbille conductrice entre deux plots de connexion des puces afin de réaliser une liaison électrique et mécanique avec le niveau de packaging suivant. La technique de dépôt par sérigraphie de pâte à braser est récemment devenue pratique en raison de son adaptation aux alliages sans plomb. Cette méthode présente l'avantage d'un faible coût et d'une possible production à grande échelle. Nous avons donc choisi de développer cette technique afin d’obtenir des matrices de connexions électriques de dimensions comprises entre 50 μm et 100 μm, pour une pâte à braser de type Sn3.0Ag0.5Cu. Nous avons déterminé les paramètres de sérigraphie afin d’obtenir un minimum d’étalement de pâte pour un remplissage maximum des ouvertures du masque choisi en Ni-électroformé d’épaisseur 50μm : une vitesse de racle de 20mm/s et une vitesse de démoulage de 4mm/s sont par exemple à retenir pour une pâte de type 5. L’étude du masque de sérigraphie a conduit au choix d’ouvertures circulaires. Des formes de billes circulaires ont été obtenues pour des UBM (Under Bump Metallurgy) également circulaires, de diamètre ¼ et ½ le diamètre de l’ouverture du masque. L’optimisation du profil de refusion a permis de déterminer qu’un palier à 180°C, un TAL de 90s ou plus et une température maximale à 250°C favorisaient l’obtention de billes circulaires avec absence de vides. Pour une pâte de type 6, des billes de 60à 70μm de diamètre ont été obtenues pour des ouvertures de masque de 100μm. Une étude de fiabilité de ces billes à partir de tests de cisaillement et de l’analyse des IMC (composés intermétalliques) formés après refusion a permis de montrer que des UBM en Cr-Cu-Au, de diamètre égal à la moitié de l’ouverture du masque, permettaient d’assurer un meilleur maintien mécanique des billes / The semiconductor industry has continuously improved its products by increasing the density of integration resulting in an increasing of the I/Os, always with a low cost requirement. To obtain high-density and high-speed packaging, the Flip-Chip interconnection technology was introduced by IBM also called C4 (Control Collapse Chip Connection). Solder bumps have been widely used in electronic industry and were generally based on the Sn-Pb alloy, for its low melting point and good wetting property. Containing highly toxic element (Pb), Pb-Sn solder alloy has been banned. The ternary alloy Sn-Ag-Cu seems to be the best compromise, in fact it as physical and chemical characteristics equivalent to that of Sn-Pb.In this study we are interested to optimize stencil printing process and adjust it with the flip-chip technology, in order to obtain solder bumps which height is between 50µm and 100µm associated to pitches less than or equal to 200µm, using Sn-3.0Ag-0.5Cu solder paste. We have optimized the stencil printing parameters machine, the stencil apertures shape and size (circular shape and 50µm height, for a Ni-electroformed stencil). Spherical solder balls have been achieved with circular UBM (Under Bump Metallurgy), which diameter is ¼ and ½ the diameter of the stencil aperture. The reflow thermal profile is the key to the formation of a reliable solder bump. It must allow a homogeneous reflow for all particles of the metallic solder paste. We define a thermal profile with a Time above liquidus (TAL) of 90s, a temperature in soaking zone (Ts) of 180°C and a maximum temperature (Tmax) of 250°C. For type 6 solder pastes, balls of 60-70µm diameter have been obtained for 100µm stencil apertures.The quality of a solder joint is directly related to the adhesion of the solder ball to the substrate. Among the various methods of mechanical testing, shear testing is the most widely used to assess the strength of the attachment of beads to the substrate and determine the fragility of the ball at the interface caused by the intermetallic layer compounds (IMC) formed after the reflow step. We have shown that Cr-Cu-Au UBM, with a diameter equal to the half of the stencil aperture, ensure the mechanical adhesion of the balls