In today’s modern society, we are surrounded by a multitude of digital devices.The number of available digital devices is set to grow even more. As the trendcontinues, product life-cycle is a major issue in mass production of these devices.Testing and verification is responsible for a significant percentage of the productioncost of digital devices. Time efficient procedures for testing and characterization aretherefore sought for. Moreover, the need for flexible and low-cost solutions in thedesign architecture of radio frequency devices coupled with the demand for highdata rate has presented a challenge caused by interferences from the analog circuitparts. Study of digital signal processing based techniques which would alleviate theeffects of the analog impairments is therefore a pertinent subject. In the first part of this thesis, we address parameter estimation based on wave-form fitting. We look at the sinewave model for parameter estimation which iseventually used to characterize the performance of a device. The underlying goal isto formulate and analyze a set of new parameter estimators which provide a moreaccurate estimate than well known estimators. Specifically, we study the maximum-likelihood (ML) SNR estimator employing the three-parameter sine fit and derivealternative estimator based on its statistical distribution. We show that the meansquare error (MSE) of the alternative estimators is lower than the MSE of the MLestimator for a small sample size and a few of the new estimators are very close tothe Cramér-Rao lower bound (CRB). Simply put, the number of acquired measure-ment samples translate to measurement time, implying that the fewer the numberof samples required for a given accuracy, the faster the test would be. We alsostudy a sub-sampling approach for frequency estimation problem in a dual channelsinewave model with common frequency. Coprime subsampling technique is usedwhere the signals from both channels are uniformly subsampled with coprime pairof sparse samplers. Such subsampling technique is especially beneficial to lower thesampling frequency required in applications with high bandwidth requirement. TheCRB based on the co-prime subsampled data set is derived and numerical illus-trations are given showing the relation between the cost in performance based onthe mean squared error and the employed coprime factors for a given measurementtime. In the second part of the thesis, we deal with the problem of phase-noise (PHN).First, we look at a scheme in orthogonal frequency-division multiplexing (OFDM)system where pilot subcarriers are employed for joint PHN compensation, channelestimation and symbol detection. We investigate a method where the PHN statis-tics is approximated by a finite number of vectors and design a PHN codebook. Amethod of selecting the element in the codebook that is closest to the current PHNrealization with the corresponding channel estimate is discussed. We present simula-tion results showing improved performance compared to state-of-the art techniques.We also look at a sequential Monte-Carlo based method for combined channel im-pulse response and PHN tracking employing known OFDM symbols. Such techniqueallows time domain compensation of PHN such that simultaneous cancellation ofthe common phase error and reduction of the inter-carrier interference occurs. / <p>QC 20150529</p>

The work presented in this thesis fits within the broader area of fiber optics communications. This is an important area of research as it provides a breeding ground for the present and future technologies supporting the Internet. Due to the ever-increasing bandwidth demands worldwide, the network infrastructures that make up the Internet are continuously being upgraded. This thesis aims to identify key segments of the Internet that are deemed to become the Internet's bottleneck if new technology does not replace the current one. These are datacenter intra and inter-connects, and metropolitan core area networks. In each category, we provide a comprehensive overview of the state of the art, identify key impairments affecting data transmission, and suggest solutions to overcome them.   For datacenter intra and inter-connects, the key impairments are lack of bandwidth from electro-optic devices, and dispersion. Solutions attempting to tackle these impairments must be constrained by cost and power consumption. The provided solution is MultiCAP, an alternative advanced modulation format that is more tolerable to dispersion and provides bandwidth management features, while being flexible enough to sacrifice performance in order to gain simplicity. MultiCAP was the first advanced modulation format to achieve over 100~Gb/s in 2013 for a data-center interconnect and set the world record on data transmission over a single VCSEL in 2014 for a short reach data link.    On metro-core networks, the challenge is to efficiently mitigate carrier induced frequency noise generated by modern semiconductor lasers. We point out that, when such lasers are employed, the commonly used laser linewidth fails to estimate system performance, and we propose an alternative figure of merit we name "Effective Linewidth". We derive this figure of merit analytically, explore it by numerical simulations and experimentally validate our results by transmitting a 28~Gbaud DP-16QAM over an optical link. / <p>QC 20170602</p> / GRIFFON

Au cours des dernières décennies, l’industrie de la micro-électronique a connu une large démocratisation de l’utilisation des applications de télécommunication. L’amélioration des procédés de conception et de fabrication ont permis de produire des circuits analogiques, mixtes et radiofréquences complexes et hautes performances pour ces applications. Toutefois, le coût de test de ces circuits intégrés représente encore une large part du coût de fabrication. En effet, très souvent, tester des fonctions analogiques ne se résume pas à un test fonctionnel mais signifie mesurer les spécifications du circuit. Ces mesures nécessitent l’utilisation d’instruments dédiés bien plus couteux que les ressources numériques disponibles sur un équipement de test industriel standard. Une des spécifications essentielle mais couteuse à caractériser pour les circuits RF est le niveau de bruit de phase. La technique actuellement utilisée en industrie consiste à capturer le signal à l’aide d’un canal testeur analogique équipé d’un convertisseur analogique-numérique hautes performances ; une transformée de Fourier est alors appliquée sur le signal numérisé et le bruit de phase est mesuré sur le spectre résultant. L’approche proposée dans cette thèse consiste à réaliser la mesure de bruit de phase en n’utilisant que des ressources digitales faible coût. L’idée fondamentale consiste à réaliser la capture 1-bit du signal analogique avec un canal numérique standard et à développer des algorithmes de post-traitement dédiés permettant de retrouver l’information relative au bruit de phase à partir d’une évaluation des temps de passages à zéro du signal. Deux méthodes sont présentées. La première méthode est basée sur une estimation de la fréquence instantanée du signal et une analyse de la dispersion induite par le bruit de phase. Cette méthode impose une contrainte forte quant à la fréquence d’échantillonnage à utiliser et s’est révélée sensible au bruit d’amplitude, limitant la gamme de mesures possibles. Une seconde méthode est alors proposée afin de s’affranchir de ces limitations. A partir de la capture binaire du signal analogique, une reconstruction de la phase instantanée du signal est réalisée, puis filtrée puis caractérisée grâce à un outil usuel d’évaluation de stabilité fréquentielle : la variance d’Allan. Cette technique, robuste au bruit d’amplitude et au jitter, peut être paramétrée et permet une caractérisation efficace du bruit de phase sans contrainte fondamentale. En plus des simulations, ces techniques font l‘objet d’une étude stochastique et sont validées expérimentalement sur différents types de signaux à mesurer – générés artificiellement ou provenant de puces sur le marché – et avec différentes conditions mesures – sur oscilloscope ou sur testeur industriel, en laboratoire et en production –. Une implémentation sur puce est aussi proposée et validée avec un prototype sur FPGA. / In recent decades, the microelectronics industry has experienced a wide democratization of the use of telecommunication applications. The improved process design and manufacturing have produced complex and high performance analog, mixed and radio frequency circuits for these applications. However, the test cost of these integrated circuits still represents a large part of the manufacturing cost. Indeed, very often, analog testing is not just a functional test but needs measurements for specification validations. These measurements require the use of dedicated instruments expensive resources on standard industrial test equipment.One of the essential but costly specifications to validate in RF circuitry is the phase noise level. The currently used industrial technique consists in capturing the signal from the circuit under test using an RF tester channel equipped with a high performance analog to digital converter; a Fourier transform is then applied to the digitized signal and the phase noise is measured on the resulting spectrum.The approach proposed in this thesis is to achieve the phase noise measurement using solely digital low-cost resources. The basic idea is to perform 1-bit capture of the analog signal with a standard digital channel and develop post-processing algorithms dedicated for phase noise evaluation from the zero-crossings of the signal.Two methods are presented. The first method is based on an estimate of the instantaneous signal frequency and an analysis of their dispersion induced by phase noise. This method imposes a strong constraint on the sampling frequency to be used and proved to be sensitive to noise amplitude, limiting the range of possible measures. A second method is then proposed to overcome these limitations. From the binary capture of the analog signal, a reconstruction of the instantaneous phase of the signal is carried out, then filtered and characterized by a common tool of frequency stability assessment: the Allan variance. This technique, robust to amplitude noise and jitter, can be parametrized and enables efficient characterization of phase noise without fundamental constraint.In addition to the simulations, these techniques are subject to a stochastic study and are validated experimentally on different types of signals to be measured - artificially generated or from chips on the market - and with different measuring instruments - on oscilloscope or industrial tester, in laboratory and on a production line-. An On-chip implementation is also proposed and validated with a FPGA prototype.

Modern communication systems require high performance radio frequency (RF) and microwave circuits and devices. This is becoming increasingly challenging to realize in the content of cost/size constraints. Integrated circuits (ICs) satisfy the cost/size requirement, but performance is often sacri¯ced. For instance, high quality factor (Q factor) passive components are difficult to achieve in standard silicon-based IC processes.<p>In recent years, microelectromechanical systems (MEMS) devices have been receiving increasing attention as a possible replacement for various on-chip passive elements, offering potential improvement in performance while maintaining high levels of integration. Variable capacitors (varactor) are common elements used in various applications. One of the MEMS variable capacitors that has been recently developed is built using deep X-ray lithography (as part of the LIGA process). This type of capacitor exhibits high quality factor at microwave frequencies.<p>The complementary metal oxide semiconductor (CMOS) technology dominates the silicon IC process. CMOS becomes increasingly popular for RF applications due to its advantages in level of integration, cost and power consumption. This research demonstrates a CMOS voltage-controlled oscillator (VCO) design which is used to investigate methods, advantages and problems in integrating LIGA-MEMS devices to CMOS RF circuits, and to evaluate the performance of the LIGA-MEMS variable capacitor in comparison with the conventional on-chip CMOS varactor. The VCO was designed and fabricated using TSMC 0.18 micron CMOS technology. The core of the VCO, including transistors, resistors, and on-chip inductors was designed to connect to either an on-chip CMOS varactor or an off-chip LIGA-MEMS capacitor to oscillate between 2.6 GHz and 2.7 GHz. Oscillator phase noise analysis is used to compare the performance between the two capacitors. The fabricated VCO occupied an area of 1 mm^2.<p>This initial attempt at VCO fabrication did not produce a functional VCO, so the performance of the capacitors with the fabricated VCO could not be tested. However, the simulation results show that with this LIGA-MEMS capacitor, a 6.4 dB of phase noise improvement at 300 kHz offset from the carrier is possible in a CMOS-based VCO design.

This thesis concerns the effect of phase noise (PHN) on multi-carrier systems such as OFDM and the detection of multi-carrier symbols affected by PHN. It is known that PHN causes mixing between sub-carriers resulting in inter-carrier interference (ICI) and rotates symbols on every sub-carrier by a certain angle called the common phase error (CPE). We explore how these two effects arise and show that these two effects are coupled to each other. We also note that higher order M-QAM constellations like 64-QAM are more sensitive to CPE than smaller constellations like 4-QAM. Based on our observations on CPE, we propose a blind CPE estimation algorithm. We then address the issue of ICI and propose a turbo receiver design to mitigate it.

This thesis concerns the effect of phase noise (PHN) on multi-carrier systems such as OFDM and the detection of multi-carrier symbols affected by PHN. It is known that PHN causes mixing between sub-carriers resulting in inter-carrier interference (ICI) and rotates symbols on every sub-carrier by a certain angle called the common phase error (CPE). We explore how these two effects arise and show that these two effects are coupled to each other. We also note that higher order M-QAM constellations like 64-QAM are more sensitive to CPE than smaller constellations like 4-QAM. Based on our observations on CPE, we propose a blind CPE estimation algorithm. We then address the issue of ICI and propose a turbo receiver design to mitigate it.

El objetivo de la tesis es estudiar en términos del ruido de fase, el diseño de osciladores de microondas sintetizados. La tesis realiza una revisión tecnológica de los componentes habitualmente empleados, en términos de ruido de fase, estableciendo las prestaciones y limitaciones de los subsistemas, analizando e incorporando las no alinealidades al método de diseño.Asimismo se realiza una caracterización experimental consistente en la medida del ruido de fase de los subsistemas y en la propuesta de un método innovador para la medida de la función de transferencia del pll. La tesis establece a partir de un catalogo de medidas, los criterios de diseño a seguir para la optimización de un oscilador sintetizado a frecuencias de microondas.

Modern communication systems require high performance radio frequency (RF) and microwave circuits and devices. This is becoming increasingly challenging to realize in the content of cost/size constraints. Integrated circuits (ICs) satisfy the cost/size requirement, but performance is often sacri¯ced. For instance, high quality factor (Q factor) passive components are difficult to achieve in standard silicon-based IC processes.<p>In recent years, microelectromechanical systems (MEMS) devices have been receiving increasing attention as a possible replacement for various on-chip passive elements, offering potential improvement in performance while maintaining high levels of integration. Variable capacitors (varactor) are common elements used in various applications. One of the MEMS variable capacitors that has been recently developed is built using deep X-ray lithography (as part of the LIGA process). This type of capacitor exhibits high quality factor at microwave frequencies.<p>The complementary metal oxide semiconductor (CMOS) technology dominates the silicon IC process. CMOS becomes increasingly popular for RF applications due to its advantages in level of integration, cost and power consumption. This research demonstrates a CMOS voltage-controlled oscillator (VCO) design which is used to investigate methods, advantages and problems in integrating LIGA-MEMS devices to CMOS RF circuits, and to evaluate the performance of the LIGA-MEMS variable capacitor in comparison with the conventional on-chip CMOS varactor. The VCO was designed and fabricated using TSMC 0.18 micron CMOS technology. The core of the VCO, including transistors, resistors, and on-chip inductors was designed to connect to either an on-chip CMOS varactor or an off-chip LIGA-MEMS capacitor to oscillate between 2.6 GHz and 2.7 GHz. Oscillator phase noise analysis is used to compare the performance between the two capacitors. The fabricated VCO occupied an area of 1 mm^2.<p>This initial attempt at VCO fabrication did not produce a functional VCO, so the performance of the capacitors with the fabricated VCO could not be tested. However, the simulation results show that with this LIGA-MEMS capacitor, a 6.4 dB of phase noise improvement at 300 kHz offset from the carrier is possible in a CMOS-based VCO design.

This dissertation explores high-speed silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) bipolar complementary metal oxide semiconductor (BiCMOS) circuits for next-generation ground- and space-based millimeter-wave (MMW >= 30 GHz) communication front-ends and X-band (8 to 12 GHz) radar (radio detection and ranging) modules. The requirements of next-generation transceivers, for both radar and communication applications, are low power, small size, light weight, low cost, high performance, and high reliability. For this purpose, the high-speed circuits that satisfy the demanding specifications of next-generation transceivers are implemented in SiGe HBT BiCMOS technology, and the device-circuit interactions of SiGe HBTs to transceiver building blocks for performance optimization and radiation tolerance are investigated. For X-band radar module components, the dissertation covers: (1) The design of an ultra-low-noise X-band SiGe HBT low-noise-amplifier (LNA). (2) The design of low-loss shunt and series/shunt X-band Si CMOS single-pole double-throw (SPDT) switches. (3) The design of a low-power X-band SiGe HBT LNA for near-space radar applications. For MMW communication front-end circuits, the dissertation covers: (4) The design of an inductorless SiGe HBT ring oscillator for MMW operation. (5) The study of emitter scaling and device biasing on MMW SiGe HBT voltage-controlled oscillator (VCO) performance. (6) The study of proton radiation on MMW SiGe HBT transceiver building blocks.

The thesis uses an up-down conversion architecture to realize a wideband frequency synthesizer for digital video broadcasting (DVB) transmission system. At first, the theoretical analysis of this architecture is performed to understand the mechanism to suppress the phase noise in an optimal way. Then, the simulations using Matlab and ADS are carried out to predict the phase noise performance. Based on the above efforts, a 50 MHz ~ 1 GHz wideband frequency synthesizer hybrid circuit is implemented and its phase noise performance, corresponding to different choices of the reference sources, is finally discussed. The second part of this thesis is to extend the up-down conversion architecture to an offset phase-locked loop (PLL) architecture for wideband frequency synthesizers. The difference from the conventional offset PLLs is the phase locking of the signal at either the sum or the difference frequency of two voltage-controlled oscillators (VCOs) to the reference source for the purpose of wideband operation. The phase noise analysis of the proposed offset PLL architecture is provided. In the experiments, a 300 MHz ~ 3.6 GHz wideband frequency synthesizer hybrid circuit is implemented to verify the analyzed phase noise results. In addition, a CMOS wideband frequency synthesizer chip using the proposed offset PLL architecture has been realized. Moreover, another two CMOS wideband frequency synthesizer chips are included in this thesis. It is worth mentioning that the VCOs in these two frequency synthesizer chips use the switched capacitor and inductor techniques to achieve a wideband operation.