Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2006. / Swaminathan, Madhavan, Committee Chair ; Cressler, John D., Committee Co-Chair ; Kenney, Stevenson J., Committee Member ; Peterson, Andrew, Committee Member ; Durgin, Gregory, Committee Member ; Sitaraman, Suresh, Committee Member.

Thesis (Ph. D.)--Oregon State University, 2007. / Printout. Includes bibliographical references (leaves 107-110). Also available online.

O presente trabalho propõe-se a oferecer respostas à questão de como a informação é preservada num sistema, focalizando-se na distinção entre os papéis desempenhados pelos constituintes elementares e pelos estruturais na preservação da memória desse sistema. Os sistema simulados circunscreveram-se a malhas, com diferentes graus de regularidade, compostas pelo acoplamento de osciladores não-lineares que apresentam comportamento coerente no estado de equilíbrio. Malhas de Sincronismo de Fase, também conhecidas por PLLs (Phase Locked Loops), foram adotadas como elementos constituintes básicos dos sistemas analisados. Para tanto, utilizou-se a plataforma de cálculo MATLAB-SIMULINK, acompanhando-se as evoluções dos diversos sistemas e de seus parâmetros dinâmicos associados, possibilitando o estabelecimento da correspondência entre os valores dos referidos parâmetros dinâmicos com parâmetros gráficos \"sensíveis\" à estrutura das malhas. Os resultados obtidos indicam a coexistência/cooperação das componentes estrutural e elementar na determinação dos valores dos parâmetros dinâmicos no estado de equilíbrio do sistema. No entanto, evidencia-se que tais componentes apresentam importâncias distintas na determinação dos diferentes parâmetros dinâmicos. / This work was conceived aiming to present some answers to how the information is preserved in a system. The focus was laid on the distinction between the tasks played by the elementary components and the structure of the system. The simulated systems were composed by coupled oscillators, more precisely by PLLs (Phase Locked Loops), arranged in networks of different regularities. Simulations were performed using Matlab-Simulink software to build a correlation between the final state dynamical parameters of the system and its degree of regularity. Results show the influence of both elementary and structural components on the system attained state. However the responses of characteristics parameters of the system to changes in the regularity of the structured network may greatly differ from one parameter to another. This behavior may suggest different strategies to preserve information of the system according to the information to be kept.

In recent years, neuromorphic architectures have been an increasingly effective tool used to solve big data problems. Hardware neural networks have not been able to fully exploit the power efficient properties of the neural paradigm, however, due to limitations in standard CMOS. One of the largest challenges is the quadratic scaling of the synapses in a neural network. There has been some work in using post CMOS technology as synapses to overcome this limitation, but systems to date have not been scalable due to the design of their neurons. This dissertation aims to design and build scalable neural network architectures that can use emerging resistive memory technology as synapses. Using analog computing techniques to build networks is promising, especially due to the development of dense, CMOS compatible analog resistive memories. Building functional analog networks in advanced technology nodes, however, is challenging due to the relatively poor performance of analog components in these nodes. This work explores oscillatory neural networks (ONNs), which use phase as the analog state variable instead of voltage or current, reducing the number of traditional analog components required and making the networks better-suited for advanced nodes. This thesis develops additional ONN theory with regard to hardware networks, since previous work did not consider the effect of transmission delay on network dynamics. Transmission delay is proven to cause desynchronization in unmodified ONNs, and the theoretical analysis suggests ways to build networks which do synchronize. Conclusions from the theoretical development are used to build a PLL-based ONN in hardware. The PLL-based ONN is more energy efficient than comparable systems implemented in digital CMOS, although the neuron area is somewhat larger. The measurement of the PLL-based ONN also reveals additional poorly-studied facets of ONN dynamics. Using the knowledge gained from the PLL-based ONN, a larger, PLL-free ONN is built in the same technology. Removing the PLL in each neuron reduces the power and area consumption without sacrificing any functionality.This dissertation demonstrates that ONNs are well-suited to take advantage of emerging resistive memory technology to build efficient hardware neural networks.

Thesis: M.S., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 1976 / Includes bibliographical references. / M.S. / M.S. Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science

Phase Synthesis is a fundamental operation in Smart Antennas and other Phased Array systems based on beamforming. There are increasing commercial applications for Integrated Phased Arrays due to their low cost, size and power and also because the RF and digital signal processing can be performed on the same chip. These low cost beamforming applications have augmented interest in Coupled Phase Locked Loop (CPLL) systems for Phase Synthesis. Previous work on the implementation of Phase Synthesis systems using Coupled PLLs for low cost beamforming had the constraint of a limited phase range of ±90°. The idea behind the thesis is that this phase synthesis range can be increased to ±180° through the use of PLLs employing Phase Frequency Detectors(PFDs), which is a significant improvement over conventional coupled-PLL systems. This work presents the detailed design and measurement results for a phase synthesizer using Coupled PLLs for achieving phase shift in the range of ±180°. Several Coupled PLL architectures are investigated and their advantages and limitations are evaluated in terms of frequency controllability, phase difference synthesis control and phase noise of the systems. A two-PLL system implementation using off the shelf components is presented, which generates a steady-state phase difference in the range ±180° using an adjustable DC control current. This is the proof of concept for doing an IC design for a Coupled Phase Locked Loop system. Commercial applications in the Wireless Medical Telemetry Service (WMTS) band motivate the design of a CPLL system in the 608-614 MHz band. The design methodology is presented which shows the flowchart of the IC design process from the system design specifications to the transistor level design. MATLAB simulations are presented to model the system performance quickly. VerilogA modeling of the CPLL system is performed followed by the IC design of the system and each block is simulated under different process and temperature corners. The transistor level design is then evaluated for its performance in terms of phase difference synthesis and phase noise and compared with the initial MATLAB analysis and improved iteratively. The CPLL system is implemented in IBM 130nm CMOS process and consumes 40mW of power from a 1.2V supply with a phase noise performance of -88 dBc/Hz for 177° phase generation.

No description available.

Within recent years, interest in the installation of solar-based, wind-based, and various other renewable Distributed Energy Resources (DERs) and Energy Storage (ES) systems has risen; in part due to rising energy costs, demand for cleaner power generation, increased power quality demands, and the need for additional protection against brownouts and blackouts. A viable solution for these requirements consists of installation of small-scale DER and ES systems at the single-phase (1Φ) distribution level to provide ancillary services such as peak load shaving, Static-VAr Compensation (STATCOM), ES, and Uninterruptable Power Supply (UPS) capabilities through the creation of microgrid systems. To interconnect DER and ES systems, power electronic converters are needed with not only control systems that operate in multiple modes of operation, but with islanding detection and resynchronization capabilities for isolation from and reclosure to the grid. The proposed system includes control architecture capable of operating in multiple modes, and with the ability to smoothly transfer between modes. Phase-Locked Loops (PLLs), islanding detection schemes, and resynchronization protocols are developed to support the control functionality proposed. Stationary frame PLL developments proposed in this work improve upon existing methods by eliminating steady-state noise/ripple without using Low-Pass Filters (LPFs), increasing frequency/phase tracking speeds for a wide range of disturbances, and retaining robustness for weakly interconnected systems. An islanding detection scheme for the stationary frame control is achieved through the stability of the PLL system interaction with the converter control. The proposed detection method relies upon the conditional stability of the PLL controller which is sensitive to grid-disconnections. This method is advantageous over other methods of active islanding detection mainly due to the need for those methods to perturb the output to test for islanding conditions. The PLL stability method does not inject signal perturbations into the output of the converter, but instead is designed to be stable while grid-connected, but inherently unstable for grid-disconnections. Resynchronization and reclosure to the grid is an important control aspect for microgrid systems that have the ability to operate in stand-alone, backup modes while disconnected from the grid. The resynchronization method proposed utilizes a dual PLL tracking system which minimizes voltage transients during the resynchronization process; while a logic-based reclosure algorithm ensures minimal magnitude, frequency, and phase mismatches between the grid and an isolated microgrid system to prevent inrush currents between the grid and stand-alone microgrid system. / Ph. D.

Networked wireless sensor systems have the potential to play a major role in critical applications including: environmental monitoring of chemical/biological attacks; condition-based maintenance of vehicles, ships and aircraft; real-time monitoring of civil infrastructure including roads, bridges etc.; security and surveillance for homeland defense systems; and battlefield surveillance and monitoring. Such wireless sensor networks can provide remote monitoring and control of operations of large-scale systems using low-power, low-cost, "throw-away" sensor nodes. This thesis focuses on two aspects of wireless sensor node development: (1) post-IC assembly of nanosensor devices onto prefabricated complementary-metal-oxide-semiconductor (CMOS) integrated circuits using a technique called dielectrophoretic (DEP) assembly; and (2) design of a low-power SiGe BiCMOS multi-band ultra-wideband (UWB) transmitter for wireless communications with other nodes and/or a central control unit in a wireless sensor network. For the first part of this work, a DEP assembly test chip was designed and fabricated using the five-metal core CMOS platform technology of Motorola's HiP6W low-voltage 0.18_m Si/SiGe BiCMOS process. The CMOS chip size was 2.5mm x 2.5 mm. The required AC signal for assembling nanowires is provided to the bottom electrodes defined in the Metal 4 (M4) layer of the IC process. This signal is then capacitively coupled to the top/assembly electrodes defined in the top metal (M5) layer that is also interconnected to appropriate readout circuitry. The placement and alignment of the nanowires on the top electrodes are defined by dielectrophoretic forces that act on the nanowires. For proof of concept purposes, metallic rhodium nanowires ((length = 5μm and diameter = 250 nm) were used in this thesis to demonstrate assembly onto the prefabricated CMOS chip. The rhodium nanowires were manufactured using a nanotemplated electroplating technique. In general, the DEP assembly technique can be used to manipulate a wider range of nanoscale devices (nanowire sensors, nanotubes, etc.), allowing their individual assembly onto prefabricated CMOS chips and can be extended to integrate diverse functionalized nanosensors with sensor readout, data conversion and data communication functionalities in a single-chip environment. In addition, this technique provides a highly-manufacturable platform for the development of multifunctional wireless sensor nodes based on assembled nano-sensor devices. The resistances of the assembled nanowires were measured to be on the order of 110 Ω consistent with prior prototype results. Several issues involved in achieving successful assembly of nanowires and good electrical continuity between the nanowires and metal layers of IC processes are addressed in this thesis. The importance of chemical/mechanical planarization (CMP) technique in modern IC processes and considerations for electrical isolation of readout circuit from the assembly sites are discussed. For the second part of this work, a multi-band hopping ultrawideband transmitter was designed to operate in three different frequency bands namely, 4.8 GHz, 6.4 GHz and 8.0 GHz. As a part of this effort, this thesis includes the design of a CMOS phase/frequency detector (PFD), a CMOS pseudo-random code generator and an on-chip passive loop filter, which were designed for the multi-band PLL frequency synthesizer. The CMOS PFD provided phase tracking over a range of -2π to +2π radians. The on-chip passive loop filter was designed for a 62_ phase margin, 250 μA-charge pump output current and 4 MHz-PLL loop-bandwidth. The CMOS pseudorandom code generator provided a two-bit output that helped switch the frequency bands of the UWB transmitter. With all these components, along with a BiCMOS VCO, a CMOS charge pump and a CMOS frequency divider, the simulated PLL frequency synthesizer locked within a relatively short time of 700ns in all three design frequency bands. The die area for the multi-band UWB transmitter as laid out was 1.5 mm x 1.0 mm. Future work proposed by this thesis includes sequential assembly of diverse functionalized gas/chemical nanosensor elements into arrays in order to realize highly sensitive "electronic noses". With integration of such diverse functionalized nano-scale sensors with low-power read-out and data communication system, a versatile and commercially viable low-power wireless sensor system can be realized. / Master of Science

Continuous Phase Frequency Shift Keying (CPFSK) is a constant amplitude modulation of growing popularity in low earth orbit satellites (LEOSAT) because of its spectral efficiency. This thesis compares the error rate performance of CPFSK demodulation using quadrature detectors and phase-locked loops under varying carrier to noise ratios and simulated Doppler shifts, as might be expected for a low earth orbit satellite downlink. Experimental comparison between a quadrature detector and a phase-locked loop demodulator shows that phase-locked loop demodulators and quadrature detectors offer equivalent performance as demodulators at low carrier to noise ratios for narrowband FM/CPFSK systems. This contrasts with earlier work that shows that phase-locked loops can provide threshold extension for wideband FM systems. / M.S.