Thesis (Ph. D.)--University of Texas at Austin, 2005. / Vita. Includes bibliographical references.

Thesis (Ph. D.)--University of Texas at Austin, 2005. / Vita. Includes bibliographical references.

Thesis (M.E.)--University of Canterbury, 2006. / Typescript (photocopy). "November 2006." Includes bibliographical references (leaves 121-124). Also available via the World Wide Web.

No description available.

This thesis describes the design, implementation and testing of a UHF frequency synthesizer. The synthesizer is designed to provide a sine wave output programmable from 400 MHz to 500 MHz in 0.1 MHz increments. The synthesis technique utilized is Digital Coherent Indirect Synthesis. This technique uses phase locking to provide a range of stable output frequencies all derived from a single crystal reference. Component design and system level analysis are presented in detail.

The recent trend in the RF and microwave industry has been a move towards increasing the number of components realized on one radio frequency integrated circuit (RFIC) (or microwave integrated circuit (MIC)). This trend has resulted in complex RFICs which often require reactive as well as other circuit components to be supplied in the form of an external circuit. Because the manufacturer's suggested circuit is often developed with a specific application in mind, the same circuit may not satisfy the demands of another application. Provided the necessary functionality and connections are possible, the external circuit may be altered such that the requirements of the other application can be met, thus extending the flexibility of the RFIC. The work presented here is focused on investigating modifications to RF Microdevices' suggested external circuit for the RF29X5 family of low cost, half duplex, FM/AM/ASK/FSK RFIC transceivers originally intended for operation in the 433, 868, or 902-928 MHz industrial, scientific, and measurement (ISM) bands. Examinations of the operating principles of the transceiver components were performed which facilitated the identification of suitable modifications. Among the modifications identified were implementation of a phase locked detector, various methods for extending the FSK data rate limitations of the transmitter, improving the phase noise of the VCO, and the implementation of a fractional-N synthesizer using the RF2905 internal phase-locked loop (PLL) components and external inexpensive logic circuits. In addition to these modifications to the external circuit, the investigation of the oscillators of the RF2905 resulted in a potentially improved implementation of the VCO by modifying the internal active circuitry as well. / Master of Engineering

Thesis (MScEng (Electrical and Electronic Engineering))--Stellenbosch University, 2008. / This thesis discusses the design, development and measured results of a phase-locked loop based frequency synthesiser for X-band Doppler radar. The objective is to obtain phase noise comparable or lower than that typically achieved with direct analogue frequency synthesis techniques. To meet this objective, a theoretical study of the noise contributions of individual components of the synthesiser and their effect on the total phase noise within and outside the loop bandwidth of the PLL is performed. The effect of different phase margins on the closed-loop frequency response of the PLL, and hence the total phase noise, is investigated. Based on the results, an optimal phase-frequency detector reference frequency, loop bandwidth, adequate phase margin, and suitable components are chosen for optimal phase noise performance. The total phase noise at the output of the synthesiser is calculated and it is shown that the phase noise specification can be met. A significant part of this thesis is devoted to the design, modelling and characterisation of a frequency multiplier, as well as to a combline and interdigital bandpass filter required for the frequency synthesiser. In the first case, a piecewise linear circuit model is used to model the behaviour of the nonlinear multiplier circuit. Fourier theory is used to calculate the large-signal driving point input and output impedances of the nonlinear circuit, enabling the computation of the circuit elements for the input and output matching networks. The measured response of the frequency multiplier under various different operating conditions is presented and discussed. The design of the microwave bandpass filters is based on the theory of coupling and external quality factors. To aid in the verification and optimisation of the design, a software simulation tool is used. The presented S-parameter measurements of the filters show how well the theory matches with what is obtained in practice. The measured spectral and phase noise response of various components comprising the synthesiser, are discussed. These measurements provide insight into the response of individual components under different operating conditions and show the behaviour of important subsystems of the synthesiser. The thesis culminates in the presentation of the measured phase noise of the complete synthesiser. It is shown how well the measured phase noise correlates with the calculated phase noise. In addition, the measured spectral content and transient behaviour of the synthesiser are investigated and discussed. High power spurious components at some output frequencies are indentified and reduced. The feasibility of using the developed prototype phase-locked loop based frequency synthesiser for coherent X-band Doppler radar is discussed and demonstrated.

Mixed-signal designs are becoming more and more complex every day. In order to adapt to the new market requirements, a formal process for design and verification of mixed signal systems i. e. top-down design and bottom-up verification methodology is required. This methodology has already been established for digital design. The goal of this research is to propose a new design methodology for mixed signal systems. In the first two chapters of this thesis, the need for a mixed signal design flow based on top-down design methodology will be discussed. The proposed design flow is based on behavioral modeling of the mixed signal system using one of the mixed signal behavioral modeling languages. These models can be used for design and verification through different steps of the design from system level modeling to final physical design. The other advantage of the proposed flow is analog and digital co-design. In the remaining chapters of this thesis, the proposed design flow was verified by designing an 800 MHz mixed signal PLL. The PLL uses a charge pump phase frequency detector, a single capacitor loop filter, and a feed forward error correction architecture using an active damping control circuit instead of passive resistor in loop filter. The design was done in 0. 18- <i>??</i> m CMOS process technology.

O presente trabalho propõe-se a oferecer respostas à questão de como a informação é preservada num sistema, focalizando-se na distinção entre os papéis desempenhados pelos constituintes elementares e pelos estruturais na preservação da memória desse sistema. Os sistema simulados circunscreveram-se a malhas, com diferentes graus de regularidade, compostas pelo acoplamento de osciladores não-lineares que apresentam comportamento coerente no estado de equilíbrio. Malhas de Sincronismo de Fase, também conhecidas por PLLs (Phase Locked Loops), foram adotadas como elementos constituintes básicos dos sistemas analisados. Para tanto, utilizou-se a plataforma de cálculo MATLAB-SIMULINK, acompanhando-se as evoluções dos diversos sistemas e de seus parâmetros dinâmicos associados, possibilitando o estabelecimento da correspondência entre os valores dos referidos parâmetros dinâmicos com parâmetros gráficos \"sensíveis\" à estrutura das malhas. Os resultados obtidos indicam a coexistência/cooperação das componentes estrutural e elementar na determinação dos valores dos parâmetros dinâmicos no estado de equilíbrio do sistema. No entanto, evidencia-se que tais componentes apresentam importâncias distintas na determinação dos diferentes parâmetros dinâmicos. / This work was conceived aiming to present some answers to how the information is preserved in a system. The focus was laid on the distinction between the tasks played by the elementary components and the structure of the system. The simulated systems were composed by coupled oscillators, more precisely by PLLs (Phase Locked Loops), arranged in networks of different regularities. Simulations were performed using Matlab-Simulink software to build a correlation between the final state dynamical parameters of the system and its degree of regularity. Results show the influence of both elementary and structural components on the system attained state. However the responses of characteristics parameters of the system to changes in the regularity of the structured network may greatly differ from one parameter to another. This behavior may suggest different strategies to preserve information of the system according to the information to be kept.

by C.Y. Ho. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1989. / Bibliography: leaves [147]-[148]