This diploma thesis deals with the implementation of standard IEEE 802.11ah into network simulator NS-3. The first part of the diploma thesis describes M2M communication for which the standard IEEE 802.11ah would be suitable. M2M communication is being more and more used in the society, that is why there is an effort to develop a new standard for this type of communication. The thesis contains a description of this standard based on technical specifications brought out by the Task Group ah (TGah). Some changes have been made in NS-3 for the purpose of this thesis in order to support this standard. In the next part there is a created scenario with basic topology in NS-3 with usage of standard IEEE 802.11ah, in which the functionality of the standard is tested. The result of this diploma thesis is a description of the changes which have been made and analysis of the output files from the simulation.

Dizertační práce se zabývá zpracováním signálu fyzických řídicích kanálů systému LTE a vyšetřováním bitové chybovosti při přenosu řídicí informace z vysílače do přijímače v závislosti na podmínkách příjmu. Práce je rozdělena do dvou hlavních částí. První část práce je zaměřena na simulaci přenosu řídicí informace LTE v základním pásmu. Jsou zde prezentovány vytvořené simulátory řídicích kanálů ve směru uplink i downlink. Simulace jsou provedeny pro všechny druhy nastavení systému a základní modely přenosového prostředí. Jsou zde popsány výsledky vlivu použití MIMO technologií na kvalitu příjmu řídicí informace především v únikových kanálech. Druhá část práce je zaměřena na možnost nasazení systému LTE ve sdíleném pásmu ISM (2.4 GHz). Jsou zde představeny základní koncepce použití, na jejichž základě je vytvořen scénář simulací. Kapitola dále popisuje tvorbu simulátoru koexistence LTE a systému Wi-Fi v přeneseném pásmu ISM 2.4GHz. Jsou zde uvedeny výsledky simulací koexistence LTE a rušivého systému Wi-Fi provedených dle vytvořeného scénáře. Výsledky simulací koexistence LTE a Wi-Fi jsou ověřeny měřením v laboratorních podmínkách. Toto porovnání je důležité z hlediska optimalizace simulátoru koexistence. Dle výsledků obou typů simulací a měření jsou stanovena provozní doporučení, která mají přispět k bezpečnému a spolehlivému vysílání a příjmu řídicích informací LTE i při nepříznivých podmínkách příjmu.

Bluetooth Low Energy (BLE) is a widely used low-energy version of Bluetooth’swireless protocol. To meet increasing requirements of modern wireless audio devices,Bluetooth LE Audio was released with its new Low Complexity CommunicationsCodec (LC3) being much more data efficient than its predecessor Low Complexity SubBand Coding. Because of its increased data efficiency, LC3 opens the door of exploring usage ofvarious physical layer configurations, especially those with lower data rates. Thedifference in performance when streaming audio with the uncoded LE 2M and 1Mconfigurations, compared to using the LE coded S=2 and S=8 configurations (whichhave a lower throughput) points to a research gap which this thesis aims to fill. To be able to gather data necessary to fill the identified gap, multiple iterations of bothsoftware and hardware artefacts were made. The produced artefacts were designed torun the same Bluetooth version (LE Audio) and switch between the physical layerconfigurations. Throughput and current consumption in varied ranges was measuredthrough usage of the artefacts. The results from the experiments show that for energy optimization, an adaptive schemewould not be beneficial over only using LE 2M. However, an adaptive scheme for thephysical layer can be used for LE Audio to improve range and stability. This doeshowever, come with the cost of increased energy consumption.

The reconfigurable aperture (RECAP) is a reconfigurable antenna consisting of a dense array of electronically controlled elements, which can be manipulated to support many antenna functions within a single architecture. RECAPs are explored herein as an enabling technology for future software defined and cognitive radio architectures, as well as compact wireless devices supporting many bands and services. First, the concept of a parasitic RECAP is developed and analyzed for various communication applications. This begins with the analysis of existing RECAP topologies (e.g. planar and parasitic) using a hybrid method combining full wave simulations and network analysis. Next, a performance versus complexity analysis is performed to assess the use of a parasitic RECAP for the most critical communications functions: pattern synthesis, MIMO communications and physical-layer wireless security. To verify simulation results, a prototype parasitic RECAP is also built and deployed in real propagation environments. Given the potential of adaptive and reconfigurable architectures for providing enhanced security, an idealized reconfigurable antenna is analyzed, resulting in the concept of secure array synthesis. The objective is to find optimal array beamforming for secure communication in the presence of a passive eavesdropper in a static line-of-sight (LOS) channel. The method is then extended to the case of multipath propagation environments. The problem is solved by casting it into the form of a semi-definite program, which can be solved with convex optimization. The method is general and can be applied to an arbitrary array topology with or without antenna mutual-coupling. Due to complexity of the problem, initial attention has been restricted to idealized reconfigurable antennas (smart antennas), where excitation amplitude and phase at each element can be controlled independently. Lastly, reconfigurable antennas are investigated as a solution to support the emerging application of over-the-air (OTA) testing in a low-cost and compact way, resulting in the concept of the reconfigurable over-the-air chamber (ROTAC). First, an idealized two-dimensional ROTAC is analyzed, revealing that the fading distribution, spatial correlation, frequency selectivity, and multipath angular spectrum can be controlled by proper specification of the random loads. Later, a prototype of ROTAC is built to study the fading statistics and angular characteristics of the multipath fields inside a practical chamber.

Non-orthogonal multiple access (NOMA), with its exceptional spectrum efficiency, was thought to be a promising technology for upcoming wireless communications. Physical layer security has also been investigated to improve the security performance of the system. Power-domain NOMA has been considered for this paper, where multiple users can share the same spectrum which bases this sharing on distinct power values. Power allocation is used to allocate different power to the users based on their channel condition. Data signals of different users are superimposed on the transmitter's side, and the receiver uses successive interference cancellation (SIC) to remove the unwanted signals before decoding its own signal. There exist an eavesdropper whose motive is to eavesdrop on the confidential information that is being shared with the users. The network model developed in this way consists of two links, one of which considers the relay transmission path from the source to Near User to Far User and the other of which takes into account the direct transmission path from the source to the destination, both of which experience Nakagami-m fading. To degrade the eavesdropper's channel, the jamming technique is used against the eavesdropper where users are assumed to be in a full-duplex mode which aims to improve the security of the physical layer. Secrecy performance metrics such as secrecy outage probability, secrecy capacity, etc. are evaluated and analyzed for the considered system. Mathematical analysis and simulation using MATLAB are done to assess, analyze and visualize the system's performance in the presence of an eavesdropper when the jamming technique is applied. According to simulation results, the active jamming approach enhances the secrecy performance of the entire system and leads to a positive improvement in the secrecy rate.

This thesis explores the practical application of Physical Layer Security (PLS) inMultiple-Input Multiple-Output (MIMO) systems, particularly focusing on ShortPacket Communication (SPC). The aim is to enhance the security of wireless com-munications against eavesdropping threats. By employing advanced techniques suchas Maximum Ratio Transmission (MRT) and Maximum Ratio Combining (MRC),along with Beamforming, the study demonstrates how these methods can signifi-cantly strengthen the signal integrity in MIMO systems.In developing a comprehensive system model that integrates PLS into MIMO,the research provides a dual approach of evaluation. Rigorous theoretical analy-sis coupled with MATLAB simulations are utilized to validate the effectiveness ofthe proposed model. These methods not only underscore the feasibility of PLSin real-world applications but also highlight the potential improvements in wirelesscommunication security, offering a valuable contribution to the field.

Algorithm design methods for radio communications systems are poised to undergo a massive disruption over the next several years. Today, such algorithms are typically designed manually using compact analytic problem models. However, they are shifting increasingly to machine learning based methods using approximate models with high degrees of freedom, jointly optimized over multiple subsystems, and using real-world data to drive design which may have no simple compact probabilistic analytic form. Over the past five years, this change has already begun occurring at a rapid pace in several fields. Computer vision tasks led deep learning, demonstrating that low level features and entire end-to-end systems could be learned directly from complex imagery datasets, when a powerful collection of optimization methods, regularization methods, architecture strategies, and efficient implementations were used to train large models with high degrees of freedom. Within this work, we demonstrate that this same class of end-to-end deep neural network based learning can be adapted effectively for physical layer radio systems in order to optimize for sensing, estimation, and waveform synthesis systems to achieve state of the art levels of performance in numerous applications. First, we discuss the background and fundamental tools used, then discuss effective strategies and approaches to model design and optimization. Finally, we explore a series of applications across estimation, sensing, and waveform synthesis where we apply this approach to reformulate classical problems and illustrate the value and impact this approach can have on several key radio algorithm design problems. / Ph. D.

The ever-increasing demand for private and sensitive data transmission over wireless networks has made security a crucial concern in the current and future large-scale, dynamic, and heterogeneous wireless communication systems. To address this challenge, wireless researchers have tried hard to continuously analyze the jamming threats and come up with improved countermeausres. In this research, we have analyzed the jamming-vulnerabilities of the leading multi-carrier communication systems, Orthogonal Frequency Division Multiplexing (OFDM) and Single-Carrier Frequency Division Multiple Access (SC-FDMA). In order to lay the necessary theoretical groundwork, first we derived the analytical BER expressions for BPSK/QPSK and analytical upper and lower bounds for 16-QAM for OFDMA and SC-FDMA using Pilot Symbol Assisted Channel Estimation (PSACE) techniques in Rayleigh slow-fading channel that takes into account channel estimation error as well as pilot-jamming effect. From there we advanced to propose more novel attacks on the Cyclic Prefix (CP) of SC-FDMA. The associated countermeasures developed prove to be very effective to restore the system. We are first to consider the effect of frequency-selectivity and fading correlation of channel on the achievable rates of the legitimate system under pilot-spoofing attack. With respect to jamming mitigation techniques, our approaches are more focused on Anti-Jamming (AJ) techniques rather than Low Probability of Intercept (LPI) methods. The Channel State Information (CSI) of the two transceivers and the CSI between the jammer and the target play critical roles in ensuring the effectiveness of jamming and nulling attacks. Although current literature is rich with different channel estimation techniques between two legitimate transceivers, it does not have much to offer in the area of channel estimation from jammer's perspective. In this dissertation, we have proposed novel, computationally simple, deterministic, and optimal blind channel estimation techniques for PSK-OFDM as well as QAM-OFDM that estimate the jammer channel to the target precisely in high Signal-to-Noise (SNR) environment from a single OFDM symbol and thus perform well in mobile radio channel. We have also presented the feasibility analysis of estimating transceiver channel from jammer's perspective at the transmitter as well as receiver side of the underlying OFDM system. / Ph. D.

In dieser Arbeit wird eine genaue Zeitsynchronisation über kupferbasierte Ethernetsysteme sowie der Entwurf von Schaltungen für die Bitübertragungsschicht (Physical Layer, PHY) in solchen Ethernetsystemen untersucht. Dabei wird der Entwurf eines integrierten Schaltkreises für den Standard 100Base-TX vorgestellt. Dieser PHY-Chip ermöglicht die Datenübertragung mit einer Datenrate von 100 MBit/s über verdrillte Kupferkabel und stellt darüber hinaus eine genaue Uhr bereit, welche zwischen den verbundenen Netzknoten synchronisiert werden kann. Dieser Schaltkreis ist insbesondere für Industrieanwendungen gedacht, bei denen verschiedene Prozesse zeitlich synchronisiert werden müssen. Prinzipiell ist der PHY-Chip jedoch universell für verschiedenste Anwendungen zur Zeitsynchronisation einsetzbar. Um die Genauigkeit der Zeitsynchronisation gegenüber herkömmlichen Ansätzen zu steigern, werden verschiedene Techniken untersucht und in dem entworfenen Schaltkreis eingesetzt. So wird die Phase der Taktsignale in feinen Schritten eingestellt und auch gemessen, sodass die Auflösung der Zeitstempel erheblich verbessert wird. Zu diesem Zweck wird ein sogenannter Digital-To-Phase Converter (DPC) eingesetzt, der 256 verschiedene Taktphasen des 125 MHz Systemtaktes bereitstellt. Für die eigentliche Zeitsynchronisation wird ein Proportional-Integral-Regler verwendet. Basierend auf einer theoretischen Rauschanalyse wird eine Methode vorgestellt, mit der die Parameter dieses Reglers so dimensioniert werden können, dass der Zeitfehler im eingeschwungenen Zustand möglichst klein wird. Darüber hinaus werden weitere Störeinflüsse analysiert und es werden geeignete Maßnahmen entwickelt, um diese zu kompensieren. So wird eine adaptive Kompensation eines Eintonstörers sowie eine Kalibrierung zur automatischen Kompensation von Asymmetrien im Kabel vorgestellt. All diese Punkte helfen, eine hervorragende Genauigkeit der Zeitsynchronisation zu ermöglichen, was durch umfangreiche Messungen verifiziert wird. Insgesamt weist der gemessene Zeitfehler in einem Punkt-zu-Punkt-Szenario eine Standardabweichung von 64 ps und einen Mittelwert unterhalb von 100 ps auf. Dies stellt eine erhebliche Verbesserung gegenüber konventionellen Lösungen zur Zeitsynchronisation über kupferbasiertes Ethernet dar, mit denen Genauigkeiten im Nanosekundenbereich erreicht werden. Als zweites Ziel dieser Arbeit wird der PHY-Chip für eine möglichst niedrige Leistungsaufnahme optimiert. Um dies zu erreichen, werden insbesondere der Leitungstreiber im Sender und der Equalizer im Empfänger systematisch optimiert. So werden zwei verschiedene Topologien von Leitungstreibern untersucht und verglichen. Beide weisen eine Leistungsaufnahme von etwa 24 mW auf. Im Vergleich zum Stand der Technik sind dies die beiden niedrigsten Werte für Leitungstreiber für den Standard 100Base-TX. Der gesamte PHY-Chip, der in einer 180 nm Technologie implementiert wurde, weist durch die zahlreichen Optimierungen eine geringe Leistungsaufnahme von maximal 69 mW auf, was ebenfalls einen Rekordwert im Vergleich mit dem Stand der Technik darstellt (80 mW). Die einzelnen Schaltungen wurden sowohl simulativ als auch mit ausführlichen Messungen verifiziert. Für den gesamten Link wird eine Bitfehlerrate besser als 10⁻¹² bei verschiedenen Kabeln bis zu 120 m Länge erreicht.:Abbildungsverzeichnis Tabellenverzeichnis Abkürzungen Symbole 1 Einleitung 1.1 Zeit und Zeitsynchronisation 1.2 Ziele dieser Arbeit 1.3 Gliederung 2 Grundlagen 2.1 100Base-TX Ethernet-Standard 2.1.1 Schnittstelle zur MAC-Schicht 2.1.2 4B5B-Kodierung 2.1.3 Scrambler und Descrambler 2.1.4 MLT-3-Kodierung 2.1.5 Bitfehlerrate und Signal-Rausch-Verhältnis 2.2 Kanalmodellierung 2.2.1 Dämpfung 2.2.2 Baseline-Wander 2.3 Zeitsynchronisierung 2.3.1 Bestimmung der Zeitdifferenz 2.3.2 Vergrößerung der Synchronisationsgenauigkeit 3 Schaltungsentwurf und Charakterisierung 3.1 Energieeffiziente Leitungstreiber 3.1.1 Vergleich von Leitungstreibern mit passiver Anpassung 3.1.2 Spannungstreiber 3.1.3 Leitungstreiber mit aktiver Anpassung 3.1.4 Vergleich der Leitungstreiber und Fazit 3.2 Takterzeugung 3.2.1 Ringoszillator 3.2.2 Phasenregelschleife 3.2.3 Phaseninterpolator 3.2.4 Messung 3.2.5 Verbesserter 10 Bit DPC 3.3 Takt- und Datenrückgewinnung 3.3.1 Phasendetektor 3.3.2 Modellierung des DPC 3.3.3 Dimensionierung des Schleifenfilters 3.3.4 Implementierung 3.4 Adaptiver Equalizer 3.4.1 Kompensation der Kabeldämpfung 3.4.2 Implementierung des analogen Filters 3.4.3 Digitale Regelung der Equalizer-Parameter 3.4.4 Messung des Equalizers 3.5 Zeitsynchronisation 3.5.1 Uhr und Steuerung der Frequenz 3.5.2 Digitale Schaltungen zur Zeitstempelung 3.5.3 Implementierung der Zeitsynchronisation 3.5.4 Adaptive Unterdrückung eines Eintonstörers 3.5.5 Automatische Kalibrierung von Asymmetrien 3.5.6 Vergleich mit dem Stand der Technik 3.6 Gesamter PHY-Schaltkreis 3.6.1 Leistungsaufnahme 3.6.2 Vergleich mit dem Stand der Technik 4 Zusammenfassung und Ausblick Literaturverzeichnis Eigene Veröffentlichungen / This work investigates accurate time synchronization over copper-based Ethernet systems as well as the design of circuits for the physical layer (PHY) in such Ethernet systems. The design of an integrated circuit (IC) for the 100Base-TX standard is presented. This PHY-IC enables data transmission at a data rate of 100 MBit/s over twisted pair copper cables and, additionally, provides an accurate clock which can be synchronized between connected network nodes. This circuit is designed for industrial applications where various processes need to be synchronized in time. In principle, however, the PHY-IC can be used universally for various time synchronization applications. In order to increase the accuracy of the time synchronization compared to conventional approaches, various techniques are investigated and used in the designed circuit. For example, the phase of the clock signals is adjusted and measured in fine steps, such that the resolution of the timestamps is improved by a large amount. For this purpose, a digital-to-phase converter (DPC) is used, which provides 256 different clock phases of the 125 MHz system clock. A proportional integral controller is used for the actual time synchronization application. Based on a theoretical noise analysis, a method is presented to dimension the parameters of this controller to minimize the timing error in the steady state. Furthermore, other disturbing influences are analyzed and suitable measures are developed to compensate them. Thus, an adaptive compensation of a single-tone interferer is presented as well as a calibration to automatically compensate for asymmetries in the cable. All these points help to provide excellent accuracy of the time synchronization, which is verified by extensive measurements. Overall, the measured time error in a point-to-point scenario has a standard deviation of 64 ps and a mean value below 100 ps. This represents a significant improvement over conventional solutions for time synchronization over copper-based Ethernet, which achieve accuracies in the nanosecond range. As a second goal of this work, the PHY-IC is optimized for lowest power consumption. In particular, the line driver in the transmitter and the equalizer in the receiver are systematically optimized to achieve this. Thus, two different topologies of line drivers are investigated and compared. Both have a power consumption of about 24 mW. These represent the two lowest values for line drivers for the 100Base-TX standard compared to the state of the art. The entire PHY-IC is implemented in a 180 nm technology and shows a power consumption below 69 mW due to the numerous optimizations. This also represents a record value compared to the state of the art (80 mW). The individual circuits were verified with simulations and with detailed measurements. For the entire link, a bit error rate better than 10⁻¹² is achieved for various cables up to 120 m length.:Abbildungsverzeichnis Tabellenverzeichnis Abkürzungen Symbole 1 Einleitung 1.1 Zeit und Zeitsynchronisation 1.2 Ziele dieser Arbeit 1.3 Gliederung 2 Grundlagen 2.1 100Base-TX Ethernet-Standard 2.1.1 Schnittstelle zur MAC-Schicht 2.1.2 4B5B-Kodierung 2.1.3 Scrambler und Descrambler 2.1.4 MLT-3-Kodierung 2.1.5 Bitfehlerrate und Signal-Rausch-Verhältnis 2.2 Kanalmodellierung 2.2.1 Dämpfung 2.2.2 Baseline-Wander 2.3 Zeitsynchronisierung 2.3.1 Bestimmung der Zeitdifferenz 2.3.2 Vergrößerung der Synchronisationsgenauigkeit 3 Schaltungsentwurf und Charakterisierung 3.1 Energieeffiziente Leitungstreiber 3.1.1 Vergleich von Leitungstreibern mit passiver Anpassung 3.1.2 Spannungstreiber 3.1.3 Leitungstreiber mit aktiver Anpassung 3.1.4 Vergleich der Leitungstreiber und Fazit 3.2 Takterzeugung 3.2.1 Ringoszillator 3.2.2 Phasenregelschleife 3.2.3 Phaseninterpolator 3.2.4 Messung 3.2.5 Verbesserter 10 Bit DPC 3.3 Takt- und Datenrückgewinnung 3.3.1 Phasendetektor 3.3.2 Modellierung des DPC 3.3.3 Dimensionierung des Schleifenfilters 3.3.4 Implementierung 3.4 Adaptiver Equalizer 3.4.1 Kompensation der Kabeldämpfung 3.4.2 Implementierung des analogen Filters 3.4.3 Digitale Regelung der Equalizer-Parameter 3.4.4 Messung des Equalizers 3.5 Zeitsynchronisation 3.5.1 Uhr und Steuerung der Frequenz 3.5.2 Digitale Schaltungen zur Zeitstempelung 3.5.3 Implementierung der Zeitsynchronisation 3.5.4 Adaptive Unterdrückung eines Eintonstörers 3.5.5 Automatische Kalibrierung von Asymmetrien 3.5.6 Vergleich mit dem Stand der Technik 3.6 Gesamter PHY-Schaltkreis 3.6.1 Leistungsaufnahme 3.6.2 Vergleich mit dem Stand der Technik 4 Zusammenfassung und Ausblick Literaturverzeichnis Eigene Veröffentlichungen

ITC/USA 2005 Conference Proceedings / The Forty-First Annual International Telemetering Conference and Technical Exhibition / October 24-27, 2005 / Riviera Hotel & Convention Center, Las Vegas, Nevada / This paper describes the Flexible Telemetry Transceiver (FNT)-a modular, scalable, standards-based, software configurable, microwave wireless telemetry network transceiver. The FNT enables flexible, high-rate, long-range, duplex, network services across multipoint to multipoint wireless channel.