Η εργασία αυτή ασχολείται με την υλοποίηση ενός μεταφραστή για το μοντέλο παράλληλου προγραμματισμού OpenMP. Το μοντέλο αυτό χρησιμοποιείται για την υλοποίηση παράλληλων εφαρμογών για την αρχιτεκτονική κοινής μνήμης, και δίνει έμφαση στην ευκολία του προγραμματισμού και την μεταφερσιμότητα των παράλληλων εφαρμογών που αναπτύσσονται μ’ αυτό. Στην εργασία αυτή παρουσιάζεται η σχεδίαση και η υλοποίηση ενός μεταγλωττιστή παράλληλων εφαρμογών OpenMP για τη γλώσσα προγραμματισμού C σύμφωνα με την έκδοση 2.0 του προτύπου OpenMP. Ο μεταγλωττιστής που υλοποιήθηκε ανήκει στην κατηγορία των μεταφραστών, δηλαδή μεταφράζει τον πηγαίο κώδικα σε γλώσσα προγραμματισμού C με τις επεκτάσεις OpenMP, σε ισοδύναμο πηγαίο κώδικα σε γλώσσα προγραμματισμού C, στον οποίο οι επεκτάσεις OpenMP έχουν αντικατασταθεί από ισοδύναμα τμήματα κώδικα τα οποία χρησιμοποιούν κλήσεις βιβλιοθήκης νημάτων για την υλοποίηση του παραλληλισμού. Ο μεταφραστής έχει σχεδιαστεί με τέτοιο τρόπο ώστε να είναι μεταφέρσιμος, υποστηρίζοντας πολλαπλές πλατφόρμες εκτέλεσης, και επεκτάσιμος, υποστηρίζοντας πολλαπλές βιβλιοθήκες νημάτων κατά τη μετάφραση των οδηγιών OpenMP. Η υλοποίηση του μεταφραστή έγινε στη γλώσσα προγραμματισμού Java, χρησιμοποιώντας το γλωσσικό εργαλείο ANTLR για την υλοποίηση του λεκτικού και συντακτικού αναλυτή. Ο μεταφραστής συνοδεύεται, επίσης, από μια βιβλιοθήκη χρόνου εκτέλεσης, η οποία περιέχει τις συναρτήσεις που ορίζονται από το πρότυπο OpenMP v2.0, καθώς και άλλες συναρτήσεις που είναι απαραίτητες για την εκτέλεση των μεταφρασμένων παράλληλων εφαρμογών. Επίσης, στη βιβλιοθήκη υλοποιούνται οι πολιτικές χρονοδρομολόγησης, επιτρέπωντας εύκολα την υλοποίηση κάποιας νέας πολιτικής. Η βιβλιοθήκη έχει υλοποιηθεί σε γλώσσα προγραμματισμού C. Στα πλαίσια της εργασίας αυτής, έχει υλοποιηθεί η υποστήριξη των βιβλιοθηκών νημάτων POSIX και NANOS σε πολυεπεξεργαστικά συστήματα κοινής μνήμης, καθώς και οι πολιτικές χρονοδρομολόγησης που ορίζονται στο πρότυπο OpenMP v2.0. / The subject of this thesis is the implementation of a translator for the OpenMP parallel programming model. This model is used for the development of parallel applications for the shared memory model and emphasizes on the ease of programming and the portability of the applications developed with it. This thesis describes the design and the implementatino of a compiler for OpenMP parallel applications for the C programming language according to version 2.0 of the OpenMP model. The compiler that has been implemented belongs to the translator class, that is translates the source code in C programming language with the OpenMP extensions to equivalent source code in C programming language where the OpenMP extensions have been replaced with equivalent code segments which use thread library calls to implement the parallelism. The translator has been designed in order to be portable, supporting multiple execution platforms, and extensible, supporting multiple thread libraries during the translation of the OpenMP directives. The translator has been implemented using the Java language and using the language tool ANTLR for the implementation of the lexer and the parser. The translator comes with a run-time library, which contains all of the functions which are defined by the OpenMP v2.0, as well as other functions which are needed for the execution of the translated parallel applications. Also, the library contains the scheduling policies allowing easy implementation of a new one. The library has been implemented using the C language. The current implementation supports the POSIX and NANOS thread libraries in shared memory SMPs, as well as all the scheduling policies defined in OpenMP v2.0

There are several timing mechanisms on presently available commercial operating systems. Two operating system platforms that immediately come to mind are the Microsoft Windows environment (the WIN32 platform) and its UNIX-based counterpart, Linux (with its POSIX standard). The timing mechanisms under these operating systems are adequate for use in conventional multimedia applications currently run on these platforms. However, the requirements of such applications are not as stringent within a real-time environment. The goal of this dissertation was to determine if it would be possible to find a workaround for applications where current timing mechanisms in the WIN32 and POSIX environments do not meet the requirements of real-time. Before a proposed workaround is presented, a clarification is given as to what is meant by the notion of a timer. Attention is also given to the fact that its accuracy is quantified in terms of its resolution. It is acknowledged that real-time extensions to both the Windows and Linux operating systems exist. However, it was decided to find a solution without such assistance. Real-time is also defined and sub-classified into hard- and soft real-time, differentiating environments that have precise constraints (hard real-time) on timing as opposed to environments where demands on accuracy and efficiency are less stringent (soft real-time). The timer that was ultimately implemented had to conform to the latter form of real-time. This dissertation therefore aims to provide a solution in a soft real-time environment. The current timing mechanisms are discussed and their performance is quantified. Their deficiency in measuring a reliable periodic interval of 1 ms is highlighted. From this qualification of timers stems the requirements for the soft real-timer timer. The areas in which improvement is sought are stated. The design and implementation of a soft real-time timer that meets these requirements is presented and its performance at various frequencies is quantified. A comparison is given between the timer and the existing timing mechanisms as well as comparison between its implementation under both Windows and Linux. Additionally, the viability of the proposed timer compared to a proven hard real-time timer is presented. Finally it is recognised that a timer would not be useful if it was not effective in a practical environment. Consequently, the timer’s performance under the same load that it would experience in a practical soft real-time environment is investigated as well. The dissertation concludes with a discussion on the compatibility of this timer with expected advances in future Central Processing Unit (CPU) technologies. / Dissertation (MSc (Computer Science))--University of Pretoria, 2007. / Computer Science / MSc / unrestricted

Electronic design automation (EDA) tools play a central role in bridging the productivity gap for designing complex hardware systems. However, with an increase in the size and complexity of today's design requirements, current methodologies and EDA tools are unable to effectively mitigate the further widening of productivity gap. It is estimated that testing and verification takes 2/3rd of the total development time of complex hardware systems. Functional simulation forms the main stay of testing and verification process and is the most widely used technique for testing and verification. Most of the simulation algorithms and their implementations are designed for uniprocessor systems that cannot easily leverage the parallelism in multi-core and GPU platforms. For example, logic simulation often uses levelized sequential algorithms, whereas the discrete-event simulation frameworks for Verilog, VHDL and SystemC employ concurrency in the form of multi-threading to given an illusion of the inherent parallelism present in circuits. However, the discrete-event model of computation requires a global notion of an event-queue, which makes improving its simulation performance via parallelization even more challenging. This work investigates automatic parallelization of simulation algorithms used to simulate hardware models. In particular, we focus on parallelizing the simulation of hardware designs described at the RTL using SystemC/HDL with examples to clearly describe the parallelization. Even though multi-cores and GPUs other parallelism, efficiently exploiting this parallelism with their programming models is not straightforward. To overcome this, we also focus our research on building intelligent translators to map simulation applications onto multi-cores and GPUs such that the complexity of the low-level programming models is hidden from the designers. / Master of Science

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / Safety critical systems are systems where its failures can cause irreparable damage for this reason the development of safety critical systems involves safety issues and require rigorous validation in the certification process. Certification processes are expensive and lengthy to follow laws and rigorous rules. With the continuous evolution provided by general purpose programming languages, ease of learning, and the use of these languages in industry and academy, researches have been performed aiming to adapt general purpose programming languages for use in safety-critical applications. The purpose of these adaptations is to reduce the scope of commands found in general purpose languages in order to develop safety critical systems, for example, to avoid or reduce the use of recursions. Some examples of these adaptations include the Real Time Specification for Java (RTSJ), developed in 1998 and Safety Critical Java. SCJ uses objects and concepts defined by the RTSJ focusing on the development of safetycritical applications. In SCJ, the concept of missions is deployed where each mission consists of schedulable objects defined by the RTSJ. The portability of a Java application is one of the main factors for choosing this language. However, there is great difficulty in finding virtual machines for embedded safety-critical systems, therefore it is difficult to benefit from the portability provided by the Java virtual machine in this context. Nevertheless, an application developed in the C++ programming language can be executed directly on the device without using a virtual machine. This work presents a translation of the Safety Critical Java to the C++ programming language, maintaining the behaviour of objects that implement the concept of missions for SCJ in C++. This enables the execution of safety-critical applications in embedded devices without the use of a virtual machine. / Sistemas críticos são sistemas em que suas falhas podem causar danos irreparáveis como colocar a vida de pessoas em risco e por este motivo envolve questões de segurança e exige uma validação rigorosa no processo de certificação. Processos de certificação são caros e demorados que seguem leis e regras rigorosas. Com a evolução contínua proporcionada por linguagens de programação de propósito geral, a facilidade de aprendizado, assim como a utilização destas linguagens na indústria e acadêmia, pesquisas vem sendo realizadas com o intuito de adaptar linguagens de programação de propósito gerais para serem utilizadas em aplicações críticas de tempo real. O objetivo destas adaptações é de tornar o escopo de comandos das linguagens para desenvolvimento de sistemas críticos mais restritos, como por exemplo, ao evitar ou reduzir a utilização de recursões. Alguns exemplos dessas adaptações são a Especificação de Tempo Real Java (Real Time Specification for Java - RTSJ) desenvolvida no ano de 1998, e a Safety Critical Java (SCJ) que utiliza objetos e conceitos definidos pela RTSJ com enfoque no desenvolvimento de aplicações para sistemas críticos. Na SCJ foi implementado o conceito de missões onde cada missão é composto por objetos escalonáveis definidos pela RTSJ. A portabilidade de uma aplicação desenvolvida em Java é um dos principais fatores dos quais desenvolvedores desejam utilizá-la. Todavia, existe uma grande dificuldade de encontrar máquinas virtuais para sistemas críticos embarcados, dificultando a portabilidade da qual a linguagem Java fornece. Por outro lado, uma aplicação desenvolvida na linguagem de programação C++ pode ser executada diretamente no dispositivo sem a necessidade de utilizar uma máquina virtual. Por este motivo, nesta dissertação é apresentada uma tradução da especificação Safety Critical Java na linguagem de programação C++, com o objetivo de manter o comportamentos de uma aplicação desenvolvida em SCJ e assim possibilitando a execução de uma aplicação com requisitos temporais em diversos dispositivos embarcados.

This thesis deals with different parallelizations of training procedure for artificial neural networks. The networks are trained as phoneme-state acoustic descriptors for speech recognition. Two effective parallelization strategies were implemented and compared. The first strategy is data parallelization, where the training is split into several POSIX threads. The second strategy is node parallelization, which uses CUDA framework for general purpose computing on modern graphic cards. The first strategy showed a 4x speed-up, while using the second strategy we observed nearly 10x speed-up. The Stochastic Gradient Descent algorithm with error backpropagation was used for the training. After a short introduction, the second chapter of this thesis shows the motivation and introduces the neural networks into the context of speech recognition. The third chapter is theoretical, the anatomy of a neural network and the used training method are discussed. The following chapters are focused on the design and implementation of the project, while the phases of the iterative development are described. The last extensive chapter describes the setup of the testing system and reports the experimental results. Finally, the obtained results are concluded and the possible extensions of the project are proposed.

Field-Programmable Gate Arrays (FPGAs) systems now comprise many processing elements that are processors running software and hardware engines used to accelerate specific functions. To make the programming of such a system simpler, it is easiest to think of a shared-memory environment, much like in current multi-core processor systems. This thesis introduces a novel, shared-memory, cache-coherent infrastructure for heterogeneous systems implemented on FPGAs that can then form the basis of a shared-memory programming model for heterogeneous systems. With simulation results, it is shown that the cache-coherent infrastructure outperforms the infrastructure of Woods [1] with a speedup of 1.10. The thesis explores the various configurations of the cache interconnection network and the benefit of the cache-to-cache cache line data transfer with its impact on main memory access. Finally, the thesis shows the cache-coherent infrastructure has very little overhead when using its cache coherence implementation.

Field-Programmable Gate Arrays (FPGAs) systems now comprise many processing elements that are processors running software and hardware engines used to accelerate specific functions. To make the programming of such a system simpler, it is easiest to think of a shared-memory environment, much like in current multi-core processor systems. This thesis introduces a novel, shared-memory, cache-coherent infrastructure for heterogeneous systems implemented on FPGAs that can then form the basis of a shared-memory programming model for heterogeneous systems. With simulation results, it is shown that the cache-coherent infrastructure outperforms the infrastructure of Woods [1] with a speedup of 1.10. The thesis explores the various configurations of the cache interconnection network and the benefit of the cache-to-cache cache line data transfer with its impact on main memory access. Finally, the thesis shows the cache-coherent infrastructure has very little overhead when using its cache coherence implementation.

Les systemes monopuce deviennent de plus en plus complexes, integrant composants a la fois logiciels et materiels dans le but de procurer une capacite de calcul croissante aux applications embarquees. L'interconnexion des composants devient un element crucial de la conception ; il fournit aux concepteursdes fonctionalites avancees telles qu'operations atomiques, transactions paralleles et primitives de communication permettant des systemes securises. Le concept de reseau sur puce s'impose comme element de communicationpour les architectures d'interconnexion des systemes de la prochaine generation. Le role des reseaux sur puce consiste a remplacer les bus partages dont la mise a l'echelle comporte de serieux problemes de conception et represente un goulot d'etranglement pour le systeme global. La modelisation d'un reseau sur puce est une tache extremement complexe ; ces modeles doivent etre a la fois rapides en terme d'execution, precis et il doivent exporter des interfaces standard an d'en ameliorer la reutilisation. Les principales contributions de cet ouvrage sont representees par : (1) le developpement d'un simulateur de reseaux sur puce complet, precis au cycle pres, base sur OCCN, un logiciel de simulation libre disponible sur sourceforge a l'adresse http://occn.sourceforge.net , (2) l'integration de plusieurs environnements de simulation heterogenes en plate-formes tres complexes utilisees pour etudier des systemes monopuce reels produits par STMicroelectronics et (3) une connaissance complete des concepts sous-jacents aux reseaux sur puce qui a apporte une contribution importante au developpement de STNoC., la nouvelle technologie d'interconnexion de STMicroelectronics developpee au sein du laboratoire Advanced System Technology (AST) de Grenoble. L'environnement de modelisation realise a ete utilise pour l'etude de deux systemes monopuce reels developpes par STMicroelectronics orientes vers la television numerique a tres haute denition (HDTV).

Después de más de 25 años de intensa investigación, la planificación de sistemas de tiempo-real ha mostrado una transición que va desde una infraestructura basada en ejecutivos cíclicos, a modelos de planificación más flexibles, tales como planificación basada en prioridades estáticas y dinámicas, planificación de tareas no críticas, y planificación con retroalimentación, por nombrar algunas. A pesar de lo anterior, actualmente tan sólo unas cuantas políticas de planificación están disponibles para la implementación de sistemas de tiempo-real. Por ejemplo, la mayoría de los sistemas operativos de tiempo-real existentes proporcionan únicamente planificación basada en prioridades fijas. Sin embargo, no todos los requerimientos de las aplicaciones de tiempo-real pueden ser satisfactoriamente atendidos utilizando exclusivamente planificación estática. Existen sistemas constituidos por tareas críticas y no críticas que son planificados de mejor manera utilizando planificación basada en prioridades dinámicas. Además, se ha demostrado que la planificación dinámica permite una mayor utilización de los recursos del sistema. En años recientes, algunos autores han publicado diferentes esquemas para integrar nuevas políticas de planificación a un sistema operativo. Algunos de ellos proponen que los nuevos servicios de planificación se implementen a nivel de usuario, evitando así que la estructura interna del sistema operativo tenga que ser modificada, y ofreciendo la oportunidad de implementar y probar muchos de los resultados generados por el trabajo de investigación en el área de planificación de sistemas de tiempo-real. De entre los trabajos relacionados publicados a la fecha, destaca el Modelo para la Planificación Definida por el Usuario, propuesto por Mario Aldea y Michael González-Harbour. El modelo presenta una Interfaz para Programas de Aplicación (API) que permite crear y utilizar planificadores a nivel de usuario de manera compatible con el modelo de planificación / Díaz Ramírez, A. (2006). Marco de referencia para la definición de planificadores a nivel de usuario en sistemas de tiempo-real [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/1934 / Palancia

The diploma thesis deals with design and development of the system which detects and numbers train carriages in compliance with International Union of Railways. Firstly, methods for correct detection of passing wheel including time records are analysed. Also, the summary of detection sensors used in railway industry is referred. I analyse meaning of each digit in numbering according to the UIC. The system solution is designed and the interaction and communication with other sub-systems is discussed. I put emphasis on the kind of solution that returns as accurate record as possible under any circumstances. The system operates in real time. Further, the results of measuring program are back-tested in order to verify low-deviation of measuring system component. The following section describes program prototype, which processes the recorded data. The algorithms which I used for the detection of wheel and train carriages are described. In the following chapter I discuss the usage of an external camera detecting the numbers in accordance to the UIC. In the last chapter, I describe the test environment in which the solution has been tested, and summarize the results of tests on a real life railway.