Post-silicon validation is an important step during the implementation flow of digital integrated circuits and systems. Most of the validation strategies are based on ad-hoc solutions, such as guidelines from best practices, decided on a case-by-case basis for a specific design and/or application domain. Developing systematic approaches for post-silicon validation can mitigate the productivity bottlenecks that have emerged due to both design diversification and shrinking implementation cycles. Ever since integrating on-chip memory blocks became affordable, embedded logic analysis has been used extensively for post-silicon validation. Deciding at design time which signals to be traceable at the post-silicon phase, has been posed as an algorithmic problem a decade ago. Most of the proposed solutions focus on how to restore as much data as possible within a software simulator in order to facilitate the analysis of functional bugs, assuming that there are no electrically-induced design errors, e.g., bit- flips. In this thesis, first it is shown that analyzing the logic inconsistencies from the post-silicon traces can aid with the detection of bit-flips and their root-cause analysis. Furthermore, when a bit-flip is detected, a list of suspect nets can be automatically generated. Since the rate of bit-flip detection as well the size of the list of suspects depends on the debug data that was acquired, it is necessary to select the trace signals consciously. Subsequently, new methods are presented to improve the bit-flip detectability through an algorithmic approach to selecting the on-chip trace signals. Hardware assertion checkers can also be integrated on-chip in order to detect events of interest, as defined by the user. For example, they can detect a violation of a design property that captures a relationship between internal signals that is supposed to hold indefinitely, so long as no bit-flips occur in the physical prototype. Consequently, information collected from hardware assertion checkers can also provide useful debug information during post-silicon validation. Based on this observation, the last contribution from this thesis presents a novel method to concurrently select a set of trace signals and a set of assertions to be integrated on-chip. / Thesis / Doctor of Philosophy (PhD)

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Optical shrink for process migration, manufacturing process variation and dynamic voltage control leads to clock skew as well as path delay variation in a manufactured chip. Since such variations are difficult to predict in pre-silicon phase, tunable clock buffers have been used in several microprocessor designs. The buffer delays are tuned to improve maximum operating clock frequency of a design. This however shifts the burden of finding tuning settings for individual clock buffers to the test process. In this project, we describe a process of using tester measurements to determine the settings of the tunable buffers for recovery of performance lost due to process variations. Then we study the impact of positioning of tunable buffers in the clock tree. In course of our study it was observed that the greatest benefit from tunable buffer placement can be derived, when the clock tree is synthesized with future tuning considerations. Accordingly, we present a clock tree synthesis procedure which offers very good mitigation against process variation, as borne out by the results. The results show that without any design intervention, an average improvement of 9% is achieved by our tuning system. However, when the clock tree is synthesized based on static timing information with tuning buffer placement considerations, much larger performance improvement is possible. In one example, performance improved by as much as 18%.

Submitted by PPG Ci?ncia da Computa??o (ppgcc@pucrs.br) on 2018-08-22T17:30:17Z No. of bitstreams: 1 GUILHERME HECK_TES.pdf: 7520580 bytes, checksum: 0abf48b5a455b7c50fa0b30109a1ee57 (MD5) / Approved for entry into archive by Sheila Dias (sheila.dias@pucrs.br) on 2018-08-23T12:09:32Z (GMT) No. of bitstreams: 1 GUILHERME HECK_TES.pdf: 7520580 bytes, checksum: 0abf48b5a455b7c50fa0b30109a1ee57 (MD5) / Made available in DSpace on 2018-08-23T13:31:43Z (GMT). No. of bitstreams: 1 GUILHERME HECK_TES.pdf: 7520580 bytes, checksum: 0abf48b5a455b7c50fa0b30109a1ee57 (MD5) Previous issue date: 2018-03-09 / A demanda sem precedentes por poderosos dispositivos de processamento gerou quebras consecutivas de paradigma de projeto de circuito na ?rea de Circuitos Integrados (CIs). O uso de tecnologia submicrom?trica profunda aumenta a densidade de integra??o a n?veis nunca vistos antes. No entanto, com CIs mais densos, a inclina??o do rel?gio e outros efeitos requerem compensa??es em design s?ncrono, o que pode aumentar a ?rea e o consumo de energia a valores inaceit?veis. Como alternativa, o paradigma ass?ncrono est? re-emergindo, focado na efici?ncia de energia. Entre os modelos cl?ssicos de projeto ass?ncrono, o Empacotamento-de-Dados (ED) se destaca pela sua capacidade de fornecer alto desempenho, reduzir a pot?ncia e obter resultados de ?rea semelhante ? dos modelos s?ncronos. Diferentemente dos modelos mais robustos de quase-atraso insens?vel, uma outra classe comum de modelos para implementar circuitos ass?ncronos, circuitos ED requerem o uso extensivo de Elementos de Atraso (EAs) para garantir a correta funcionalidade. No entanto, todos os circuitos s?o afetados por varia??es de Processo, Tens?o e Temperatura (PTT), incluindo a L?gica Combinacional (LC) em ED impondo margem em elementos de atraso. Al?m disso, projetos atuais usam escalonamento de tens?o para melhorar a efici?ncia de energia, o que afeta o atraso diferentemente em LCs e EAs adicionando mais margem em EAs. Um novo modelo baseado em ED chamado Blade usa o conceito de resili?ncia como uma esperan?a para evitar a margem de atraso causada por PTT e escalonamento de tens?o. Contudo, o uso de dois elementos de atraso ir? representar mais margens e mais tempo de teste no circuito final. Assim, este trabalho mostra uma an?lise do comportamento de elementos de atraso sob escalonamento de tens?o e o impacto em testes p?s-sil?cio. Ele introduz um novo termo para determinar o impacto da escala de tens?o sobre os elementos de atraso e tamb?m a compara??o entre os EAs mais utilizados em projetos ED usando esta nova m?trica. Uma an?lise de testes em modelos ED e Blade ? apresentada e o impacto da escala de tens?o nestes projetos ? analisado. Finalmente, um novo elemento de atraso ? proposto focando na redu??o de margem e redu??o no tempo de teste para o modelo Blade. / The unprecedented demand for powerful processing devices has generated consecutive circuit design paradigm breaks in the Integrated Circuits (ICs) arena. The use of deep submicron technology increases the integration density to levels never seen before. However, with denser ICs, clock skew and other effects require compensations in synchronous design, which can increase area overhead and power consumption to unacceptable values. As an alternative, the asynchronous paradigm is re-emerging, focused on power efficiency. Among classical asynchronous design templates, the Bundled-Data (BD) one stands off for its capability to provide high performance, reduce power and achieve area results similar to that of synchronous designs. Unlike the more robust Quasi-Delay Insensitive (QDI) templates, another common class of templates to implement asynchronous circuits, BD circuits require the extensive use of Delay Elements (DEs) to guarantee correct functionality. However, all circuits are affected by Process, Voltage and Temperature (PVT) variations, including the Combinational Logic (CL) on BD imposing margin on delay elements. In addition, current designs use voltage scaling to improve power efficiency, which impacts the delay differently in CLs and DEs adding more margin in DEs. A new template based on BD called Blade uses resiliency concept as a hope to avoid the delay margin caused by PVT and voltage scaling. Although, the use of two delay elements will represents more margins and extra test time on final circuit. So, this work shows an analysis of delay elements behavior under voltage scaling and the impact on post-silicon tests. It introduces a new term to determine the voltage scaling impact on delay elements and also the comparison between the most used DEs on BD designs using this novel metric. An analysis of tests in BD and Blade templates are presented and the impact of voltage scaling in these designs is analyzed. Finally, a novel delay element is proposed focusing in margin reduction and reduction in test time for Blade template.