Pre-silicon verification is an essential part of integrated circuit design to capture functional design errors. Complex simulation, emulation and formal verification tools are used in a virtual environment before the device is manufactured in silicon. However, as the design complexity increases and the design cycle becomes shorter for fast time-to-market, design errors are more likely to escape from the pre-silicon verification and functional bugs are found during the actual operation. Since manufacturing test primarily focuses on the physical defects, post-silicon validation is the final gatekeeper to capture these escaped design bugs. Consequently, post-silicon validation has become a critical path in shortening the development cycle of System-On-Chip(SoC) design. A major challenge in post-silicon validation is the limited observability of internal states caused by the limited storage capacity available for silicon debugging. Since a post-silicon validation operates on a fabricated chip, recording the values of each and every internal signals is not possible. Due to this limitation of post-silicon validation, acquiring the circuit's internal behavior with the limited available resources is a very challenging task in post-silicon validation. There are two main categories to expand the observability: trace and scan signal based approaches. Real time system response during silicon debug can be acquired using a trace signal based technique; however due to the limited space for the trace buffer, the selection of the trace signals is very critical in maximizing the observability of the internal states. The scan based approach provides high observability and requires no additional design overhead; however the designers cannot acquire the real time system response since the circuit operation has to be stopped to transfer the internal states. Recent research has shown that observability can be enhanced if trace and scan signals can be efficiently combined together, compared to the other debugging scenarios where only trace signals are monitored. This dissertation proposes an enhanced and systematic algorithm for the efficient combination of trace and scan signals using restorability values to maximize the observability of internal circuit states. In order to achieve this goal, we first introduce a technique to calculate restorability values accurately by considering both local and global connectivity of the circuit. Based on these restorability values, the dynamic trace signal selection algorithm is proposed to provide a higher number of restored states regardless of the incoming test vectors. Instead of using total restorability values, we separate 0 and 1 restorability values to differentiate the different circuit responses to the different incoming test vectors. Also, the two groups of trace signals can be selected dynamically based on the characteristics of the incoming test vectors to minimize the performance degradation with respect to the different incoming test vectors. Second, we propose a new algorithm to find the optimal number of trace signals, when trace and scan signals are combined together for better observability. Our technique utilizes restorability values and finds the optimal number of trace signals so that the remaining space of trace buffer can be utilized for the scan signals. Observability can be enhanced further with data compression technique. Since the entries of the dictionary are determined from the golden simulation, a high compression ratio can be achieved with little extra hardware overhead. Experimental results on benchmark circuits and a real industry design show that the proposed technique provides a higher number of restored states compared to the existing techniques. / text

Timing analysis is a key sign-off step in the design of today's chips, but technology scaling introduces many sources of variability and uncertainty that are difficult to model and predict. The result of these uncertainties is a degradation in our ability to predict the performance of fabricated chips, i.e., a lack of model-to-hardware matching. The prediction of circuit performance is the result of a complex hierarchy of models ranging from the basic MOSFET device model to full-chip models of important performance metrics including power, frequency of operation, etc. The assessment of the quality of such models is an important activity, but it is becoming harder and more complex with rising levels of variability and the increase in the number of systematic effects observed in modern CMOS processes. The purpose of this research is (i) to introduce special-purpose test structures that specifically focus on ensuring the accuracy of gate timing models, and (ii) to introduce methods that analyze the extracted information, in the form of path delay measurements, using the proposed test structures. The certification of digital design correctness (the so-called signoff) is based largely on the results of performing Static Timing Analysis (STA), which, in turn, is based entirely on the gate timing models. The proposed test structures compare favorably to alternative approaches; they are far easier to measure than direct delay measurement, and they are much more general than simple ring-oscillator structures. Furthermore, the structures are specified at a high level, allowing them to be synthesized using a standard ASIC place-and-route flow, thus capturing the local layout systematic effects which can sometimes be lost by simpler (e.g., ring oscillator) structures. For the silicon timing analysis, we propose methods that deduce segment delays from the path delay measurements. These estimated segment delays using our methods can be directly compared with the timing models. Therefore, it will be easy to identify the cause of timing mismatches. Deducing segment delays from path delays, however, is not an easy problem. The difficulties associated with deconvolving segment delays from measured path delays come from insufficient sampling points. To overcome this limitation, we first group the segments based on certain characteristics of segments, and adapt Moore-Penrose pseudo-inverse method to approximately solve the segment delays. Secondly, we used equality-constrained least squares methods, which enable us to find a unique and optimized solution of segment delays from underdetermined systems. We also propose another improved test structure that has a built-in test pattern generator, and hence does not require ATPG (Automatic Test Pattern Generation). It is a self-timed circuit, and this feature makes the test structure run as fast as it can. Therefore, measurements can be made under high speed switching conditions. Finally, we can study dynamic effects such as timing effects of different levels of switching activities and voltage drop with the new test structure. / text

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abstract: Digital systems are essential to the technological advancements in space exploration. Microprocessor and flash memory are the essential parts of such a digital system. Space exploration requires a special class of radiation hardened microprocessors and flash memories, which are not functionally disrupted in the presence of radiation. The reference design ‘HERMES’ is a radiation-hardened microprocessor with performance comparable to commercially available designs. The reference design ‘eFlash’ is a prototype of soft-error hardened flash memory for configuring Xilinx FPGAs. These designs are manufactured using a foundry bulk CMOS 90-nm low standby power (LP) process. This thesis presents the post-silicon validation results of these designs. / Dissertation/Thesis / Masters Thesis Electrical Engineering 2016

abstract: Digital systems are increasingly pervading in the everyday lives of humans. The security of these systems is a concern due to the sensitive data stored in them. The physically unclonable function (PUF) implemented on hardware provides a way to protect these systems. Static random-access memories (SRAMs) are designed and used as a strong PUF to generate random numbers unique to the manufactured integrated circuit (IC). Digital systems are important to the technological improvements in space exploration. Space exploration requires radiation hardened microprocessors which minimize the functional disruptions in the presence of radiation. The design highly efficient radiation-hardened microprocessor for enabling spacecraft (HERMES) is a radiation-hardened microprocessor with performance comparable to the commercially available designs. These designs are manufactured using a foundry complementary metal-oxide semiconductor (CMOS) 55-nm triple-well process. This thesis presents the post silicon validation results of the HERMES and the PUF mode of SRAM across process corners. Chapter 1 gives an overview of the blocks implemented on the test chip 25. It also talks about the pre-silicon functional verification methodology used for the test chip. Chapter 2 discusses about the post silicon testing setup of test chip 25 and the validation of the setup. Chapter 3 describes the architecture and the test bench of the HERMES along with its testing results. Chapter 4 discusses the test bench and the perl scripts used to test the SRAM along with its testing results. Chapter 5 gives a summary of the post-silicon validation results of the HERMES and the PUF mode of SRAM. / Dissertation/Thesis / Masters Thesis Electrical Engineering 2017

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<p>The number of speed-limiting paths in modern digital integrated circuits (ICs) is in the range of millions. Due to un-modelled electrical effects and process variations in advanced fabrication technologies, it is difficult for pre-silicon timing analysis tools to provide accurate delay estimates. Hence, programmable delay elements are commonly inserted in high-performance circuits in order to provide a tuning mechanism at the post-silicon phase. Due to the large number of such tuning elements, finding the appropriate configuration bits for each element mandates an automated approach.</p> <p>In this thesis we present three contributions to the field of digital IC design automation that leverage the presence of programmable delay tuning elements. These new automated approaches are geared toward three distinct objectives. The first one is to maximize the circuit performance using a scalable algorithmic framework. The second objective is to combat the lifetime performance degradation caused by circuit aging. The final objective is to improve the timing of the scan enable signal during the at-speed testing of digital ICs.</p> <p>As the programmable delay tuning elements will become prevalent in the future generations of digital ICs, the contributions from this thesis will help improve the design methodologies that are expected to evolve in order to address at runtime the timing problems introduced by the increased fabrication process variability.</p> / Doctor of Philosophy (PhD)