In the past few years, due to the rapid advance in technology and the aid of 3D graphics applications the world of 3D graphics is rapidly expanding from desktop computers and dedicated gaming consoled to handheld devices, such as cellular phones, PDAs, laptops etc.,. However, unlike traditional desktop computers and gaming consoles, mobile computing devices typically have slower processors that have less capability for handling large computation-intensive workloads like 3D graphics application. In addition, the power consumption is one of the major design specifications to realize the 3D graphics accelerating engine for mobile devices because handheld batteries have limited lifetimes. Moreover, the size of chip is depend on the Moore¡¦s Law: The number of transistors in a chip are double in every eighteen months. Even though the produce cost is decrease, but the capacity of battery cannot increase like the transistors. Therefore, how to reduce power consumption by using efficient power management techniques has become a very important research topic in 3D graphics SoC design. For 3D graphics applications, dynamic voltage and frequency scaling (DVFS) is a good candidate to reduce the power consumption of 3D graphics accelerating engine. So many relative papers have researched in how to accurately predict the workload and scale the voltage and frequency. The prediction policy can divide into History-based predictor [1] and Frame-structure predictor [2-4]. The History-based predictor predicts the latter frame workload by previous frame workload to scale the voltage, and the frame-structure predictor performs offline and then determine the different kind of frame for an application. A table is used to save the mapping of different kind of frame to the voltage, and then the voltage is scaled according to the mapping table. A lot of researchers put the power management policy in software i.e. processors, but our proposed workload prediction scheme has been realized into the hardware circuit. Therefore, it can not only reduce the overhead of processor but also quickly adjust the voltage and frequency of 3D graphics accelerating engine. Our prediction policy is one of the History-based predictor ,and it is an adaptive PID predictor [5-6] in which the parameters of Proportional controller and Integral controller can be adaptively adjusted so that it can obtain more accurate prediction results than non-adaptive predictor. In general, the workload that the selected voltage can handle is usually over than the predicted workload. That is, actual workload is usually less than predicted workload. So that the slack time will be generated. We can utilize the slack time through Inter-frame compensation [7-10] to save more energy while maintaining the similar output quality. We use a simple policy to adaptively select the parameters for compensation between the frames to simplify the hardware architecture of the power management policy. Experimental results show that, we can get more energy saving and more accurate workload prediction when the adaptive PI predictor and adaptive Inter-frame compensation are utilized.

Network Processors are multicore processors capable of processing network packets at wire speeds of multi-Gbps. Due to their high performance and programmability, these processors have become the main computing elements in many demanding network processing equipments like enterprise, edge and core routers. With the ever increasing use of the internet, the processing demands of these routers have also increased. As a result, the number and complexity of the cores in network processors have also increased. Hence, efficiently managing these cores has become very challenging. This dissertation discusses two main issues related to efficient usage of large number of parallel cores in network processors: (1) How to allocate work to the processing cores to optimize performance? (2) How to meet the desired performance requirement power efficiently? This dissertation presents the design of a hash based scheduler to distribute packets to cores. The scheduler exploits multiple dimensions of locality to improve performance while minimizing out of order delivery of packets. This scheduler is designed to work seamlessly when the number of cores allocated to a service is changed. The design of a resource allocator is also presented which allocates different number of cores to services with changing traffic behavior. To improve the power efficiency, a traffic aware power management scheme is presented which exploits variations in traffic rates to save power. The results of simulation studies are presented to evaluate the proposals using real and synthetic network traces. These experiments show that the proposed packet scheduler can improve performance by as much as 40% by improving locality. It is also observed that traffic variations can be exploited to save significant power by turning off the unused cores or by running them at lower frequencies. Improving performance of the individual cores by careful scheduling also helps to reduce the power consumption because the same amount of work can now be done with fewer cores with improved performance. The proposals made in this dissertation show promising improvements over the previous work. Hashing based schedulers have very low overhead and are very suitable for data rates of 100 Gbps and even beyond. / text

Energy consumption by computing systems is rapidly increasing due to the growth of data centers and pervasive computing. In 2006 data center energy usage in the United States reached 61 billion kilowatt-hours (KWh) at an annual cost of 4.5 billion USD [Pl08]. It is projected to reach 100 billion KWh by 2011 at a cost of 7.4 billion USD. The nature of energy usage in these systems provides an opportunity to reduce consumption. Specifically, the power and performance demand of computing systems vary widely in time and across workloads. This has led to the design of dynamically adaptive or power managed systems. At runtime, these systems can be reconfigured to provide optimal performance and power capacity to match workload demand. This causes the system to frequently be over or under provisioned. Similarly, the power demand of the system is difficult to account for. The aggregate power consumption of a system is composed of many heterogeneous systems, each with a unique power consumption characteristic. This research addresses the problem of when to apply dynamic power management in multi-core processors by accounting for and predicting power and performance demand at the core-level. By tracking performance events at the processor core or thread-level, power consumption can be accounted for at each of the major components of the computing system through empirical, power models. This also provides accounting for individual components within a shared resource such as a power plane or top-level cache. This view of the system exposes the fundamental performance and power phase behavior, thus making prediction possible. This dissertation also presents an extensive analysis of complete system power accounting for systems and workloads ranging from servers to desktops and laptops. The analysis leads to the development of a simple, effective prediction scheme for controlling power adaptations. The proposed Periodic Power Phase Predictor (PPPP) identifies patterns of activity in multi-core systems and predicts transitions between activity levels. This predictor is shown to increase performance and reduce power consumption compared to reactive, commercial power management schemes by achieving higher average frequency in active phases and lower average frequency in idle phases. / text

The objective of this dissertation is to develop task scheduling guidelines and algorithms for wireless sensor nodes that harvest energy from ambient environment and use supercapacitor based storage systems to buffer the harvested energy. This dissertation makes five contributions. First, a physics based equivalent circuit model for supercapacitors is developed. The variable leakage resistance (VLR) model takes into account three mechanisms of supercapacitors: voltage dependency of capacitance, charge redistribution, and self-discharge. Second, the effects of time and supercapacitor initial state on supercapacitor voltage change and energy loss during charge redistribution are investigated. Third, the task scheduling problem in supercapacitor based environmentally powered wireless sensor nodes is studied qualitatively. The impacts of supercapacitor state and energy harvesting on task scheduling are examined. Task scheduling rules are developed. Fourth, the task scheduling problem in supercapacitor based environmentally powered wireless sensor nodes is studied quantitatively. The modified earliest deadline first (MEDF) algorithm is developed to schedule nonpreemptable tasks without precedence constraints. Finally, the modified first in first out (MFIFO) algorithm is proposed to schedule nonpreemptable tasks with precedence constraints. The MEDF and MFIFO algorithms take into account energy constraints of tasks in addition to timing constraints. The MEDF and MFIFO algorithms improve the energy performance and maintain the timing performance of the earliest deadline first (EDF) and first in first out (FIFO) algorithms, respectively.

Voyage planning methods have advanced significantly in recent years to take advantage of the increasingly available computing power. With the aid of detailed weather predictions it is now possible to decide a route that is optimized with respect to some criterion. With the introduction of so called All Electric Ships; ships with diesel electric propulsion, varying the power production in order to adjust the propulsion has become easier. Incorporating a power management system with the voyage planning software on a ship allows for different techniques to reduce fuel consumption. In this thesis, three different approaches are developed, compared and combined. The first method handles the task of how to optimally share a load demand across a set of generators. The second is performing power production scheduling with respect to engine efficiencies, and finally in the third the potential in energy storage integration with the power management system is investigated. From the results, it is argued that the largest potential lies in the first approach where large fuel savings can be made without any large risk. The second approach shows potential for fuel reduction but this however is found to be heavily dependent on weather predictions and accuracy of the used models. Regarding energy storage it is found that while it is not economically feasible to increase the fuel efficiency, energy storage can be used to handle load transients and fulfil power redundancy requirements.

In this thesis, we propose a stochastic power management strategy for in-wheel motor electric vehicles (IWM-EVs) to optimize energy consumption and to increase driving range. The driving range for EVs is a critical issue since the battery is the only source of energy. Considering the unpredictable nature of the driver’s power demand, a stochastic dynamic programing (SDP) control scheme is employed. The Policy Iteration Algorithm, one of the efficient SDP algorithms for infinite horizon problems, is used to calculate the optimal policies which are time-invariant and can be implemented directly in real-time application. Applying this control package to a high-fidelity model of an in-wheel motor electric vehicle developed in the Autonomie/Simulink environment results in considerable battery charge economy performance, while it is completely free to launch since it does not need further sensor and communication system. In addition, a skid avoidance algorithm is integrated to the power management strategy to maintain the wheels’ slip ratios within the desired values. Undesirable slip ratio causes poor brake and traction control performances and therefore should be avoided. The simulation results with the integrated power management and skid avoidance systems show that this system improves the braking performance while maintaining the power efficiency of the power management system.

Rechargeable batteries are found in almost every battery powered application. Be it portable, stationary or motive applications, these batteries go hand in hand with battery charging systems. With energy harvesting being targeted in this day and age, high energy density and longer lasting batteries with efficient charging systems are being developed by companies and original equipment manufacturers. Whatever the application may be, rechargeable batteries, which deliver power to a load or system, have to be replenished or recharged once their energy is depleted. Battery charging systems must perform this replenishment by using very fast and efficient methods to extend battery life and to increase periods between charges. In this regard, they have to be versatile, efficient and user programmable to increase their applications in numerous battery powered systems. This is to reduce the cost of using different battery chargers for different types of battery powered applications and also to provide the convenience of rare battery replacement and extend the periods between charges. This thesis proposes a user programmable charging system that can charge a Lithium ion battery from three different input sources, i.e. a wall outlet, a universal serial bus (USB) and an energy harvesting system. The proposed charging system consists of three main building blocks, i.e. a pulse charger, a step down DC to DC converter and a switching network system, to extend the number of applications it can be used for. The switching network system is to allow charging of a battery via an energy harvesting system, while the step down converter is used to provide an initial supply voltage to kick start the energy harvesting system. The pulse charger enables the battery to be charged from a wall outlet or a USB network. It can also be reconfigured to charge a Nickel Metal Hydride battery. The final design is implemented on an IBM 0.18µm process. Experimental results verify the concept of the proposed charging system. The pulse charger is able to be reconfigured as a trickle charger and a constant current charger to charge a Li-ion battery and a Nickel Metal Hydride battery, respectively. The step down converter has a maximum efficiency of 90% at an input voltage of 3V and the charging of the battery via an energy harvesting system is also verified.

This thesis focuses on the feasibility of designing a commercial hybrid electric vehicle (HEV). In this work, relevant system models are developed for the vehicle including powertrain, braking system, electrical machines and battery. Based on these models ten different HEV configurations are assembled for detailed assessment of fuel consumption. This thesis also proposes a smart power management strategy which could be applied to any kind of HEV configuration. The suggested expert system deals with the external information about the driving conditions and modes of the driver as well as the internal states of the internal combustion engine efficiency and the state of charge of the battery, and decides on the power distribution between two different power supplies based on the predefined algorithms. The study illustrates the characteristics of the powertrain components for various HEV configurations. The work also shows the power flow of HEV configurations with the developed smart power management system and therefore, the effectiveness of power management strategies has been evaluated in detail.

Computing systems are experiencing a significant evolution triggered by the convergence of multiple technologies including multicore processor architectures, expanding I/O capabilities (e.g., storage and wireless communication), and virtualization solutions. The integration of these technologies has been driven by the need to deliver performance and functionality for applications being developed in emerging mobile and enterprise systems. These accomplishments, though, have come at the cost of increased power and thermal signatures of computing platforms. In response to the resulting power issues, power centric policies have been deployed across all layers of the stack including platform hardware, operating systems, application middleware, and virtualization components. Effective active power management requires that these independent layers or components behave constructively to attain globally desirable benefits. Two choices are (1) to tightly integrate different policies using negotiated management decisions, and (2) to coordinate their use based on the localized policy decisions that are already part of modern computer architectures and software systems. Recognizing the realities of (2), the goal of this thesis is to identify, define, and evaluate novel system-level coordination mechanisms between diverse management components that exist across system layers. The end goal of these mechanisms, then, is to enable synergistic behaviors between management entities, across different levels of abstraction, and across different physical platforms to improve power management functionality. Contributions from this work include operating system level mechanisms that dynamically capture workload behavior thereby enabling power efficient scheduling, and system descriptor mechanisms that allow for improved workload allocation and resource management schemes. Finally, observing the strong need for coordination in managing virtualized systems due to the existence of multiple, independent system layers, a set of extensions to virtualization architectures for effectively coordinating VM management in datacenters are developed.

The single-core performance trend predicted by Moore's law has been impeded in recent years partly due to the limitations imposed by increasing processor power demands. One way to mitigate this limitation in performance improvement is the introduction of multi-core and multi-processor computation. Another approach to increasing the performance-per-Watt metric is to utilize the processor's power more efficiently. In a single-core system, the processor cannot sustainably dissipate more than the nominal Thermal Design Power (TDP) limit determined for the processor at design time. Therefore it is important to understand and manage the power demands of the processes being executed. This principle also applies to multi-core and multi-processor environments. In a multi-processor environment, knowing the power demands of the workload, the power management unit can schedule the workload to a processor based on the state of each processor and process in the most efficient way. This is an example of the knapsack problem. Another approach, also applicable to multi-cores, could be to reduce the core's power by reducing its working voltage and frequency, leading to mitigation of the power bursts, lending more headroom to other cores, and keeping the total power under the TDP limit. The information collected from the execution of the software running on the processor (i.e. the workload) is the key to determining the actions needed with regards to power management at any given time. This work comprises two different approaches in improving the comprehension of software power demands as it executes on the processor. In the first part of this work, the effects of software data on power is analysed. It is important to be able to model the power based on the instructions it comprises, however, to the best of our knowledge, no work exists in which the effects of the values being processed has been investigated with regards to processor power. Creating a power model capable of accurately reflecting the power demands of the software at any given time is a problem addressed by previous research. The software power model can be used in processor simulation environments as well as in the processor itself to create an estimated power dissipation without the need to physically measure the power. In the first part of this research, the effects of software data on power is investigated. In order to collect the data required as part of this research, a profiler tool has been developed by the author and used in this part of the research as well as the second part. The second part of this work focuses on the development of processor power throughout time during the execution of the software. Understanding the power demands of the processor at any given time is important to maintain and manage processor power. Additionally, acquiring an insight into the future power demands of the software can help the system with scheduling planning ahead of time, in order to prepare for any high-power section of the code as well as to plan to use the available power headroom as a result of an upcoming low-power section. In this part of our work, a new hierarchical approach to software phase classification is developed. Software phase classification problem focuses on determining the behaviour of the software at any given time slice by assigning the time slice to one of pre-determined software phases. Each phase is assumed to have known behaviour which was previously measured and instrumented based on previously observed instances of the phase, or by utilizing a model capable of estimating the behaviour of each phase. Using a two-tiered hierarchical clustering approach, our proposed phase classification methodology incorporates the recent performance behaviour of the software in order to determine the power phase. We focused on determining the power phase using the performance information because the real processor power is not usually available without the need for added hardware, while there exists a large number of different performance counters available on most modern processors. Additionally, based on our observations, the relation between performance phases and power behaviour is highly predictable. This method is shown to provide robust results with a low amount of noise compared to other methods, while providing a high enough timing accuracy for the processor to act on. To the best of our knowledge, no other existing work is able to provide both timing accuracy and reduced noise compared to our work. Software phase classification can be used to control the processor power based on the software's phase at any given time, but it does not provide future insight into the progression of the workload. Finally, we developed and compared several phase prediction methodologies based on phase precursors and phase locality concepts. Phase precursor-based methods rely on detecting the precursors observed before the software enters a certain phase, while phase locality methods rely on the locality principle, which postulates a high probability for the current software behaviour to be observed in the near-future. The phase classification, as well as phase prediction methodologies was shown to be able to reduce the power bursts within a workload in order to provide a more smooth power trace. As the bursts are removed from one workload's power trace, the multi-core processor power headroom can be confidently utilized for another process. / Graduate