There have been many efforts to improve efficiency of transmitter while meeting stringent linearity requirement of modern communication system. Among the technology to enhance efficiency of linear transmitter, the out-phasing technologies, also called the linear amplification with nonlinear components (LINC), is considered as a promising technology. LINC has been studied long times, since it provides excellent linearity with high efficiency by allowing adopt high efficient switch-mode power amplifiers. However, The LINC transmitter has some technical challenges: linearity degradation due to amplitude and phase mismatches, efficiency degradation due to poor combining efficiency, and narrow frequency bandwidth due to output matching network of switching power amplifier. In this thesis, some state-of-the-art techniques for solving the problems of LINC transmitters are presented. An unbalanced phase calibration technique compensates amplitude/phase mismatches between two parallel paths in the LINC system, and multi-level LINC (MLINC) and an uneven multi-level LINC (UMLINC) structure improve the overall power efficiency. And the reconfigurable Class-D switching PA enables multi-band operation with high efficiency and good linearity. With these techniques, the new multi-band out-phasing transmitter improves the efficiency without sacrificing the linearity performance.

The objective of this research is to explore circuit techniques and architectures suitable for implementation in digital technologies, that can be used to enhance the efficiency of power stages. Specifically, the use of switching power stages with pulse-width modulation techniques is considered. Switching power stages, such as Class D amplifiers, are inherently well-suited for implementation in deep-submicron CMOS. Pulse-width modulation (PWM) employs discrete amplitude levels and encodes signal information in local time-based averages, and as such can also benefit from such technologies. Additionally PWM does not suffer from quantization noise, and is well-suited for low noise applications. PWM designs, that can be applied for a range of signal bandwidth requirements, spanning several tens to hundreds of kHz are proposed. Applications for these architectures include audio systems, powerline communications and wireless communications. Design challenges and requirements that can arise in different application contexts are considered in the specification of the architectures. A common goal in the definition of the architectures is to minimize complexity of the designs. In the first part of the dissertation, a third-order self-oscillating PWM class-D amplifier for audio applications, that utilizes a hysteretic comparator is described. The design is analyzed and its THD is theoretically determined by employing an equivalent model, that relates the approach to natural sampling pulse-width modulation. The architecture eliminates the requirement for a high-quality carrier generator. A low-cost hysteresis compensation technique is utilized to enhance distortion performance at high output power levels. An implementation is presented in a 0.7um CMOS process. The design achieves a dynamic range (DR) of 116.5 dB, and a THD+N of 0.0012%, while delivering a power of 125 mW into an 8[Omega] load at 1 kHz. The THD+N is under 0.006% up to 90% of the maximum output power. The amplifier can deliver 1.45 W into the load with a THD of 5% with a 5 V power supply. The efficiency is greater than 84% for output power larger than 1 W. The area of the amplifier is 6 mm². The achieved performance indicates that the design is well-suited for high-performance audio applications. A class D line driver that utilizes a phase-locked loop (PLL) based PWM generation technique is presented next. The principle of operation, and implementation details relating to loop stability, linearity and noise performance are analyzed. An implementation is presented in a 130nm CMOS process. The amplifier can deliver 1.2 W into an 6.8[Omega] load with a 4.8 V power supply. The architecture eliminates the requirement for a high-quality carrier generator and a fast, continuous voltage comparator that are often required in PWM implementations. The design can achieve a THD of -65 dB, with a switching frequency that can be as high as 20 MHz. The peak efficiency is 83% for output power larger than 1 W, for a switching frequency of 10 MHz. The area of the amplifier is 2.25 mm². This architecture is potentially suitable for powerline applications. Finally, a phase-locked loop based PWM Cartesian transmitter with the capability to drive switched power amplifiers, such as a Class D power amplifier, is proposed. A phase-locked loop based technique is employed to generate a high-frequency PWM pulse stream centered at 1.28 GHz. The prototype is simulated in a 130 nm CMOS process, and achieves 35% peak efficiency for 17 dBm output power with a carrier frequency of 900 MHz. Operation of the architecture with non-constant envelope modulation, such as that employed in the WCDMA standard, is verified in simulation. / text

The objective of the proposed research is to characterize the safe-operating-area of silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) under radiofrequency (RF) operation and extreme environments. The degradation of SiGe HBTs due to mixed-mode DC and RF stress has been modeled for the first time. State-of-the-art 200 GHz SiGe HBTs were first characterized, and then DC and RF stressed. Excess base leakage current was modeled as a function of the stress current and voltage. This physics-based stress model was then designed as a sub-circuit in Cadence, and incorporated into SiGe power amplifier design to predict the DC and RF stress-induced excess base current. Based on these studies, characterization of RF safe-operating-area for SiGe HBTs using devices and circuits is proposed.

Active magnetic bearings (AMBs) have become a key technology in industrial applications with a continued drive for cost reduction and an increase in reliability. AMBs require position feedback to suspend the rotor. Conventional contactless position sensors are used to measure the rotor's position. The major disadvantages of conventional position sensors are their cost and that the sensors are viewed as a weak point in an AMB system. A self-sensing sensor is a type of sensor which is cost effective, reduces sensor wire-length and increases reliability, thus ideal for the industry. This type of sensor relies on the current and voltage signals of the AMB's to obtain the rotor position. Due to the rapid and advanced development of digital electronics, it has become more powerful and cheaper, thus self-sensing in mass production will be cost effective. Different self-sensing approaches were developed in the past and can be divided into two main categories: state estimation and amplitude modulation approaches. In this research the focus will be on the amplitude modulation approach. Amplitude modulation makes use of two signals, namely the modulation signal and the carrier signal. In a self-sensing AMB system the carrier can be a high frequency component injected into the system or the switching ripple of the switch mode power amplifier can be used. The modulation signal is the change in rotor position which results in changing inductances. The actuator material introduces nonlinear effects on the estimated position. Due to these nonlinear effects, it is rather difficult to obtain the rotor position. The first industrial application of a self-sensing turbomolecular pump system was implemented in 2005 by S2M. The aim of this thesis is to evaluate existing self-sensing schemes, devise improvements and investigate possible new schemes. Four different demodulation methods and two new self-sensing schemes are evaluated. An AMB transient simulation model which includes saturation, hysteresis, eddy currents and cross-coupling is used to evaluate the schemes in simulation. The self-sensing schemes are implemented in hardware and evaluated on a 7 A rms 500 N AMB. A comparative study was done on the different self-sensing schemes. From the comparative study it was determined that the gain- and phase effects have a direct effect on the sensitivity of the system. It was also proved that self-sensing can be implemented on a coupled AMB with a sensitivity of 10.3 dB. / Thesis (Ph.D. (Electrical and Electronic Engineering))--North-West University, Potchefstroom Campus, 2009.

Active magnetic bearings (AMBs) have become a key technology in industrial applications with a continued drive for cost reduction and an increase in reliability. AMBs require position feedback to suspend the rotor. Conventional contactless position sensors are used to measure the rotor's position. The major disadvantages of conventional position sensors are their cost and that the sensors are viewed as a weak point in an AMB system. A self-sensing sensor is a type of sensor which is cost effective, reduces sensor wire-length and increases reliability, thus ideal for the industry. This type of sensor relies on the current and voltage signals of the AMB's to obtain the rotor position. Due to the rapid and advanced development of digital electronics, it has become more powerful and cheaper, thus self-sensing in mass production will be cost effective. Different self-sensing approaches were developed in the past and can be divided into two main categories: state estimation and amplitude modulation approaches. In this research the focus will be on the amplitude modulation approach. Amplitude modulation makes use of two signals, namely the modulation signal and the carrier signal. In a self-sensing AMB system the carrier can be a high frequency component injected into the system or the switching ripple of the switch mode power amplifier can be used. The modulation signal is the change in rotor position which results in changing inductances. The actuator material introduces nonlinear effects on the estimated position. Due to these nonlinear effects, it is rather difficult to obtain the rotor position. The first industrial application of a self-sensing turbomolecular pump system was implemented in 2005 by S2M. The aim of this thesis is to evaluate existing self-sensing schemes, devise improvements and investigate possible new schemes. Four different demodulation methods and two new self-sensing schemes are evaluated. An AMB transient simulation model which includes saturation, hysteresis, eddy currents and cross-coupling is used to evaluate the schemes in simulation. The self-sensing schemes are implemented in hardware and evaluated on a 7 A rms 500 N AMB. A comparative study was done on the different self-sensing schemes. From the comparative study it was determined that the gain- and phase effects have a direct effect on the sensitivity of the system. It was also proved that self-sensing can be implemented on a coupled AMB with a sensitivity of 10.3 dB. / Thesis (Ph.D. (Electrical and Electronic Engineering))--North-West University, Potchefstroom Campus, 2009.

This thesis addresses the potential of implementing a predriver for class-D power amplifier for WLAN in 65 nm CMOS technology. In total, eight different predrivers have been created using Cadence Virtuoso CAD tools. All designs have been tested using Agilent's Advance Design System (ADS) and simulated using the ADS-Cadence dynamic link. Furthermore, a comparison between the eight designs and the reference design has been done. The examined parameters were output power (Pout), efficiency, and effective area consumption. The simulation results show that most of the proposed designs obtain higher output power, higher efficiency, and lower effective area than the reference design. For the reference design, output power of 34.2 dBm, efficiency of 20.8 %, and effective area of 63952 um2 were obtained. For design No.1, the effective area was 31511um2, which was almost half of the area occupied by the reference design. For design No.3, the efficiency was 71.2 %, which was almost 3 and half times higher than the efficiency of the reference design. Furthermore, all designs, except design NO.7, gave more or less the same output power (around 34.4 dBm).

In wireless communication systems, multiple standards have been implemented to meet the past and present demands of different applications. This proliferation of wireless standards, operating over multiple frequency bands, has increased the demand for radio frequency (RF) components, and consequently power amplifiers (PA) to operate over multiple frequency bands. In this research work, a systematic approach for the synthesis of a novel dual-band matching network is proposed and applied for effective design of PA capable of maintaining high power efficiency at two arbitrary widely spaced frequencies. The proposed dual-band matching network incorporates two different stages. The first one aims at transforming the targeted two complex impedances, at the two operating frequencies, to a real one. The second stage is a dual-band filter that ensures the matching of the former real impedance to the termination impedance to 50 Ohm. Furthermore, an additional transmission line is incorporated between the two previously mentioned stages to adjust the impedances at the second and third harmonics without altering the impedances seen at the fundamental frequencies. Although simple, the harmonic termination control is very effective in enhancing the efficiency of RF transistors, especially when exploiting the Class J design space. The proposed dual-band matching network synthesis methodology was applied to design a dual-band power amplifier using a packaged 45 W gallium nitride (GaN) transistor. The power amplifier prototype maintained a peak power efficiency of about 68% at the two operating frequencies, namely 800 MHz and 1.9 GHz. In addition, a Volterra based digital predistortion technique has been successfully applied to linearize the PA response around the two operating frequencies. In fact, when driven with multi-carrier wideband code division multiple access (WCDMA) and long term evolution (LTE) signals, the linearized amplifier maintained an adjacent channel power ratio (ACPR) of about 50 dBc and 46 dBc, respectively.

The evolution of wireless technology has necessitated the support of multiple communication standards by mobile devices. At present, multiple chipsets/radios operating at predefined sets of modulation schemes, frequency bands, bandwidths and output power levels are used to achieve this objective. This leads to higher component counts, increased cost and limits the capacity to cope with future communication standards. In order to tackle different wireless standards using a single chipset, digital circuits have been increasingly deployed in radios and demonstrated re-configurability in different modulation schemes (multimode) and frequency bands (multiband). Despite efforts and progress made in digitizing the entire radio, the power amplifier (PA) is still designed using an conventional approach and has become the bottleneck in digital transmitters, in terms of low average power efficiency, poor compatibility with modern CMOS technology and limited re-configurability. This research addresses these issues from two aspects. The first half of the thesis investigates signal encoding issues between the modulator and PA. We propose, analyze and evaluate a new hybrid amplitude/time signal encoding scheme that significantly improves the coding efficiency and dynamic range of a digitally modulated power amplifier (DMPA) without significantly increasing design complexity. The proposed hybrid amplitude/time encoding scheme combines both the amplitude domain and the time domain to optimally encode information. Experimental results show that hybrid amplitude/time encoding results in a 35% increase in the average coding efficiency with respect to conventional time encoding, and is only 6.7% lower than peak efficiency when applied to a Wireless Local Area Network (WLAN) signal with a peak to average power ratio equal to 9.9 dB. A new DMPA architecture, based on the proposed hybrid encoding, is also proposed. The second half of this thesis presents the design, analysis and implementation of a CMOS PA that is amenable to the proposed hybrid encoding scheme. A multi-way current mode class-D PA architecture has been proposed and realized in 130 nm CMOS technology. The designed PA has satisfied the objectives of wide bandwidth (1.5 GHz - 2.7 GHz at 1 dB output power), and high efficiency (PAE 63%) in addition to demonstrating linear responses using the proposed digital encoding. A complete digital transmitter combining the encoder and the multi-way PA was also investigated. The overall efficiency is 27% modulating 7.3 dB peak to average power ratio QAM signals.

CMOS is the favorite candidate process for the high integration of the wireless communication IC blocks, RF frontend and digital baseband circuitry. Also the design of the RF power amplifier stage is the one of the most important part of the RF CMOS circuit design. Since high frequency and high power simultaneously exists on this stage, devices works on the limits of the process. Therefore standard device models may not be valid enough for a successful design. In the thesis high frequency passive device and MOS transistor models for the CMOS process searched though the literature and presented. Besides, different structures of the inductors are investigated for the best quality factor for the chosen process. Class E power amplifiers can reach very high efficiencies and they are very suitable for the low power applications. After the derivation of the classical Class E equations is presented, a new Class E circuit model including MOS transistor&rsquo / s channel resistance is developed and new sets of equations are obtained for the model. Circuit parameters are determined using numerical methods. Class E circuit simulations with these new parameters and earlier parameters are compared. Finally, a 100mW 2.4GHz Class E power amplifier is designed and simulated targeting Bluetooth applications. In this design, Class E circuit parameters are determined for AMS CMOS 0.35um process MOS transistor including the channel resistance. Simulations are performed using Cadence/BSIM3v3 and OrCad PSPICE.

Ces travaux de recherche concernent les amplificateurs RF de puissance pour stations de base. La technologie actuelle de transistor RF la plus compétitive, le LDMOS, est confrontée à l’augmentation constante du débit et à la concurrence d’autres technologies comme le HEMT GaN. Un autre challenge est l’intégration de l’adaptation de sortie réalisée en dehors du boîtier qui n’est plus compatible avec les futurs standards combinant jusqu’à soixante-quatre amplificateurs de puissance proches les uns des autres.Une première piste envisagée dans cette thèse est le substrat Si à haute résistivité. A partir de simulations puis de mesures sur plaques, l’amélioration du facteur de qualité des éléments passifs a été démontrée mais ces premières investigations ne permettent pas l’intégration de l’adaptation de sortie avec la technologie actuelle bien que les résultats soient très encourageants. Les challenges technologiques de ce nouveau substrat ont mené à considérer la structure différentielle pour les amplificateurs. En plus des avantages connus de cette configuration, nous avons montré que la conception d’un amplificateur de puissance différentiel montre une amélioration importante de la bande instantanée répondant au besoin d’un débit toujours plus élevé. Cette amélioration ne dégrade pas les autres performances en gain, rendement et puissance de sortie. Dans la continuité de cette thèse, les perspectives concernent la conception d’un amplificateur de puissance sur substrat SI à haute résistivité combinée à une structure différentielle qui pourrait permettre une avancée majeure sur toutes les performances tout en gardant l’avantage du faible coût du LDMOS Silicium en comparaison des autres substrats. / This research concerns the RF power amplifiers for base stations. The current most competitive technology of RF transistor, the LDMOS, faces the constantly increasing data rate and competition from other technologies such as GaN HEMT. Another challenge is the integration of the output matching made outside of the package which is not compatible with future standards combining up to sixty-four power amplifiers close to each other. A first track proposed in this thesis is the high resistivity Si substrate. From simulations and measurements on wafers, improved passive elements quality factor has been demonstrated but these initial investigations do not allow the integration of the output matching with the current technology, although the results are very encouraging. The technological challenges of this new substrate led to consider the differential structure for amplifiers. Besides to the known advantages of this configuration, we have shown that the design of a differential power amplifier shows a significant improvement in the instantaneous band width meeting the need for higher data rate. This improvement does not degrade other performance as gain, efficiency and output power. In continuation of this thesis, the perspective concerns the design of a power amplifier on a high resistivity Si substrate combined with a differential structure that could enable a major advance over all performance while keeping the advantage of low cost of LDMOS silicon compared to other substrates.