This project consists of analyzing and finding solutions to the effect of non-linear distortionon the performance of a Massive Multiple Input Multiple Output (MIMO) system interms of Spectral Efficiency (SE) and Symbol Error Rate (SER). Massive MIMO is one ofthe technologies that are considered the backbone of the 5th generation of wireless communicationsand therefore this technology has gathered much interest from researchersand companies alike [19], as it is proven that this kind of system greatly improves thecapacity of the wireless connection [8]. Since Massive MIMO is still a relatively newtechnology and it is yet to be implemented for commercial use, there are several challengesthat arise when trying to implement such a system. One of these problems arisefrom the fact that the Power Amplifiers (PAs) in the transmitters of Massive MIMO systemsare non-linear and thus impose a distortion on the transmitted signals of the system[12]. The thesis aims to study this non-linear effect on the performance of massive MIMOsystems by first modelling the distortion effect on the transmitted signals using two differentnon-linear models. Moreover, closed-form expressions for one of the models areformed to facilitate the simulation of the non-linear model and facilitate the analysis ofthe distortion effect on the performance metrics. Then the established system model issimulated and based on the results, the effect of each of the power amplifier non-lineardistortion models on the performance metrics of the Massive MIMO system is studied.Furthermore, based on the analysis of the simulation results, a compensation mechanismis introduced to the Massive MIMO system in order to mitigate the distortion effect onthe system performance in terms of SER and SE.

abstract: The drive towards device scaling and large output power in millimeter and sub-millimeter wave power amplifiers results in a highly non-linear, out-of-equilibrium charge transport regime. Particle-based Full Band Monte Carlo device simulators allow an accurate description of this carrier dynamics at the nanoscale. This work initially compares GaN high electron mobility transistors (HEMTs) based on the established Ga-face technology and the emerging N-face technology, through a modeling approach that allows a fair comparison, indicating that the N-face devices exhibit improved performance with respect to Ga-face ones due to the natural back-barrier confinement that mitigates short-channel-effects. An investigation is then carried out on the minimum aspect ratio (i.e. gate length to gate-to-channel-distance ratio) that limits short channel effects in ultra-scaled GaN and InP HEMTs, indicating that this value in GaN devices is 15 while in InP devices is 7.5. This difference is believed to be related to the different dielectric properties of the two materials, and the corresponding different electric field distributions. The dielectric effects of the passivation layer in millimeter-wave, high-power GaN HEMTs are also investigated, finding that the effective gate length is increased by fringing capacitances, enhanced by the dielectrics in regions adjacent to the gate for layers thicker than 5 nm, strongly affecting the frequency performance of deep sub-micron devices. Lastly, efficient Full Band Monte Carlo particle-based device simulations of the large-signal performance of mm-wave transistor power amplifiers with high-Q matching networks are reported for the first time. In particular, a CellularMonte Carlo (CMC) code is self-consistently coupled with a Harmonic Balance (HB) frequency domain circuit solver. Due to the iterative nature of the HB algorithm, this simulation approach is possible only due to the computational efficiency of the CMC, which uses pre-computed scattering tables. On the other hand, HB allows the direct simulation of the steady-state behavior of circuits with long transient time. This work provides an accurate and efficient tool for the device early-stage design, which allows a computerbased performance evaluation in lieu of the extremely time-consuming and expensive iterations of prototyping and experimental large-signal characterization. / Dissertation/Thesis / Ph.D. Electrical Engineering 2011

In this thesis, a new way of using predisortion for linearization of power amplifiers is evaluated. In order to achieve an adequate power level for the jamming signal, power amplifiers are used in military jamming systems. Due to the nonlinear characteristic of the power amplifier, distortion will be present at the output. As a consequence, unwanted frequencies are subject to jamming. To decrease the distortion, linearization of the power amplifier is necessary. In the system of interest, a portion of the distorted power amplifier output signal is fed back. Using this measurement, a predistortion signal is synthesized to allow suppression of the unwanted frequency components. The predistortion signal is updated a number of times in order to achieve a good outcome. Simulations are carried out in Matlab for testing of the algorithm. The evaluation of the new linearization technique shows promising results and that good suppression of distortion components is achieved. Furthermore, new predistortion features are possible to implement, such as predistorsion in selected frequency bands. However, real hardware testing needs to be carried out to confirm the results.

This thesis discusses the design, construction and testing of a highefficiency, 100 MHz, 1 kW, Class-E solid state power amplifier. The design was performed with the aid of computer simulations using electronic design software (ADS). The amplifier was constructed around Ampleon's BLF188XR LDMOS transistor in a single ended design. The results for 100 MHz operation show a power added efficiency of 82% at 1200 W pulsed power output. For operation at 102 MHz results show a power added efficiency of 86% at 1050 W pulsed power output. Measurements of the drain- and gate voltage waveforms provide validation of Class-E operation.

Les signaux des nouveaux standard de communications (LTE) ont une grande différence entre la puissance maximale et moyenne (PAPR), cela n'est pas favorable pour l'utilisation dans les amplificateurs conventionnels vu qu'ils présentent un rendement maximale seulement quand ils travaillent au niveau de puissance maximale. Des amplificateurs de puissance Doherty pour présenter une efficacité constante pour une large gamme de puissance constituent une solution favorable à ce problème. Ce travail présente la méthodologie de conception et des résultats de mesure d'un amplificateur de puissance Doherty entièrement intégré dans la technologie 65 nm CMOS avec une constante PAE sur un 7 dB de plage de puissance. Mesures de 2,4 GHz à 2,6 GHz montrent des performances constantes PAE à partir du niveau de 20% jusqu'à 24% avec une puissance de sortie maximale de 23,4 dBm. Le circuit a été conçu avec une attention particulière pour le faible coût. / The signals of the new communication standards (LTE) show a great difference between the peak and its average power (PAPR) being unsuitable for use with conventional power amplifiers because they present maximum efficiency only when working with maximum power. Doherty power amplifiers for presenting a constant efficiency for a wide power range represent a favorable solution to this problem. This work presents the design methodology and measurements results of a fully integrated Doherty Power Amplifier in 65 nm CMOS technology with constant PAE over a 7 dB backoff. Measurements from 2.4 GHz to 2.6 GHz show constant PAE performance starting in 20% level up to 24% with a maximum output power of 23.4 dBm.The circuit was designed with special attention to low cost.

Dans l’ère des systèmes de communication multi-standards, le besoin des circuits en radio fréquence (RF) flexibles et reconfigurables pousse l´industrie et le monde académique vers la recherche d´architectures alternatives d’émetteurs et de récepteurs RF. Dans cette thèse, nous nous intéressons aux émetteurs RF flexibles. Nous présentons une architecture basée sur l’utilisation d’un oscillateur de puissance composé d´un amplificateur de puissance dans une boucle de rétroaction positive. Pour des raisons de compatibilité avec des circuit numériques et dans le but de minimiser les coûts de fabrication, nous avons choisi la technologie CMOS. Ce choix génère des difficultés de conception des circuits en RF à cause des faibles tensions de claquage. Cette contrainte de conception a motivé le choix de la classe EF2 pour l’amplificateur de puissance afin de réduire le stress en tension sur les transistors. Nous présentons la conception de cet amplificateur de puissance de classe EF2, ainsi que la conception de l’oscillateur de puissance. Nous validons cette architecture avec une implémentation en technologie CMOS 0.13um de STMicroelectronics. Nous démontrons le bon comportement par une campagne de mesures des circuits fabriqués. Ce circuit répond aux contraintes de flexibilité de modulation et de puissance de sortie. Il peut donc être utilisé pour différents standards de communications. Les limitations inhérentes de cette architecture sont discutées et une modélisation mathématique est présentée. / This work presents the study, design and measurement of RF circuits aiming communication applications. The need for flexible and reconfigurable RF hardware leads to the need of alternative transmitter architectures. In the center of this innovative architecture, there is thepower oscillator. This circuit is composed of a power amplifier in a positive feedback loop soit oscillates. As the circuit under study is mainly composed of a power amplifier, a study on power amplifier is mandatory. Modern CMOS technologies impose difficulties in the efficient RF generation due to low breakdown voltages. In order to reduce the voltage stress on the transistors, wave form-engineering techniques are used leading to the use of class EF2. Thedesign and measurement of a class EF2 power amplifier and power oscillator are shown. Thecircuits were implemented in standard STMicroelectronics 0.13um CMOS. Correct behaviorfor the circuits was obtained in measurement, leading to a first implementation of class EF2 inRF frequencies. From a system perspective, the proposed architecture is shown to be flexible and able to generate different modulations without change in the hardware. Reconfigurability is shown not only in modulation but also in output power level. The limitations of this architecture are discussed and some mathematical modeling is presented.

Cette thèse s’inscrit dans le domaine de l’amplification de puissance microonde linéaire et haut rendement en technologie GaN. Le premier chapitre décrit le contexte général de l’émission de signaux microondes de puissance pour les télécommunications sans fil, avec un focus particulier apporté sur l’amplificateur de puissance RF. Les différents critères de linéarité et d’efficacité énergétique sont introduits.Le second chapitre présente plus particulièrement la technologie GaN et le transistor de puissance comme brique de base pour l’amplification de puissance microonde. Une revue synthétique des différentes architectures relevées dans la littérature relative à l’amplification à haut rendement est faite.En troisième chapitre, le banc de mesure temporelle d’enveloppe développé et servant de support expérimental à cette étude est présenté. Les procédures d’étalonnage et de synchronisation sont décrites. En illustration, une nouvelle méthode de mesure du NPR large bande est présentée, et validée expérimentalement.Une solution d’amplification adaptative innovante est étudiée dans le quatrième chapitre, et constitue le cœur de ce mémoire. Celle-ci se base sur le contrôle dynamique de la polarisation de grille autour du point de pincement, au rythme de l’enveloppe de modulation. Un démonstrateur d’amplification 10W GaN en bande S (2.5GHz) est développé. Comparativement à la classe B fixe, une forte amélioration de la linéarité est obtenue, sans impact notable sur le rendement moyen de l’amplificateur RF. Finalement, une investigation de la technique proposée pour l’amélioration du rendement du modulateur dans l’architecture d’envelope tracking de drain est menée. / This work deals with linear and high efficiency microwave power amplification in GaN technology.The first chapter is dedicated to the general context of wireless telecommunication with a special emphasis on the RF power amplifier. The most representative figures of merit in terms of linearity and power efficiency are introduced.The second chapter deals more specifically with the GaN technology and GaN-based transistor for microwave power amplification. A description of the principal architectures found in the literature related to high efficiency and linear amplification is summarized.In the third chapter, the developed envelope time-domain test bench is presented. Time-synchronization and envelope calibration procedures are discussed. As an illustration, a new specific wideband NPR measurement is presented and experimentally validated.An innovative power amplifier architecture is presented in the fourth chapter. It is based on a specific dynamic gate biasing technique of the power amplifier biased close to the pinch-off point. A 10W GaN S-band demonstrator has been developed. Compared to fixed class-B conditions, a linearity improvement has been reported without any prohibitive efficiency degradation of the RF power amplifier. Finally, an investigation of the proposed technique for the efficiency improvement in the drain envelope tracking technique is proposed.

Comme toutes modulations multiporteuses, l'OFDM souffre d'une forte variation d'amplitudes qui se traduit par un PAPR élevé. Cette caractéristique de l'OFDM la rend très sensible aux non-linéarités de l'amplificateur de puissance. Pour faire face à cette problématique, on peut surdimensionner l'amplificateur de puissance (solution non efficace en terme de rendement énergétique), linéariser l'amplificateur via les techniques de pré-distorsions, ou réduire le PAPR du signal avant amplification. L'objectif de cette thèse s'inscrit dans cette dernière thématique et plus particulièrement sur les techniques dites d'ajout de signal.Dans cette thèse, après une étude sur l'état de l'art des techniques de réduction du PAPR et en particulier les techniques dites d'ajout de signal, nous avons développé et proposé de nouvelles techniques de réduction du PAPR. Ces contributions s'articulent principalement autour des techniques de Clipping et de la Tone Reservation. / One of the main drawbacks of the OFDM modulation scheme is its high Peak-To-Average Power variation (PAPR) which can induce poor power efficiency at the transmitter amplifier. The digital base band pre-distortion for linearisation of power amplifier and the PAPR mitigation are the most commonly used solution in order to deals with efficiency and linearisation at the high power amplifier. This thesis is focused on the PAPR mitigation solution, and particularly on the adding signal based techniques. The proposed solutions in this report are about improving the Tone Reservation method which is the most popular adding signal based technique for PAPR mitigation, and also the classical clipping method which is the most simple method (in terms of computational complexity) actually.

The ultimate goal of the modern wireless communication industry is the full integration of digital, analog, and radio frequency (RF) functions. The most successful solution for such demands has been complementary metal oxide semiconductor (CMOS) technology, thanks to its cost-effective material and great versatility. Power amplifier (PA), the biggest bottleneck to integrate in a single-chip transceiver in wireless communications, significantly influences overall system performance. Recent advanced wireless communication systems demand a power amplifier that can simultaneously support different communication standards. A fully integrated single-chip tunable CMOS power amplifier is the best solution in terms of the cost and level of integration with other functional blocks of an RF transceiver. This work, for the first time, proposes a fully integrated band-switchable RF power amplifier by using a novel approach towards switching the matching networks. In this approach, which is called Bit Optimized Reconfigurable Network (BORN), two matching networks which can be controlled by digital bits will provide three operating frequency bands for the power amplifier. In order to implementing the proposed BORN PA, a robust high-power RF switch is presented by using resistive body floating technique and 6-terminal triple-well NMOS. The proposed BORN PA delivers measured saturated output power (Psat) of 21.25/22.25/ 23.0dBm at 960MHz/1317MHz/1750MHz, respectively. Moreover, the proposed BORN PA provides respective 3-dB bandwidth of 400MHz/425MHz/550MHz, output 1-dB compression point (P1dB) of 19.5dBm/20.0dBm/21.0dBm, and power-added efficiency (PAE) of 9/11/13% at three targeted frequency bands, respectively. The promising results show that the proposed BORN PA can be a practical solution for RF multiband applications in terms of the cost and level of integration with other functional blocks of an RF transceiver.

Submitted text deals with a power amplifier intended for usage in music electronics. First part is related to the common problems of low-frequency amplifiers including principles and individual circuit wiring types. Next part is related to description of self-made power amplifier including wiring scheme diagram. The end of the text concerns about mechanical construction of mounting box and design of possible module layout inside a device.