No description available.

Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2006. / This thesis investigates to the design, analysis and testing of a Superconducting Programmable Gate Array (SPGA). The objective was to apply existing programmable logic concepts to RSFQ circuits and in the process develop a working prototype of a superconducting programmable logic device. Various programmable logic technologies and architectures were examined and compared to find the best solution. Using Rapid Single Flux Quantum (RSFQ) circuits as building blocks, a complete functional design was assembled incorporating a routing architecture and logic blocks. The Large-Scale Integrated circuit (LSI) layout of the final chip is presented and discussed followed by a discussion on testing. This thesis demonstrates the successful implementation of a fully functional reprogrammable logic device using RSFQ circuitry.

No description available.

Thesis (MTech (Electrical Engineering))--Cape Peninsula University of Technology, 2008. / Includes bibliographical references (leaves 335-340). Also available online.

Thesis (Ph. D.)--University of Washington, 2005. / Vita. Includes bibliographical references (p. 121-130).

Thesis submitted in fulfilment of the requirements for the degree Magister Technologiae: Discipline Electrical Engineering in the Faculty of Engineering at the Cape Peninsula University of Technology 2008 / As one of the biggest developing country in the world, South Africa is developing very fast resent years. The country’s industrialization process is rapidly evolved. The manufacturing industry as one of the most important sections of the industrialization is playing a very heavy role in South Africa’s economic growth. Big percentage of population is involved in the manufacturing industry. It is necessary to keep and enhance the competitiveness of the South Africa’s manufacturing industry in the world wide. But the manufacturing companies are facing with unpredictable market demands and global competitions. To overcome these challenges, the manufacturing companies need to produce new products which can cater to the market demand as soon as possible. Reconfigurable Manufacturing System (RMS) is one of the possible solutions for the manufacturing companies to produce the suitable product for the market in a short period of time with low cost and flexibility. That is because the RMS can be reconfigured easily according to the required specifications for manufacturing the appropriate product for the market and with above mentioned characteristics. Now, RMS is considered as one of the promising concepts for mass production. As one of the very latest research fields, many companies, universities and institutions have been involved to design and develop RMSs. South Africa as one of the most important manufacturing country in the world, her own universities and researchers has the obligation to study this field and follow the newest development steps. In this project, a lab-scaled reconfigurable plant and a Field Programmable Gate Array (FPGA) technology based reconfigurable controller are used to realize and verify the concepts of the RMS in order to find the methodology of developing RMSs. The lab-scaled reconfigurable plant can be reconfigured into the inverted pendulum and the overhead crane. Although it is not used for manufacturing purpose, it can be used to verify the RMS concepts and the control strategies applied to it. Furthermore, control of the inverted pendulum and the overhead crane are both typical problems in the control field. It is meaningful to develop the controllers for them. As the reconfigurable plant is configured, the reconfigurable controller is reconfigured synchronously in order to produce the proper control signal for the reconfigured plant. In this project, both linear and nonlinear control strategies are deployed. Good results are received. The outcomes of the project are mainly for the education and fundamental research purposes, but the developed control strategies have significant sense towards the military missile guidance and the overhead crane operation in industry.

No description available.

Thesis (M.Eng.)--Memorial University of Newfoundland, 1999. / Bibliography: leaves 100-102.

Placement is one of the most important steps in physical design for VLSI circuits. For field programmable gate arrays (FPGAs), the placement step determines the location of each logic block. I present novel timing and congestion driven placement algorithms for FPGAs with minimal runtime overhead. By predicting the post-routing timing-critical edges and estimating congestion accurately, this algorithm is able to simultaneously reduce the critical path delay and the minimum number of routing tracks. The core of the algorithm consists of a criticality-history record of connection edges and a congestion map. This approach is applied to the 20 largest Microelectronics Center of North Carolina (MCNC) benchmark circuits. Experimental results show that compared with the state-of-the-art FPGA place and route package, the Versatile Place and Route (VPR) suite, this algorithm yields an average of 8.1% reduction (maximum 30.5%) in the critical path delay and 5% reduction in channel width. Meanwhile, the average runtime of the algorithm is only 2.3X as of VPR.

The realisation of signal processing algorithms in fixed-point offers substantial performance advantages over floating-point realisations. However, it is widely acknowledged that the task of realising algorithms in fixed-point is a challenging one with limited tool support. This thesis examines various aspects related to the translation of algorithms, given in infinite precision or floating-point, into fixed-point. In particular, this thesis reports on the implementation of a given algorithm, an EDFA (Erbium-Doped Fibre Amplifier) control algorithm, on a FPGA (Field Programmable Gate Array) using fixed-point arithmetic. An analytical approach is proposed that allows the automated realisation of algorithms in fixedpoint. The technique provides fixed-point parameters for a given floating-point model that satisfies a precision constraint imposed on the primary output of the algorithm to be realised. The development of a simulation framework based on this analysis allows fixed-point designs to be generated in a shorter time frame. Albeit being limited to digital algorithms that can be represented as a data flow graph (DFG), the approach developed in the thesis allows for a speed up in the design and development cycle, reduces the possibility of error and eases the overall effort involved in the process. It is shown in this thesis that a fixed-point realisation of an EDFA control algorithm using this technique produces results that satisfy the given constraints.