This paper details the design and simulation of a fault-tolerant Quantum-dot Cellular Automata (QCA) NOT gate. A version of the standard NOT gate can be constructed to take advantage to the ability to easily integrate redundant structures into a QCA design. The fault-tolerant characteristics of this inverter are analyzed with QCADesigner v2.0.3 (Windows version) simulation software. These characteristics are then compared with the characteristics of two other non-redundant styles of NOT gates. The redundant version of the gate is more robust than the standard style for the inverter. However, another simple inverter style seems to be even more than this fault-tolerant design. Both versions of the gate will need to be studied further in the future to determine which design is most practical. / Thesis (M.S.)--Wichita State University, College of Engineering, Dept. of Electrical and Computer Engineering / "July 2006." / Includes bibliographic references (leaves 31-33)

Conventional CMOS (the current dominant technology for VLSI) implemented with ever smaller transistors is expected to encounter serious problems in the near future with the need for difficult fabrication technologies. The most important problem is heat generation. The desire for device density, power dissipation and performance improvement necessitates new technologies that will provide innovative solutions to integration and computations. Nanotechnology, especially Quantum-dot Cellular Automata (QCA) provides new possibilities for computing owing to its unique properties. Numerous nanoelectronic devices are being investigated and many experimental devices have been developed. Thus, high level circuit design is needed to keep pace with changing physical studies. The circuit design aspects of QCA have not been studied much because of its novelty. Arithmetic units, especially multipliers and dividers play an important role in the design of digital processors and application specific systems. Therefore, designs for parallel multipliers and dividers are presented using this technology. Optimal design of parallel multipliers for Quantum-Dot Cellular Automata is explored in this dissertation. As a main basic element to build multipliers, adders are implemented and compared their performances with previous adders. And two different layout schemes that single layer and multi-layer wire crossings are compared and analyzed. This dissertation proposes three kinds of multipliers. Wallace and Dadda parallel multipliers, quasi-modular multipliers, and array multipliers are designed and simulated with several different operand sizes. Also array multipliers that are well suited in QCA are constructed and formed by a regular lattice of identical functional units so that the structure is conformable to QCA technology without extra wire delay. All these designs are constructed using coplanar layouts and compared with other QCA multipliers. The delay, area and complexity are compared for several different operand sizes. This research also studies divider designs for quantum-dot cellular automata. A digit recurrence restoring binary divider is a conventional design that serves as a baseline. By using controlled full subtractor cell units, a relatively simple and efficient implementation is realized. The Goldschmidt divider using the new architecture (data tag method) to control the various elements of the divider is compared for the performance. / text

This thesis focuses on reducing the delay of non-restoring division. Although the digit recurrence division is lower in complexity and occupies a smaller area than division by convergence, it has a drawback: slow division speed. To mitigate this problem, two modification ideas are proposed here for the non-restoring division, the fastest division algorithm of the digit recurrence division methods. For the first proposed approach, the delay of the multiplexer for selecting the quotient digit and determining the way to calculate the partial remainder can be reduced through inverting the order of its flowchart. Second, one adder and one inverter can be removed by using a new quotient digit converter. To prove these ideas are valid, the simulation results comparing the modified non-restoring division and the standard non-restoring division are provided. / text

This dissertation focuses on improving the division-by-convergence algorithm. While the division by convergence algorithm has many advantages, it has some drawbacks, such as a need for extra bits in the multiplier and a large ROM table for the initial approximation. To mitigate these problems, two new methods are proposed here. In addition, the research scope is extended to seek an efficient architecture for implementing a divider with Quantum-dot Cellular Automata (QCA), an emerging technology. For the first proposed approach, a new rounding method to reduce the required precision of the multiplier for division by convergence is presented. It allows twice the error tolerance of conventional methods and inclusive error bounds. The proposed method further reduces the required precision of the multiplier by considering the asymmetric error bounds of Goldschmidt dividers. The second proposed approach is a method to increase the speed of convergence for Goldschmidt division using simple logic circuits. The proposed method achieves nearly cubic convergence. It reduces the logic complexity and delay by using an approximate squarer with a simple logic implementation and a redundant binary Booth recoder. Finally, a new architecture for division-by-convergence in QCA is proposed. State machines for QCA often have synchronization problems due to the long wire delays. To resolve this problem, a data tag method is proposed. It also increases the throughput significantly since multiple division computations can be performed in a time skewed manner using one iterative divider. / text

Since its inception, Moore's Law has been a reliable predictor of computational power. This steady increase in computational power has been due to the ability to fit increasing numbers of transistors in a single chip. A consequence of increasing the number of transistors is also increasing the power consumption. The physical properties of CMOS technologies will make this powerwall unavoidable and will result in severe restrictions to future progress and applications. A potential solution to the problem of rising power demands is to investigate alternative low power nanotechnologies for implementing logic circuits. The intrinsic properties of these emerging nanotechnologies result in them being low power in nature when compared to current CMOS technologies. This thesis specifically highlights quantum dot celluar automata (QCA) and nanomagnetic logic (NML) as just two possible technologies. Designs in NML and QCA are explored for simple arithmetic units such as full adders and subtractors. A new multilayer 5-input majority gate design is proposed for use in NML. Designs of reversible adders are proposed which are easily testable for unidirectional stuck at faults.

The increasing need for low power and stunningly fast devices in Complementary Metal Oxide Semiconductor Very large Scale Integration (CMOS VLSI) circuits, directs the stream towards scaling of the same. However scaling at sub-micro level and nano level pose quantum mechanical effects and thereby limits further scaling of CMOS circuits. Researchers look into new aspects in nano regime that could effectively resolve this quandary. One such technology that looks promising at nano-level is the quantum dot cellular automata (QCA). The basic operation of QCA is based on transfer of charge rather than the electrons itself. The wave nature of these electrons and their uncertainty in device operation demands a probabilistic approach to study their operation. The data is assigned to a QCA cell by positioning two electrons into four quantum dots. However the site in which the electrons settles is uncertain and depends on various factors. In an ideal state, the electrons position themselves diagonal to each other, through columbic repulsion, to a low energy state. The quantum cell is said to be polarized to +1 or -1, based on the alignment of the electrons. In this thesis, we put forth a probabilistic model to design sequential QCA in Bayesian networks. The timing constraints inherent in sequential circuits due to the feedback path, makes it difficult to assign clock zones in a way that the outputs arrive at the same time instant. Hence designing circuits that have many sequential elements is time consuming. The model presented in this paper is fast and could be used to design sequential QCA circuits without the need to align the clock zones. One of the major advantages of our model lies in its ability to accurately capture the polarization of each cell of the sequential QCA circuits. We discuss the architecture of some of the basic sequential circuits such as J-K flip flop (FF), RAM memory cell and s27 benchmark circuit designed in QCADesigner. We analyze the circuits using a state-of-art Dynamic Bayesian Networks (DBN). To our knowledge this is the first time sequential circuits are analyzed using DBN. For the first time, Estimated Posterior Importance Sampling Algorithm (EPIS) is used to determine the probabilistic values, to study the effect due to variations in physical dimension and operating temperature on output polarization in QCA circuits.

As CMOS scaling faces a technological barrier in the near future, novel design paradigms are being proposed to keep up with the ever growing need for computation power and speed. Most of these novel technologies have device sizes comparable to atomic and molecular scales. At these levels the quantum mechanical effects play a dominant role in device performance, thus inducing uncertainty. The wave nature of particle matter and the uncertainty associated with device operation make a case for probabilistic modeling of the device. As the dimensions go down to a molecular scale, functioning of a nano-device will be governed primarily by the atomic level device physics. Modeling a device at such a small scale will require taking into account the quantum mechanical phenomenon inherent to the device. In this dissertation, we studied one such nano-device: Quantum-Dot Cellular Automata (QCA). We used probabilistic modeling to perform a fast approximation based method to estimate error, power and reliability in large QCA circuits. First, we associate the quantum mechanical probabilities associated with each QCA cell to design and build a probabilistic Bayesian network. Our proposed modeling is derived from density matrix-based quantum modeling, and it takes into account dependency patterns induced by clocking. Our modeling scheme is orders of magnitude faster than the coherent vector simulation method that uses quantum mechanical simulations. Furthermore, our output node polarization values match those obtained from the state of the art simulations. Second, we use this model to approximate power dissipated in a QCA circuit during a non-adiabatic switching event and also to isolate the thermal hotspots in a design. Third, we also use a hierarchical probabilistic macromodeling scheme to model QCA designs at circuit level to isolate weak spots early in the design process. It can also be used to compare two functionally equivalent logic designs without performing the expensive quantum mechanical simulations. Finally, we perform optimization studies on different QCA layouts by analyzing the designs for error and power over a range of kink energies.To the best of our knowledge the non-adiabatic power model presented in this dissertation is the first work that uses abrupt clocking scheme to estimate realistic power dissipation. All prior works used quasi-adiabatic power dissipation models. The hierarchical macromodel design is also the first work in QCA design that uses circuit level modeling and is faithful to the underlying layout level design. The effect of kink energy to study power-error tradeoffs will be of great use to circuit designers and fabrication scientists in choosing the most suitable design parameters such as cell size and grid spacing.

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